DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 8, 2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 2, 4-8, 10, 12-17, 19, 20, 33, 34 and 37-49 have been considered but are moot on grounds of new rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Darwish (US 2012/0161226 A1 now US 8,546,878 B2).
In regards to claim 1, Darwish (Figs. 43A, 43B, 37A, 1B, 2A, 2B, 6, 2B, 44J-44L and associated text and items) discloses a p-type semiconductor layer (item P-body) including n-type semiconductor regions (n+ regions); and a trench isolation structure (item 4310) laterally surrounding the p-type semiconductor layer (item P-body), and wherein any n-type semiconductor region (n+ regions) disposed within the p- type semiconductor layer (item P-body) that is laterally surrounded by the trench isolation structure (item 4310) has: a footprint (footprint of n+ regions) with a circular, oval, or obround shape (shape of n+ regions); a uniform size (uniform size of n+ regions) throughout the p-type semiconductor layer (item P-body) such that each n-type semiconductor region (n+ regions) has the same uniform size (uniform size of n+ regions) throughout the p-type semiconductor layer (item P-body); a boundary (boundary of n+ regions) of the footprint (footprint of n+ regions) spaced apart from the trench isolation structure (item 4310) that laterally surrounds the p-type semiconductor layer (item P-body).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to include a footprint with a circular, oval, or obround shape, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oliveri et al. in U.S. Patent 5,032,887 (hereinafter Oliveri) in view of Darwish (US 2012/0161226 A1 now US 8,546,878 B2).
In regards to claim 10, Oliveri teaches in FIGS. 1-4 and related text, a semiconductor device, comprising: an n-type substrate (N+ layer, FIG. 3, [col.3, lines 33-34]);
an n-type layer (N- layer, FIG. 3, [col. 3, lines 34-35]) on the n-type substrate (N+ layer);
a p-type layer (1, FIG. 3, [col. 3, line 39]) over the n-type layer (N- layer); and
a first area (area of FIG. 4, area excluding regions 5 and 7) including a plurality of n-type regions (2, FIGS. 3 and 4, [col. 3, line 42]) in the p-type layer (1), wherein each of the n-type regions (2) has: a footprint with a circular, oval, or obround shape (circular; FIGS. 2b and 4, since oxide ring 3 has a ring shape with an inner/outer diameter, [col. 4, lines 64-68]);
a boundary of the footprint spaced apart from a first structure (10); and
a first group of contacts (6/9, FIG. 3, [col. 4, lines 11 and 41]) connected to the n-type region (2)
Oliveri does not explicitly state that each of the n-type regions has a uniform size throughout the p-tvpe layer such that each n-type region has the same uniform size throughout the p-tvpe layer; and the first structure is a first isolation structure that surrounds the first area.
However, Oliveri’s FIG. 4 appears to depict that each of the n-type regions (2, excluding n-type regions in bond pad region 7) has a uniform size throughout the p-type layer (1) such that each n-type region (2) has the same uniform size throughout the p-type layer. Furthermore, Oliveri’s FIG. 3 suggests first structure 10 is an insulating (isolation) structure that surrounds the first area.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Oliveri such that:
each of the n-type regions has a uniform size throughout the p-type layer such that each n-type region has the same uniform size throughout the p-type layer, in order to simplify the manufacturing process; and
2) structure 10 is an isolation structure that surrounds the p-type layer, in order to simplify the manufacturing process and provide better protection/isolation to the device.
Darwish (Figs. 43A, 43B, 37A, 1B, 2A, 2B, 6, 2B, 44J-44L and associated text and items) discloses a p-type layer (item P-body) over an n-type layer (item 4301) including a first trench isolation structure (item 4310) laterally surrounding the p-type layer (item P-body) such that an outer perimeter of the first area is defined by the first trench isolation structure (item 4310), and n-type regions (n+ regions) disposed in the p-type layer (item P-body) within the first area, wherein any n-type region (n+ regions) disposed in the p-type layer (item P-body) within the first area has: a footprint (footprint of n+ regions) with a circular, oval, or obround shape (shape of n+ regions); a uniform size (uniform size of n+ regions) throughout the p-type layer (item P-body) such that each n-type region (n+ regions) has the same uniform size (uniform size of n+ regions) throughout the p-type layer (item P-body); a boundary (boundary of n+ regions) of the footprint (footprint of n+ regions) spaced apart from the first trench isolation structure (item 4310) that laterally surrounds the first area.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Darwish, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
Claim(s) 1, 2, 4-8, 10, 12-20, 22, and 38 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oliveri et al. in U.S. Patent 5,032,887 (hereinafter Oliveri) OR over Oliveri in view of Strachan et al. in US 2017/0200712 A1 (hereinafter Strachan) in view of Darwish (US 2012/0161226 A1 now US 8,546,878 B2).
Regarding claim 1, Oliveri teaches in FIGS. 1-4 and related text, a semiconductor device, comprising: a p-type semiconductor layer (1, FIG. 3, [col. 3, line 39]) including a plurality of n-type semiconductor regions (2, FIGS. 3 and 4, [col. 3, line 42], and excluding n-type regions in bond pad region 7), wherein each of the n-type semiconductor regions (2) has:
a footprint with a circular, oval, or obround shape (circular; FIGS. 2b and 4, since oxide ring 3 has a ring shape with an inner/outer diameter, [col. 4, lines 64-68]);
a boundary of the footprint spaced apart from a structure (10); and
a group of contacts (6/9, FIG. 3, [col. 4, lines 11 and 41]) connected to the n-type semiconductor region (2).
Oliveri does not explicitly state: wherein each of the n-type semiconductor regions has a uniform size throughout the p-type semiconductor layer such that each n-type semiconductor region has the same uniform size throughout the p-type semiconductor layer; and that structure 10 is an isolation structure that surrounds the p-type semiconductor layer.
However, Oliveri’s FIG. 4 appears to depict that each of the n-type semiconductor regions (2, excluding n-type regions in bond pad region 7) has a uniform size throughout the p-type semiconductor layer (1) such that each n-type semiconductor region (2) has the same uniform size throughout the p-type semiconductor layer. Furthermore, Oliveri’s FIG. 3 suggests structure 10 is an insulating (isolation) structure that surrounds the p-type semiconductor (1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Oliveri such that:
each of the n-type semiconductor regions has a uniform size throughout the p-type semiconductor layer such that each n-type semiconductor region has the same uniform size throughout the p-type semiconductor layer, in order to simplify the manufacturing process; and
2) structure 10 is an isolation structure that surrounds the p-type semiconductor layer, in order to simplify the manufacturing process and provide better protection/isolation to the device.
In the alternative, Strachan teaches in FIG. 1 and related text, an isolation structure (108, [0013]) that laterally surrounds a p-type semiconductor layer (106, [0012]), wherein any n-type semiconductor region (126, 128 or 126 plus 128) disposed within the p-type semiconductor layer (item 106) that is laterally surrounded by the isolation structure (108, [0013]) has: a footprint with a shape (shape of items 126, 128 or 126 plus 128), a boundary of the footprint (boundary of items 126, 128 or 126 plus 128) spaced apart from the isolation structure (item 108) that laterally surrounds the p-type semiconductor layer (item 106).
Oliveri and Strachan are analogous art to the claimed invention because they both are directed at bipolar semiconductor devices, and one of ordinary skill in the art would have had a reasonable expectation of success to modify Oliveri in view of Strachan because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Oliveri such that the structure 10 is an isolation structure that surrounds the p-type semiconductor layer, as taught by Strachan, in order to provide isolation and protection to the device.
Oliveri as modified by Stachan does not specifically disclose a uniform size throughout the p-type smeiconductor layer such that each n-type semiconductor region has the same uniform size throughout the p-type semiconductor layer.
Darwish (Figs. 43A, 43B, 37A, 1B, 2A, 2B, 6, 2B, 44J-44L and associated text and items) discloses a p-type semiconductor layer (item P-body) including a plurality of n-type semiconductor regions (n+ regions); and a trench isolation structure (item 4310) laterally surrounding the p-type semiconductor layer (item P-body), and wherein any n-type semiconductor region (n+ regions) disposed within the p- type semiconductor layer (item P-body) that is laterally surrounded by the trench isolation structure (item 4310) has: a footprint (footprint of n+ regions) with a circular, oval, or obround shape (shape of n+ regions); a uniform size (uniform size of n+ regions) throughout the p-type semiconductor layer (item P-body) such that each n-type semiconductor region (n+ regions) has the same uniform size (uniform size of n+ regions) throughout the p-type semiconductor layer (item P-body); a boundary (boundary of n+ regions) of the footprint (footprint of n+ regions) spaced apart from the trench isolation structure (item 4310) that laterally surrounds the p-type semiconductor layer (item P-body).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Darwish, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
Regarding claim 2, Oliveri as modified by Strachan teaches the semiconductor device of claim 1. Strachan further teaches wherein the trench isolation structure (108) includes a dielectric liner (110, [0013]) and a conductive material (112, [0013]) formed thereon.
Oliveri and Strachan are analogous art to the claimed invention because they both are directed at bipolar semiconductor devices, and one of ordinary skill in the art would have had a reasonable expectation of success to modify Oliveri in view of Strachan because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Oliveri such that the structure 10 is an isolation structure that surrounds the p-type semiconductor layer, and wherein the isolation structure has a dielectric liner and a conductive material formed thereon, as taught by Strachan, in order to provide isolation and protection to the device.
Regarding claim 4, Oliveri as modified by Strachan teaches the semiconductor device of claim 1. Oliveri further teaches wherein the p-type semiconductor layer (1) corresponds to a first p-type semiconductor layer, the semiconductor device further comprising:
a first n-type semiconductor layer on which the p-type semiconductor layer is located (N- layer, FIG. 3); and a second n-type semiconductor layer (N layer, FIG. 3) on which the first n-type semiconductor layer (N- layer, FIG. 3) is located, the second n-type semiconductor layer (N layer) having a greater n- type dopant concentration than the first n-type semiconductor layer (N- layer).
Oliveri does not teach the semiconductor device further comprising: a second p-type semiconductor layer on which the first p-type semiconductor layer is located, the second p-type semiconductor layer having a greater p- type dopant concentration than the first p-type semiconductor layer.
Strachan teaches in FIG. 1 and related text, wherein a p-type semiconductor layer (106) corresponds to a first p-type semiconductor layer, the semiconductor device further comprising: a second p-type semiconductor layer (120, [0014]) on which the first p-type semiconductor layer (106) is located, the second p-type semiconductor layer (106) having a greater p- type dopant concentration than the first p-type semiconductor layer (layer 120 has a doping concentration greater than 1e17
c
m
-
3
; [0014], and layer 106 has a doping concentration less than 1e15
c
m
-
3
; [0012]).
Oliveri and Strachan are analogous art to the claimed invention because they both are directed at bipolar semiconductor devices, and one of ordinary skill in the art would have had a reasonable expectation of success to modify Oliveri in view of Strachan because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Oliveri to include a second p-type semiconductor layer on which the first p-type semiconductor layer is located, the second p-type semiconductor layer having a greater p- type dopant concentration than the first p-type semiconductor layer, in order to provide an LR-LC diode device with adjustable breakdown voltage (Strachan, [0016]).
Regarding claim 5, Oliveri as modified by Strachan teaches the semiconductor device of claim 4. Oliveri further teaches a plurality of first pn junctions is formed at a first depth from a surface of the first p-type semiconductor layer (1, FIG. 3), the plurality of first pn junctions being across the plurality of n-type semiconductor regions (2) of the plurality and the first p-type semiconductor layer (1).
The combined structure of Oliveri and Strachan teaches a second pn junction is formed at a second depth from the surface greater than the first depth, the second pn junction being across the second p-type semiconductor layer and the first n-type semiconductor layer.
Regarding claim 6, Oliveri as modified by Strachan teaches the semiconductor device of claim 4. Oliveri does not explicitly state wherein the of n-type semiconductor regions, the first and second p-type semiconductor layers, and the first n-type semiconductor layer form an open-base npn bipolar transistor.
Strachan teaches in FIG. 1 and related text, wherein an n-type semiconductor region (122/126/128, [0014]), first and second p-type semiconductor layers (106, 120, [0014]), and an n-type semiconductor layer (102, [0015]) form an open-base npn bipolar transistor (the n-type layers are coupled to terminals but the p-type layers are not directly coupled to terminals).
Oliveri and Strachan are analogous art to the claimed invention because they both are directed at bipolar semiconductor devices, and one of ordinary skill in the art would have had a reasonable expectation of success to modify Oliveri in view of Strachan because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined structure of Oliveri and Strachan such that the plurality of n-type semiconductor regions, the first and second p-type semiconductor layers, and the first n-type semiconductor layer form an open-base npn bipolar transistor, as taught by Strachan, in order to provide an LR-LC diode device with adjustable breakdown voltage (Strachan, [0016]).
Regarding claim 7, Oliveri as modified by Strachan teaches the semiconductor device of claim 6. Oliveri further teaches wherein: the group of contacts (6/9) is coupled to a terminal (emitter bond pad area 7, [col. 4, lines 44-46]);
Oliveri does not teach the terminal corresponds to a first terminal of the open-base npn bipolar transistor; and the second n-type semiconductor layer corresponds to a second terminal of the open-base npn bipolar transistor.
Strachan teaches in FIG. 1 and related text, a terminal (138, [0022]) corresponds to a first terminal of the open-base npn bipolar transistor; and a second n-type semiconductor layer (102) corresponds to a second terminal (102 is coupled to terminal 140, [0022]) of the open-base npn bipolar transistor.
Oliveri and Strachan are analogous art to the claimed invention because they both are directed at bipolar semiconductor devices, and one of ordinary skill in the art would have had a reasonable expectation of success to modify Oliveri in view of Strachan because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined structure of Oliveri and Strachan such that the plurality of n-type semiconductor regions, the first and second p-type semiconductor layers, and the first n-type semiconductor layer form an open-base npn bipolar transistor, as taught by Strachan, in order to provide an LR-LC diode device with adjustable breakdown voltage (Strachan, [0016]).
Regarding claim 8, Oliveri as modified by Strachan teaches the semiconductor device of claim 4. The combined structure of Oliveri and Strachan further teaches wherein the trench isolation structure extends from a surface of the first p-type semiconductor layer past an interface between the first and the second n-type semiconductor layers.
In regards to claim 10, Oliveri teaches in FIGS. 1-4 and related text, a semiconductor device, comprising: an n-type substrate (N+ layer, FIG. 3, [col.3, lines 33-34]);
an n-type layer (N- layer, FIG. 3, [col. 3, lines 34-35]) on the n-type substrate (N+ layer);
a p-type layer (1, FIG. 3, [col. 3, line 39]) over the n-type layer (N- layer); and
a first area (area of FIG. 4, area excluding regions 5 and 7) including a plurality of n-type regions (2, FIGS. 3 and 4, [col. 3, line 42]) in the p-type layer (1), wherein each of the n-type regions (2) has: a footprint with a circular, oval, or obround shape (circular; FIGS. 2b and 4, since oxide ring 3 has a ring shape with an inner/outer diameter, [col. 4, lines 64-68]);
a boundary of the footprint spaced apart from a first structure (10); and
a first group of contacts (6/9, FIG. 3, [col. 4, lines 11 and 41]) connected to the n-type region (2)
Oliveri does not explicitly state that each of the n-type regions has a uniform size throughout the p-tvpe layer such that each n-type region has the same uniform size throughout the p-tvpe layer; and the first structure is a first isolation structure that surrounds the first area.
However, Oliveri’s FIG. 4 appears to depict that each of the n-type regions (2, excluding n-type regions in bond pad region 7) has a uniform size throughout the p-type layer (1) such that each n-type region (2) has the same uniform size throughout the p-type layer. Furthermore, Oliveri’s FIG. 3 suggests first structure 10 is an insulating (isolation) structure that surrounds the first area.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Oliveri such that:
each of the n-type regions has a uniform size throughout the p-type layer such that each n-type region has the same uniform size throughout the p-type layer, in order to simplify the manufacturing process; and
2) structure 10 is an isolation structure that surrounds the p-type layer, in order to simplify the manufacturing process and provide better protection/isolation to the device.
In the alternative, Strachan teaches in FIG. 1 and related text, a first trench isolation structure (108, [0013]) that laterally surrounding a p-type layer (106, [0012]) such that an outer perimeter of a first area is defined by the first trench isolation structure (item 108), n-type regions (126, 128 or 126 plus 128) disposed in the p-type layer (item 106) within the first area has: a footprint with a shape (shape of items 126, 128 or 126 plus 128), a boundary of the footprint (boundary of items 126, 128 or 126 plus 128) spaced apart from the trench isolation structure (item 108) that laterally surrounds the first area.
Oliveri and Strachan are analogous art to the claimed invention because they both are directed at bipolar semiconductor devices, and one of ordinary skill in the art would have had a reasonable expectation of success to modify Oliveri in view of Strachan because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Oliveri such that the structure 10 is an isolation structure that surrounds the p-type semiconductor layer, as taught by Strachan, in order to provide isolation and protection to the device.
Oliveri as modified by Stachan does not specifically disclose a uniform size throughout the p-type layer such that each n-type region has the same uniform size throughout the p-type layer.
Darwish (Figs. 43A, 43B, 37A, 1B, 2A, 2B, 6, 2B, 44J-44L and associated text and items) discloses a p-type layer (item P-body) over an n-type layer (item 4301) including a a first trench isolation structure (item 4310) laterally surrounding the p-type layer (item P-body) such that an outer perimeter of the first area is defined by the first trench isolation structure (item 4310), and n-type regions (n+ regions) disposed in the p-type layer (item P-body) within the first area, wherein any n-type region (n+ regions) disposed in the p-type layer (item P-body) within the first area has: a footprint (footprint of n+ regions) with a circular, oval, or obround shape (shape of n+ regions); a uniform size (uniform size of n+ regions) throughout the p-type layer (item P-body) such that each n-type region (n+ regions) has the same uniform size (uniform size of n+ regions) throughout the p-type layer (item P-body); a boundary (boundary of n+ regions) of the footprint (footprint of n+ regions) spaced apart from the first trench isolation structure (item 4310) that laterally surrounds the first area.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Darwish, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
Regarding claim 12, Oliveri as modified by Strachan teaches the semiconductor device of claim 10. Oliveri further teaches wherein the p-type layer (1) and the n-type regions (2) forms a plurality of first pn junctions at a first depth from a surface of the p-type layer (1) that faces away from the n-type substrate (N+ layer, FIG. 3).
Regarding claim 13, Oliveri as modified by Strachan teaches the semiconductor device of claim 12. Oliveri further teaches wherein the first area (area of FIG. 4, area excluding regions 5 and 7) further includes a second pn junction (junction between p-type layer 1 and n-type layer N- in FIG. 3) at a second depth from the surface greater than the first depth, the second pn junction formed across the n-type layer (N- layer, FIG. 3) and the p-type layer (1).
Oliveri does not teach the second pn junction formed across the n-type layer and a p-type buried region extended from the p-type layer toward the n-type substrate.
Strachan teaches in FIG. 1 and related text, a second pn junction (130) formed across an n-type layer (102, [0012]) and a p-type buried region (120, [0014]) extended from a p-type layer (106, [0012]) toward an n-type substrate (102).
Oliveri and Strachan are analogous art to the claimed invention because they both are directed at bipolar semiconductor devices, and one of ordinary skill in the art would have had a reasonable expectation of success to modify Oliveri in view of Strachan because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Oliveri to include a p-type buried region to create a second pn junction formed across the n-type layer and a p-type buried region extended from the p-type layer toward the n-type substrate, in order to provide an LR-LC diode device with adjustable breakdown voltage (Strachan, [0016]).
Regarding claim 14, Oliveri as modified by Strachan teaches the semiconductor device of claim 13. Oliveri does not explicitly state wherein the plurality of n-type regions, the p-type layer, the p-type buried region, and the n-type layer form an open- base npn bipolar transistor.
Strachan teaches in FIG. 1 and related text, wherein an n-type region (122/126/128, [0014]), a p-type layer (106), a p-type buried region(120), and an n-type layer (102) form an open-base npn bipolar transistor (the n-type layers are coupled to terminals but the p-type layers are not directly coupled to terminals).
Oliveri and Strachan are analogous art to the claimed invention because they both are directed at bipolar semiconductor devices, and one of ordinary skill in the art would have had a reasonable expectation of success to modify Oliveri in view of Strachan because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined structure of Oliveri and Strachan such that the plurality of n-type regions, the p-type layer, the p-type buried region, and the n-type layer form an open- base npn bipolar transistor, as taught by Strachan, in order to provide an LR-LC diode device with adjustable breakdown voltage (Strachan, [0016]).
Regarding claim 15, Oliveri as modified by Strachan teaches the semiconductor device of claim 13. Oliveri does not teach further comprising: a second area located next to the first area, the second area including: a p-type region in the p-type layer; and a second group of contacts connected to the p-type region; and a second trench isolation structure laterally surrounding the second area.
Strachan teaches in FIG. 1 and related text, a second area (area of 116, [0013]) located next to a first area (area of 114, [0013]), the second area (area of 116) including:
a p-type region (134, [0021]) in a p-type layer (106, [0021]); and a second group of contacts (contacts coupled to terminal 138, [0022]) connected to the p-type region (134); and
a second trench isolation structure (108, [0013]) laterally surrounding the second area (area of 116).
Oliveri and Strachan are analogous art to the claimed invention because they both are directed at bipolar semiconductor devices, and one of ordinary skill in the art would have had a reasonable expectation of success to modify Oliveri in view of Strachan because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined structure of Oliveri and Strachan to include a second area located next to the first area, the second area including: a p-type region in the p-type layer; and a second group of contacts connected to the p-type region; and a second isolation structure surrounding the second area, as taught by Strachan, in order to construct parallel diode as a component of a bidirectional diode device (Strachan, [0013]).
Regarding claim 16, Oliveri as modified by Strachan teaches the semiconductor device of claim 15. Strachan further teaches wherein the second area (area of 116) includes a third pn junction (136, [0021]) at a third depth from the surface greater than a first depth (depth of PN junction 132, [0015]) and less than a second depth (depth of pn unction 130, [0015]), the third pn junction (136) formed across a p-type layer (106) and an n-type layer (104, [0012]).
Oliveri and Strachan are analogous art to the claimed invention because they both are directed at bipolar semiconductor devices, and one of ordinary skill in the art would have had a reasonable expectation of success to modify Oliveri in view of Strachan because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined structure of Oliveri and Strachan to include a second area located next to the first area, wherein the second area includes a third pn junction at a third depth from the surface greater than the first depth and less than the second depth, the third pn junction formed across the p-type layer and the n-type layer, as taught by Strachan, in order to construct parallel diode as a component of a bidirectional diode device (Strachan, [0013]).
Regarding claim 17, Oliveri as modified by Strachan teaches the semiconductor device of claim 15. Strachan further teaches wherein the first and second isolation structures (108) extend from the surface past an interface between an n-type layer (104) and an n-type substrate (102).
Regarding claim 19, Oliveri as modified by Strachan teaches the semiconductor device of claim 15. Oliveri further teaches wherein the first group of contacts (6/9) is connected to a terminal (emitter bond pad area 7, [col. 4, lines 44-46]).
Strachan teaches wherein the second group of contacts (contacts coupled to terminal 138, [0022]) is connected to a terminal (138).
Regarding claim 20, Oliveri as modified by Strachan teaches the semiconductor device of claim 15. Oliveri further teaches wherein: the first group of contacts (6/9) of the first area is connected to a first terminal (emitter bond pad area 7).
Strachan further teaches wherein the second group of contacts (contacts coupled to terminal 138) of the second area is connected to a second terminal (also connected to terminal 140 when the device is in operation, [0022]).
Regarding claim 38, Oliveri as modified by Strachan teaches the semiconductor device of claim 1. Oliveri further teaches wherein each group of contacts (6/7) from each n-type semiconductor region (2) are coupled to a terminal (emitter bond pad area 7, [col. 4, lines 44-46]).
Claims 33-37, 39, and 40 are rejected under 35 U.S.C. 103 as being unpatentable over Oliveri et al. in U.S. Patent 5,032,887 (hereinafter Oliveri) and Strachan et al. in US 2017/0200712 A1 (hereinafter Strachan) in view of Darwish (US 2012/0161226 A1 now US 8,546,878 B2) as applied to the claims above, and further in view of Wang et al. in US 2018/0047717 A1 (hereinafter Wang).
Regarding claim 33, Oliveri as modified by Strachan substantially teaches the entire claimed semiconductor device of claim 1.
Oliveri further teaches wherein the p-type semiconductor layer (1) interfaces with each the n- type semiconductor regions (2) from the plurality of n-type semiconductor regions.
Oliveri as modified by Strachan and Darwish (Figs. 43A, 43B, 37A, 1B, 2A, 2B, 6, 2B, 44J-44L and associated text and items) discloses further comprising a p-type region (item p+) disposed in the p-type semiconductor layer (item P-body), wherein: at least one of the n-type semiconductor regions (n+ regions) from the plurality of n- type semiconductor regions (n+ regions) interfaces with the p-type region (item p+), but does not specifically disclose the p-type region having a different p-type dopant concentration than the p-type semiconductor layer;
Wang teaches in FIG. 7f and related text, a p-type region (132, [0078]) disposed in a p-type semiconductor layer (112, [0078]), the p-type region (132) having a different p-type dopant concentration than the p-type semiconductor layer (112, [0078]); and wherein: at least one of an n-type semiconductor region (123, [0055]) interfaces with the p-type region (132).
Oliveri, Strachan, Darwish and Wang are analogous art because they are directed at bipolar semiconductor devices, and one of ordinary skill in the art would have had a reasonable expectation of success to modify the combined structure of Oliveri and Strachan in view of Wang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined structure of Oliveri, Strachan and Darwish to include the teachings of Wang, in order to provide an open-base bipolar transistor device with a parasitic capacitance value such that the device can maintain a high response speed (Wang, [0089]).
Regarding claim 34, Oliveri as modified by Strachan, Darwish and Wang teaches the semiconductor device of claim 33. Wang further teaches wherein the p-type region (132) has a greater p-type dopant concentration than the p-type semiconductor layer (112, [0078]).
Regarding claim 37, Oliveri as modified by Strachan, Darwish and Wang teaches the semiconductor device of claim 33. Wang further teaches wherein the p-type region (132) extends continuously from an n-type semiconductor region to an isolation structure (102, [0059]). Oliveri teaches a plurality of n-type semiconductor regions.
Regarding claim 39, Oliveri as modified by Strachan and Darwish substantially teaches the entire claimed semiconductor device of claim 10.
Oliveri further teaches wherein the p-type layer (1) interfaces with the plurality of n-type regions (2).
Oliveri as modified by Strachan and Darwish discloses comprising a p-type region disposed in the p-type layer, the plurality of n-type regions interface with the p-type region, but does not specifically disclose the p-type region having a greater p-type dopant concentration than the p-type layer.
Wang teaches a p-type region (132, [0078]) disposed in a p-type layer (112, [0078]), the p-type region (132) having a greater p-type dopant concentration than the p-type layer (112, [0079]); and wherein: an n-type region (123, [0055]) interfaces with the p-type region (132).
Oliveri, Strachan, Darwish and Wang are analogous art because they are directed at bipolar semiconductor devices, and one of ordinary skill in the art would have had a reasonable expectation of success to modify the combined structure of Oliveri, Strachan, Darwish in view of Wang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined structure of Oliveri, Strachan and Darwish to include a p-type region disposed in the p-type layer, the p-type region having a greater p-type dopant concentration than the p-type layer; and wherein: the plurality of n-type regions interface with the p-type region, as taught by Wang, in order to provide an open-base bipolar transistor device with a parasitic capacitance value such that the device can maintain a high response speed (Wang, [0089]).
Regarding claim 40, Oliveri as modified by Strachan, Darwish and Wang teaches the semiconductor device of claim 39. Wang further teaches wherein the p-type region (132) extends continuously from an n-type region (123) to the first isolation structure (102, [0059]).
Oliveri teaches a plurality of n-type semiconductor regions.
Claims 41-49 are rejected under 35 U.S.C. 103 as being unpatentable over Oliveri et al. in U.S. Patent 5,032,887 (hereinafter Oliveri) and Strachan et al. in US 2017/0200712 A1 (hereinafter Strachan) in view of Darwish (US 2012/0161226 A1 now US 8,546,878 B2), and further in view of Denison in US 2008/0169513 A1.
Regarding claim 41, Oliveri as modified by Strachan and Darwish teaches substantially the entire claimed semiconductor device of claim 10. Oliveri does not explicitly state wherein the first area is a first low capacitance diode area and the n-type regions is a first plurality of n-type regions, the semiconductor device further comprising: a second low capacitance diode area including a second plurality of n-type regions in the p-type layer, wherein each of the n-type regions in the second plurality of n-type regions has: the footprint with the circular, oval, or obround shape; and the uniform size throughout the p-type layer such that each n-type region has the same uniform size throughout the p-type layer; and a first parallel diode area located between the first and second low capacitance diode areas, the first parallel diode area including: a p-type region in the p-type layer; and a second group of contacts connected to the p-type region.
Strachan teaches in FIG. 3 and related text, a first area (area of 314, [0032]) comprising an n-type region (322), buried p-type region (320, [0034]), and an n-type layer (302, [0033]) form an LR-LC diode (low capacitance, [0004]) diode area. Strachan further teaches a second low capacitance diode area (area of 370, [0032]) including a second n-type region (376, [0036]); and a first parallel diode area (area of 316, [0037]) located between the first and second low capacitance diode areas (areas of 314 and 370), the first parallel diode area (area of 316) including a p-type region (334, [0035]) in a p-type layer (306, [0033]).
Denison teaches in FIG. 1 and related text, a bipolar semiconductor device in which p-type and n-type doped regions (118, 116, [0016]) are contacted using groups of contacts (132, [0017]), in order to avoid current crowding and counteract local increase of current during ESD stress ([0016]).
Oliveri, Strachan, Darwish and Denison are analogous art because they are directed at bipolar semiconductor devices, and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of Oliveri in view of Strachan, Darwish and Denison because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined structure of Oliveri and Strachan:
to include a buried p-type region such that the first area is a first low capacitance diode area, as taught by Strachan, in order to provide an LR-LC diode device with adjustable breakdown voltage (Strachan, [0016]);
to include a second low capacitance diode area, as taught by Strachan, in order to form a pair of bidirectional diodes having a high breakdown voltage (Strachan, [0038]);
wherein the second low capacitance diode area a includes second plurality of n-type regions in the p-type layer, wherein each of the n-type regions in the second plurality of n-type regions has: the footprint with the circular, oval, or obround shape; and the uniform size throughout the p-type layer such that each n-type region has the same uniform size throughout the p-type layer, as taught by Oliveri, in order to eliminate focusing points of emitter current and consequent failures due to breakdown (Oliveri, [col. 5, line 38-42]);
to include a first parallel diode area located between the first and second low capacitance diode areas, the first parallel diode area including: a p-type region in the p-type layer, as taught by Strachan, in order to construct a parallel diode as a component of a bidirectional diode device having a high breakdown voltage (Strachan, [0013]/[0038]); and
to include a second group of contacts connected to the p-type region, as taught by Denison, in order to avoid current crowding and counteract local increase of current during ESD stress (Denison, [0016]).
Regarding claim 42, Oliveri as modified by Strachan, Darwish and Denison teaches the semiconductor device of claim 41. Oliveri does not teach wherein the p-type region is a first p-type region, the semiconductor device further comprising: a second parallel diode area located between the first and second low capacitance diode areas, the second parallel diode area including: a second p-type region in the p-type layer; and a third group of contacts connected to the second p-type region; and a second trench isolation structure surrounding the second low capacitance diode area; a third trench isolation structure surrounding the first parallel diode area; and a fourth trench isolation structure surrounding the second parallel diode area.
Strachan teaches in FIG. 3 and related text, wherein the p-type region (334) is a first p-type region, the semiconductor device further comprising: a second parallel diode area (area of 372, [0032]) located adjacent to the second low capacitance diode area, the second parallel diode area (area of 372) including: a second p-type region (378, [0037]) in the p-type layer (306); and a second trench isolation structure (308, [0032]) surrounding the second low capacitance diode area (area of 370); a third trench isolation structure (308) surrounding the first parallel diode area (area of 316); and a fourth trench isolation structure (308) surrounding the second parallel diode area (area of 372). It is noted Strachan does not teach the second parallel diode area is located between the first and second low capacitance diode areas, but teaches the second parallel diode area is adjacent to the second low capacitance diode area.
Denison teaches in FIG. 1 and related text, a bipolar semiconductor device in which p-type and n-type doped regions (118, 116, [0016]) are contacted using groups of contacts (132, [0017]), in order to avoid current crowding and counteract local increase of current during ESD stress ([0016]).
Oliveri, Strachan, Darwish and Denison are analogous art because they are directed at bipolar semiconductor devices, and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of Oliveri in view of Strachan and Denison because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined structure of Oliveri and Strachan:
to include a second parallel diode area, the second parallel diode area including: a second p-type region in the p-type layer; a second isolation structure surrounding the second low capacitance diode area; a third isolation structure surrounding the first parallel diode area; and a fourth isolation structure surrounding the second parallel diode area, as taught by Strachan, in order to form a pair of bidirectional diodes having a high breakdown voltage (Strachan, [0038]);
to locate the second parallel diode area between the first and second low capacitance diode areas in order to reduce electrical interference effects between the first and second low capacitance diode areas, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70; and
to include a third group of contacts connected to second the p-type region, as taught by Denison, in order to avoid current crowding and counteract local increase of current during ESD stress (Denison, [0016]).
Regarding claim 43, Oliveri as modified by Strachan, Darwish and Denison teaches the semiconductor device of claim 42. Oliveri does not teach the semiconductor device further comprising: a third low capacitance diode area including a third plurality of n-type regions in the p-type layer, wherein each of the n-type regions in the third plurality of n-type regions has: the footprint with the circular, oval, or obround shape; and the uniform size throughout the p-type layer such that each n-type region has the same uniform size throughout the p-type layer; and a third parallel diode area located between the first and third low capacitance diode areas, the third parallel diode area including: a third p-type region in the p-type layer; and a fourth group of contacts connected to the third p-type region; and wherein the second low capacitance diode area is on a first side of the first low capacitance diode area and the third low capacitance diode area is on a second side of the first low capacitance diode area, the first side being opposite the second side.
However, the combination of Oliveri, Strachan, Darwish and Denison teaches first and second low capacitance diode areas and first and second parallel diode areas. It would have therefore been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified to the combined structure of Oliveri, Strachan, Darwish and Denison to include: a third low capacitance diode area including a third plurality of n-type regions in the p-type layer, wherein each of the n-type regions in the third plurality of n-type regions has: the footprint with the circular, oval, or obround shape; and the uniform size throughout the p-type layer such that each n-type region has the same uniform size throughout the p-type layer; and a third parallel diode area, the third parallel diode area including: a third p-type region in the p-type layer; and a fourth group of contacts connected to the third p-type region, as taught by Oliveri, Strachan, Darwish and Denison, in order to increase the number of ESD devices in a single package. Additionally, it would have been obvious to arrange the diodes such that the third low capacitance diode is located between the second and third low capacitance diode areas, the second low capacitance diode area is on a first side of the first low capacitance diode area and the third low capacitance diode area is on a second side of the first low capacitance diode area, the first side being opposite the second side, in order to reduce electrical interference between the second and low capacitance diode areas, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
In regards to claims 44-49, the combination of Oliveri, Strachan, Darwish and Denison discloses the Applicant’s claimed invention.
Conclusion
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 January 30, 2026