Prosecution Insights
Last updated: July 17, 2026
Application No. 17/855,145

MULTIPLE COMPOSITION THERMAL INTERFACE MATERIALS FOR MULTI-DIE PACKAGES

Final Rejection §103
Filed
Jun 30, 2022
Examiner
VALENZUELA, PATRICIA D
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
2 (Final)
90%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
647 granted / 717 resolved
+22.2% vs TC avg
Minimal +2% lift
Without
With
+2.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
63 currently pending
Career history
794
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
86.7%
+46.7% vs TC avg
§102
4.8%
-35.2% vs TC avg
§112
1.8%
-38.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 717 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-13, 22-29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Valavala(USPGPUB DOCUMENT: 2021/0125897, hereinafter Valavala) in view of Chan Arguedas (USPGPUB DOCUMENT: 2020/0373220, hereinafter Chan Arguedas). Re claim 1 Valavala discloses in Fig 1 a die package comprising: a substrate(102) comprising a first face(first/second face) and an opposing second face(first/second face); a first semiconductor die(110/111) coupled to the first face(first/second face) of the substrate(102); a second semiconductor die(110/111) coupled to the first face(first/second face) of the substrate(102); and a heat spreader(120) over a side of the first semiconductor die and the second semiconductor die(110/111) opposite the substrate, wherein; a first thermal interface material(left140/right140) is between the first semiconductor die and the heat spreader; a second thermal interface material(left140/right140) the first thermal interface material(left140/right140) has a first composition[0022] the second thermal interface material(left140/right140) has a second composition[0022], different than the first composition[0022]. Valavala does not disclose, but not the first thermal interface material(left140/right140), is between the second semiconductor die(110/111) and the heat spreader; the second thermal interface material(left140/right140) has a second composition[0022], different than the first composition[0022], and a first softening temperature of the first composition[0022] is lower than a second softening temperature of the second composition[0022][0023]. Chan Arguedas discloses the second thermal interface material(104B)[0023] has a second composition[0022], different than the first composition[0022], and a first softening temperature of the first composition[0022] is lower than a second softening temperature of the second composition[0022][0023]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Chan Arguedas to the teachings of Valavala in order to enable the transfer of heat away from heat-sensitive elements in these devices [0001, Chan Arguedas]. In doing so, but not the first thermal interface material (104A)[0023 of Chan Arguedas], is between the second semiconductor die(110/111) and the heat spreader; Re claim 2 Valavala and Chan Arguedas disclose the die package of claim 1, wherein the first composition[0022] has a lower elastic modulus than the second composition[0022] under a first condition or conditions. Re claim 3 Valavala and Chan Arguedas disclose the die package of claim 1, wherein the first softening temperature[0023] is at least about 5 0C lower than the second softening temperature[0023]. Re claim 4 Valavala and Chan Arguedas disclose the die package of claim 1, wherein a first compressibility of the first thermal interface material(left140/right140) at first condition or conditions is higher than a second compressibility of the second thermal interface material(left140/right140) at the first condition or conditions Re claim 5 Valavala and Chan Arguedas disclose the die package of claim 1, wherein a first height of the first semiconductor die(110/111) relative to the first face(first/second face) of the substrate(102) is less than a second height of the second semiconductor die(110/111) relative to the first face(first/second face) of the substrate(102) and a difference in thickness between the first thermal interface material(left140/right140) and the second thermal interface material accommodates a difference in spacing between the first and second semiconductor die(110/111) and a surface of the heat spreader, the difference in spacing being associated with the difference between the first and second heights of the semiconductor die. Re claim 6 Valavala and Chan Arguedas disclose the die package of claim 1, wherein the first thermal interface material(left140/right140) has a first composition[0022]comprising in and the second thermal interface material(left140/right140) has a second composition[0022] comprising in that is different from the first composition[0022]. Re claim 7 Valavala and Chan Arguedas disclose the die package of claim 1, wherein the first and second semiconductor die(110/111)s are each one of a memory device, a computer processing unit (CPU), a graphics processing unit[0014] (GPU), or a processor. Re claim 8 Valavala discloses in Fig 1 an electronic device comprising: a circuit board[0052]; and a die package coupled to the circuit board[0052] with one or more solder joints(543/243), wherein the die package comprises: a package substrate(102) comprising a first face(first/second face) and an opposing second face(first/second face);a first semiconductor die(110/111); and a heat spreader(120), a first thermal interface material(left140/right140) is thermally connected to the heat spreader(120) by a second thermal interface material(left140/right140); a second semiconductor die(110/111) coupled to the first face(first/second face) of the substrate(102);a heat spreader over a side of the first semiconductor die and the second semiconductor die(110/111) opposite the substrate, Valavala does not disclose but not the first thermal interface material(left140/right140), is between the second semiconductor die(110/111) and the heat spreader; wherein the first thermal interface material(left140/right140) comprises a first composition[0022] and the second thermal interface material(left140/right140) comprises a second composition[0022] different than the first composition[0022], wherein a first softening temperature of the first composition[0022] is lower than a second softening temperature of the second composition[0022][0023]; wherein the first composition comprises a different amount of one or more of Sn, Ag, Ni, Au, or Bi than the second composition. Chan Arguedas discloses wherein the first thermal interface material(104A)[0023] comprises a first composition[0022] and the second thermal interface material(104B)[0023] comprises a second composition[0022] different than the first composition[0022], wherein a first softening temperature of the first composition[0022] is lower than a second softening temperature of the second composition[0022][0023]; wherein the first composition comprises a different amount of one or more of Sn, Ag, Ni, Au, or Bi than the second composition[0023]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Chan Arguedas to the teachings of Valavala in order to enable the transfer of heat away from heat-sensitive elements in these devices [0001, Chan Arguedas]. In doing so, but not the first thermal interface material (104A)[0023 of Chan Arguedas], is between the second semiconductor die(110/111) and the heat spreader; Re claim 9 Valavala and Chan Arguedas disclose the electronic device of claim 8, wherein the first composition[0022] has a lower elastic modulus than the second composition[0022] under a first specified condition or conditions. Re claim 10 Valavala and Chan Arguedas disclose the electronic device of claim 8, wherein the first softening temperature[0023] is at least about 5 °C lower than the second softening temperature[0023]. Re claim 11 Valavala and Chan Arguedas disclose the electronic device of claim 8, wherein the circuit board[0052] comprises a mother board. Re claim 12 Valavala and Chan Arguedas disclose the electronic device of claim 8, further comprising an antenna coupled to the circuit board[0052]. Re claim 13 Valavala and Chan Arguedas disclose the electronic device of claim 8, wherein further comprising an antenna coupled to the circuit board[0052]. Re claim 22 Valavala and Chan Arguedas disclose the die package of claim 5, wherein:the first thermal interface material(left140/right140) is in direct contact with both a surface of the heat spreader and the first semiconductor die; andthe second thermal interface material is in contact with both the surface of the heat spreader and the second semiconductor die(110/111). Re claim 23 Valavala and Chan Arguedas disclose the die package of claim 22, wherein the surface of the heat spreader is planar and a difference in thickness between the first thermal interface material(left140/right140) and the second thermal interface material is equal to a difference in spacing between the first and second semiconductor die(110/111) and the planar surface of the heat spreader. Re claim 24 Valavala discloses in Fig 1 an apparatus, comprising: a package substrate(102); a first integrated circuit (IC) die(110/111) coupled to the package substrate(102); a second IC die(110/111) adjacent to the first IC die(110/111) and also coupled to the package substrate(102); and a heat spreader(120) over a side of the first and the second IC die(110/111) opposite the substrate, wherein:a first thermal interface material(left140/right140) is between the first IC die(110/111) and the heat spreader(120);a second thermal interface material is between the second IC die(110/111) and the heat spreader(120); Valavala does not disclose the first thermal interface material(left140/right140) is absent from between the second IC die(110/111) and the heat spreader(120);the first thermal interface material(left140/right140) is a first composition comprising In;the second thermal interface material is a second composition comprising In,different than the first composition; andthe first composition comprises a different amount of one or more of Sn, Ag, Ni,Au, or Bi than the second composition. Chan Arguedas disclose the first thermal interface material (104A)[0023] is a first composition comprising In;the second thermal interface material (104B)[0023] is a second composition comprising In,different than the first composition [0023]; andthe first composition comprises a different amount of one or more of Sn, Ag, Ni,Au, or Bi than the second composition [0023]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Chan Arguedas to the teachings of Valavala in order to enable the transfer of heat away from heat-sensitive elements in these devices [0001, Chan Arguedas]. In doing so, the first thermal interface material (104A)[0023 of Chan Arguedas] is absent from between the second IC die(110/111) and the heat spreader(120); Re claim 25 Valavala and Chan Arguedas disclose the apparatus of claim 24, wherein a first softening temperature of the first composition is at least 5 °C lower than a second softening temperature of the second composition. Re claim 26 Valavala and Chan Arguedas disclose the apparatus of claim 24, wherein:the first thermal interface material(left140/right140) is in direct contact with both a surface of the heat spreader(120) and the first IC die(110/111);the second thermal interface material is in contact with both the surface of the heat spreader(120) and the second IC die(110/111). Re claim 27 Valavala and Chan Arguedas disclose the apparatus of claim 26, wherein:a first height of the first IC die(110/111) relative to a surface of the substrate is different from a second height of the second IC die(110/111) relative to the surface of the substrate; anda difference in thickness between the first thermal interface material(left140/right140) and the second thermal interface material accommodates a difference in spacing between the first and second semiconductor die(110/111) and a surface of the heat spreader(120). Re claim 28 Valavala and Chan Arguedas disclose the apparatus of claim 27, wherein:the first height of the first IC die(110/111) is less than the second height of the second IC die(110/111); andthe first thermal interface material(left140/right140) has a greater thickness than the second thermal interface material. Re claim 29 Valavala and Chan Arguedas disclose the apparatus of claim 24, wherein the second thermal interface material is absent from between the first IC die(110/111) and the heat spreader(120) Response to Arguments Applicant’s arguments with respect to claim(s) 1-13, 22-29 have been considered but are moot because the arguments do not apply to any of the references and new interpretation of the references being used in the current rejection. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICIA D VALENZUELA whose telephone number is (571)272-9242. The examiner can normally be reached Monday-Friday 10am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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Prosecution Timeline

Jun 30, 2022
Application Filed
Feb 24, 2023
Response after Non-Final Action
Jan 16, 2026
Non-Final Rejection mailed — §103
Apr 15, 2026
Response Filed
Jul 01, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
90%
Grant Probability
92%
With Interview (+2.1%)
2y 2m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 717 resolved cases by this examiner. Grant probability derived from career allowance rate.

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