Prosecution Insights
Last updated: April 19, 2026
Application No. 17/855,145

MULTIPLE COMPOSITION THERMAL INTERFACE MATERIALS FOR MULTI-DIE PACKAGES

Non-Final OA §103
Filed
Jun 30, 2022
Examiner
VALENZUELA, PATRICIA D
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
92%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allow Rate
645 granted / 715 resolved
+22.2% vs TC avg
Minimal +2% lift
Without
With
+2.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
63 currently pending
Career history
778
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
60.1%
+20.1% vs TC avg
§102
19.9%
-20.1% vs TC avg
§112
8.6%
-31.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 715 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1-13 in the reply filed on 09/30/25 is acknowledged. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chan Arguedas(USPGPUB DOCUMENT: 2020/0373220, hereinafter Chan Arguedas) in view of Choudhury (USPGPUB DOCUMENT: 2017/0186665, hereinafter Choudhury). Re claim 1 Chan Arguedas discloses in Fig 1 a die package comprising: a substrate(102) comprising a first face(first/second face) and an opposing second face(first/second face); a first semiconductor die(106) coupled to the first face(first/second face) of the substrate(102); and a heat spreader(110), wherein the first semiconductor die(106) is thermally connected to the heat spreader(110) by a first thermal interface material(104A)[0023] is thermally connected to the heat spreader(110) by a second thermal interface material(104B)[0023] the first thermal interface material(104A)[0023] comprises a first composition[0022] and the second thermal interface material(104B)[0023] comprises a second composition[0022], different than the first composition[0022], and wherein a first softening temperature of the first composition[0022] is lower than a second softening temperature of the second composition[0022][0023]. Chan Arguedas does not disclose a second semiconductor die coupled to the first face(first/second face) of the substrate(102); Choudhury disclose a second semiconductor die(203/204) coupled to the first face(first/second face) of the substrate(201); It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Choudhury to the teachings of Chan Arguedas in order to avoid negative effects on the performance capabilities of the MCP by increasing unwanted heat production [0003, Choudhury]. Re claim 2 Chan Arguedas and Choudhury disclose the die package of claim 1, wherein the first composition[0022] has a lower elastic modulus than the second composition[0022] under a first specified condition or conditions. Re claim 3 Chan Arguedas and Choudhury disclose the die package of claim 2, wherein the first softening temperature[0023] is at least about 5 0C lower than the second softening temperature[0023]. Re claim 4 Chan Arguedas and Choudhury disclose the die package of claim 2, wherein a first compressibility of the first composition[0022] of the first thermal interface material(104A)[0023] at the first specified condition or conditions is higher than a second compressibility of the second composition[0022] of the second thermal interface material(104B)[0023]. Re claim 5 Chan Arguedas and Choudhury disclose the die package of claim 1, wherein a first height of the first semiconductor die(106) relative to the first face(first/second face) of the substrate(102) is different from a second height of the second semiconductor die relative to the first face(first/second face) of the substrate(102). Re claim 6 Chan Arguedas and Choudhury disclose the die package of claim 1, wherein the first thermal interface material(104A)[0023] comprises a first solder composition[0022] and the second thermal interface material(104B)[0023] comprises a second solder composition[0022] that is different from the first solder composition[0022]. Re claim 7 Chan Arguedas and Choudhury disclose the die package of claim 1, wherein the first and second semiconductor dies are each one of a memory device, a computer processing unit (CPU), a graphics processing unit[0014] (GPU), or a processor. Re claim 8 Chan Arguedas discloses in Fig 1 an electronic device comprising: a circuit board[0016]; and a die package coupled to the circuit board[0016] with one or more solder joints(122), wherein the die package comprises: a package substrate(102) comprising a first face(first/second face) and an opposing second face(first/second face);a first semiconductor die(106); and a heat spreader(110), wherein the first semiconductor die(106) is thermally connected to the heat spreader(110) by a first thermal interface material(104A)[0023] is thermally connected to the heat spreader(110) by a second thermal interface material(104B)[0023];wherein the first thermal interface material(104A)[0023] comprises a first composition[0022] and the second thermal interface material(104B)[0023] comprises a second composition[0022] different than the first composition[0022], wherein a first softening temperature of the first composition[0022] is lower than a second softening temperature of the second composition[0022][0023]. Chan Arguedas does not disclose a second semiconductor die coupled to the first face(first/second face) of the substrate(102); Choudhury disclose a second semiconductor die(203/204) coupled to the first face(first/second face) of the substrate(201); It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Choudhury to the teachings of Chan Arguedas in order to avoid negative effects on the performance capabilities of the MCP by increasing unwanted heat production [0003, Choudhury]. Re claim 9 Chan Arguedas and Choudhury disclose the electronic device of claim 8, wherein the first composition[0022] has a lower elastic modulus than the second composition[0022] under a first specified condition or conditions. Re claim 10 Chan Arguedas and Choudhury disclose the electronic device of claim 8, wherein the first softening temperature[0023] is at least about 5 °C lower than the second softening temperature[0023]. Re claim 11 Chan Arguedas and Choudhury disclose the electronic device of claim 8, wherein the circuit board[0016] comprises a mother board. Re claim 12 Chan Arguedas and Choudhury disclose the electronic device of claim 8, further comprising an antenna coupled to the circuit board[0016]. Re claim 13 Chan Arguedas and Choudhury disclose the electronic device of claim 8, wherein further comprising an antenna coupled to the circuit board[0016]. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICIA D VALENZUELA whose telephone number is (571)272-9242. The examiner can normally be reached Monday-Friday 10am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Jun 30, 2022
Application Filed
Feb 24, 2023
Response after Non-Final Action
Jan 09, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604686
SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
2y 5m to grant Granted Apr 14, 2026
Patent 12604749
SEMICONDUCTOR PACKAGE
2y 5m to grant Granted Apr 14, 2026
Patent 12598990
ELECTRICALLY ISOLATED DISCRETE PACKAGE WITH HIGH PERFORMANCE CERAMIC SUBSTRATE
2y 5m to grant Granted Apr 07, 2026
Patent 12598986
METAL INSULATOR METAL CAPACITOR (MIM CAPACITOR)
2y 5m to grant Granted Apr 07, 2026
Patent 12593675
RETICLE STITCHING TO ACHIEVE HIGH-CAPACITY INTEGRATED CIRCUIT
2y 5m to grant Granted Mar 31, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
92%
With Interview (+2.1%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 715 resolved cases by this examiner. Grant probability derived from career allow rate.

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