Prosecution Insights
Last updated: May 29, 2026
Application No. 17/855,162

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Non-Final OA §103
Filed
Jun 30, 2022
Priority
Jul 09, 2020 — JP 2020-118648 +1 more
Examiner
FARMER, EMILY NICOLE
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Fuji Electric Co. Ltd.
OA Round
2 (Non-Final)
94%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allowance Rate
30 granted / 32 resolved
+25.8% vs TC avg
Moderate +9% lift
Without
With
+8.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
17 currently pending
Career history
54
Total Applications
across all art units

Statute-Specific Performance

§103
87.8%
+47.8% vs TC avg
§102
3.7%
-36.3% vs TC avg
§112
3.7%
-36.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 32 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of Claims Claims 1, 3, 6-12, and 14-17 are pending. Claims 2, 4, 5, and 13 are cancelled. Claims 14-17 are withdrawn. Claims 1, 3, and 6 are amended. Response to Arguments/Amendments Applicant's arguments filed 06/12/2025 have been fully considered but they are not persuasive. Regarding the amended claim 1, applicant argues (Pages 7-9) that the cited prior art does not read on the amended claim limitations, specifically of a “vertical portion, a first continuing portion, a first divided portion, a second continuing portion, and a second divided portion, wherein a sum of a thickness of the first continuing portion and a thickness of the second communication portion is the same as a thickness of a vertical portion.” Applicant argues that Chandra fails to teach “wherein a sum of a thickness of the first continuing portion and a thickness of the second communication portion is the same as a thickness of a vertical portion,” however, base reference Kitajima teaches the stated claim limitation, further discussed below. The rejection of claims 1, 3, and 6-12 are upheld. Claim Objections Claim 1 is objected to because of the following informalities: Claim 1 reads “and a sum of a thickness of the first continuing portion and a thickness of the second communication portion” but should read “and a sum of a thickness of the first continuing portion and a thickness of the second continuing portion” Appropriate correction is required. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 3, 6, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Kitajima et al. (US PGPub 2017/0207179), herein referred to as Kitajima, and further in view of Chandra et al. (US PGPub 2020/0044372), herein referred to as Chandra. Regarding claim 1, Kitajima teaches (Figs. 4-5) a semiconductor device, comprising: a semiconductor chip; an insulated circuit substrate including an insulating board (1, [0048]), and a circuit pattern disposed on the insulating board and being electrically connected to the semiconductor chip (2, [0048]); and a wiring member having a leg portion (6a, 6b, [0076, 0090]) at one end thereof and an external connection terminal (6, [0076, 0090]) at another end thereof, the leg portion being bonded to the circuit pattern (4b, [0076, 0090]), wherein the leg portion includes a vertical portion (6, [0076, 0089]), a first divided portion (6a, [0076, 0090]), and a second divided portion (6b, [0076, 0090]), the vertical portion extends in a vertical direction that is orthogonal to a plane of the circuit pattern, and having a split end (6a, 6b, [0076, 0090]) that is provided at a side of the vertical portion at which the circuit pattern is disposed, the first divided portion extending in a first direction that is parallel to the plane of the circuit pattern and is bonded to the circuit pattern, the second divided portion extends in a second direction opposite the first direction and is bonded to the circuit pattern ([0076, 0090]) and a sum of a thickness of the first continuing portion (6a, [0076]) and a thickness of the second continuing portion (6b, [0076]) is the same as a thickness of the vertical portion ([0076]). Kitajima does not explicitly teach a first continuing portion, a second continuing portion, the first continuing portion has a bent shape to connect the split end of the vertical portion and the first divided portion and has an elasticity, from the first continuing portion the second continuing portion has a bent shape to connect the split end of the vertical portion and the second divided portion and has an elasticity. Chandra teaches (Fig. 5A, [0036]) wherein the leg portion further includes a first continuing portion (506a) that has a bent shape to connect the split end of the vertical portion (504) and the first divided portion (506) and that has an elasticity, and a second continuing portion (508a) that has a bent shape to connect the split end of the vertical portion (504) and the second divided portion (508) and that has an elasticity, the first divided portion continuing from the first continuing portion and extending in the first direction, and the second divided portion continuing from the second continuing portion and extending in the second direction ([0036]). Chandra teaches wherein the lead frame may be provided by a single piece of material that is cut and bent to form the continuing portion that has a bent shape ([0037]). In order to be bent, the continuing portion must have a material elasticity. Although Chandra teaches wherein two divided portions obtained from splitting a vertical portion width-wise are bent to form the continuing portions, a person of ordinary skill in the art would recognize that the same method could be applied to two divided portions obtained from splitting a vertical portion thickness-wise to form the continuing portions with an equivalent resulting structure. Because Kitajima and Chandra are both directed toward leadframe devices, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kitajima and Chandra to include wherein the leg portion further includes a first continuing portion that has a bent shape to connect the split end of the vertical portion and the first divided portion and that has an elasticity, and a second continuing portion that has a bent shape to connect the split end of the vertical portion and the second divided portion and that has an elasticity, the first divided portion continuing from the first continuing portion and extending in the first direction, and the second divided portion continuing from the second continuing portion and extending in the second direction for the purpose of providing a structurally robust connector lead frame (Chandra, [0037]). Regarding claim 3, Kitajima in view of Chandra teaches the semiconductor device according to claim 1, wherein the first continuing portion (Chandra, 506a), the first divided portion (Kitajima, Fig. 4, 6a), the second continuing portion (Chandra, 508a), and the second divided portion (Kitajima, Fig. 4, 6b) all have the same thickness, which is half the thickness of the vertical portion (Kitajima, Fig. 4, 6). Regarding claim 6, Kitajima in view of Chandra teaches (Fig. 5) the semiconductor device according to claim 1, wherein in a plan view of the semiconductor device, the first divided portion and the second divided portion have a same area size ([0095]). Kitajima teaches wherein dividing the electrode terminal into two branches reduces the current flow to each terminal by half, thus the area size of the first and second divided portions must have a same area size ([0095]). Regarding claim 7, Kitajima in view of Chandra teaches (Fig. 4) the semiconductor device according to claim 1, wherein the first divided portion (6a, [0084]) has a first end at a side of the first divided portion opposite to a side where the split end is located in the first direction, and the second divided portion (6b, [0076]) has a second end at a side of the second divided portion opposite to a side where the split end is located in the second direction, and a length from the split end to the first end and a length from the split end to the second end are the same ([0084]). Kitajima teaches wherein the sectional areas of branches of the electrode terminal are assumed equal to each other ([0079]). Because both branches are split in a width direction, the length of the branches must be equal in order to achieve equal area. Additionally, Kitajima teaches wherein dividing the electrode terminal into two branches reduces the current flow to each terminal by half, and given the requirement of the same width for each branch, the length of each must be equal ([0084]). Claims 8-12 are rejected under 35 U.S.C. 103 as being unpatentable over Kitajima in view of Chandra, as applied to claim 1 above, further in view of Tønnes (DE102018204408, US PGPub 2021/0013148 cited for convenience), herein referred to as Tønnes. Regarding claim 8, Kitajima in view of Chandra teaches (Kitajima, Fig. 4) the semiconductor device according to claim 1 and a split end (6a, 6b, [0074]) of the vertical portion of leg portion, but does not explicitly teach wherein the leg portion included in the wiring member is provided in plurality, and the wiring member further includes a body portion to which is connected a top end of the vertical portion opposite to the split end of the vertical portion of each of the plurality of leg portions. Tønnes teaches (Fig. 1) wherein the leg portion included in the wiring member is provided in plurality (20, [0038]), and the wiring member further includes a body portion (10, [0038]) to which is connected a top end of the vertical portion (20, [0038]) opposite to the end of the each of the plurality of leg portions. Because Kitajima in view of Chandra and Tønnes are both directed toward power devices, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kitajima in view of Chandra and of Tønnes to include wherein the leg portion included in the wiring member is provided in plurality, and the wiring member further includes a body portion to which is connected a top end of the vertical portion opposite to the split end of the vertical portion of each of the plurality of leg portions for the purpose of providing electrical connections from legs to a central body (Tønnes, [0010]). The semiconductor device according to claim 1, wherein the leg portion included in the wiring member is provided in plurality, and the wiring member further includes a body portion to which is connected a top end of the vertical portion opposite to the split end of the vertical portion of each of the plurality of leg portions. Regarding claim 9, Kitajima in view of Chandra and Tønnes teaches the semiconductor device according to claim 8, wherein the body portion (Tønnes, Fig. 8, 10, [0038]) extends in a wiring direction, and each of the plurality of leg portions is arranged in the wiring direction (Kitajima, Fig. 14, 6). Regarding claim 10, Kitajima in view of Chandra and Tønnes teaches the semiconductor device according to claim 9, wherein each of the plurality of leg portions (Kitajima, Fig. 5, 6a, 6b, [0089]) is connected to the body portion (Tønnes, Fig. 1, 10) in such a manner that the first direction and the wiring direction are the same direction (Kitajima, Fig. 14). Regarding claim 11, Kitajima in view of Chandra and Tønnes teaches the semiconductor device according to claim 10, wherein the first divided portion (Kitajima, Fig. 5, 6a) and the second divided portion (Kitajima, Fig. 5, 6b) included in each of the plurality of leg portions (Tønnes, Fig. 1, 20) are aligned in the wiring direction with respect to the body portion (Kitajima, Fig. 14). Regarding claim 12, Kitajima in view of Chandra and Tønnes teaches the semiconductor device according to claim 9, further comprising a heat dissipation plate (Kitajima, Fig. 14, 11, [0035]), wherein the insulated circuit substrate (Kitajima, Fig. 14, 1, [0035]) is provided in plurality, the plurality of insulated circuit substrates being arranged along the wiring direction on the heat dissipation plate, and the wiring member extends in the wiring direction so that the body portion (Tønnes, Fig. 1, 10) passes over the plurality of insulated circuit substrates, and each of the plurality of leg portions (Tønnes, Fig. 1, 20) is bonded to a respective one of the plurality of insulated circuit substrates (Kitajima, Fig. 14, 11). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY FARMER whose telephone number is (703)756-1472. The examiner can normally be reached Monday-Friday 7:30-5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /EMILY FARMER/Examiner, Art Unit 2812 /DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Jun 30, 2022
Application Filed
Mar 12, 2025
Non-Final Rejection mailed — §103
Jun 12, 2025
Response Filed
Jul 21, 2025
Final Rejection mailed — §103
Sep 26, 2025
Interview Requested
Oct 02, 2025
Applicant Interview (Telephonic)
Oct 06, 2025
Examiner Interview Summary
Oct 17, 2025
Response after Non-Final Action

Precedent Cases

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Prosecution Projections

2-3
Expected OA Rounds
94%
Grant Probability
99%
With Interview (+8.7%)
3y 1m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 32 resolved cases by this examiner. Grant probability derived from career allowance rate.

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