Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
This communication is a second office action, final rejection on the merits. Claims 1-2, as amended, are currently pending and have been considered below. Claims 3-26, as previously filed, are currently pending and haven been considered below.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-26 are rejected under 35 U.S.C. 102 (a)(2) as being anticipated by Phillips et al. (USP 10,730,531; hereinafter Phillips).
Regarding Claim 1:
Phillips discloses a system on a chip (SoC), comprising: a reduced instruction set computer (RISC) central processing unit (CPU) (Phillips, Column 16, Lines 41-52, Phillips discloses the computing device includes one or more processors and may be any suitable processing device, such as processor core, microprocessor, ASIC, FPGA, controller, microcontroller, etc.);
a memory interface (Phillips, Column 17, Lines 20-43, Phillips discloses an interface for communicating data which includes controllers, receivers, transceiver, transmitters, port, software, and hardware for data);
an interconnect to support cache coherence (Phillips, Column 8, Lines 14-24, Phillips discloses an on-board diagnostics detector and communication links configured to receive and send data, signals, messages, etc.);
an input/output (I/O) unit (Phillips, Column 2, Lines 3-23, Phillips discloses inputting and outputting data);
general processing clusters (Phillips, Column 2, Lines 3-23, Phillips discloses one or more processors);
processing units to accelerate deep learning (Phillips, Column 2, Lines 3-23, Phillips discloses one or more processors communicating with the machine learned model (i.e. deep learning)); and
wherein the processing units are to use a neural network to determine an orientation of a vehicle with respect to a centerline of a path utilizing image data and determine a lateral position of the vehicle with respect to a centerline of the path utilizing the image data (Phillips, Fig. 4C, Column 12 Lines 33 Column 13 Line 35, Phillips discloses controlling the vehicle based on the determined risk associated (i.e. probabilities) with the object within the path of the vehicle, with the current travel lane of the vehicle having a center and the edges of the lane being determined through the analyzed collected images).
Regarding Claim 2:
The claim recites analogous limitations to claim 1 above, and is therefore rejected on the same premise.
Regarding Claim 3:
Phillips discloses The SoC of claim 1.
Phillips further discloses further comprising memory communicatively coupled to the memory interface (Phillips, Column 16, Lines 41-52, Phillips discloses a memory connected to the communication interface (i.e. memory interface)).
Regarding Claim 4:
Phillips discloses The SoC of claim 1.
Phillips further discloses further comprising one or more cache memories (Column 18, Lines 15-23, Phillips discloses one or more memories remote from the system).
Regarding Claim 5:
Phillips discloses The SoC of claim 1.
Phillips further discloses wherein the processing units to accelerate deep learning comprise one or more cores to perform matrix operations (Phillips, Column 18, Lines 44-54, Phillips discloses the processing units may include a plurality of various machine learned models including boosted random forest techniques, support vector machines, multi-layer non-linear models, feed forward neural networks, recurrent neural networks, convolutional neural networks (i.e. matrix operations), and other forms of neural networks).
Regarding Claim 6:
Phillips discloses The SoC of claim 1.
Phillips further discloses wherein the processing units to accelerate deep learning comprise one or more cores to perform convolution operations (Phillips, Column 18, Lines 44-54, Phillips discloses deep learning comprises convolutional neural networks).
Regarding Claim 7:
Phillips discloses The SoC of claim 1.
Phillips further discloses further comprising a network interface to couple the SoC to a network (Phillips, Column 8, Lines 14-24, Phillips discloses the communication channel connects one or more buses together and communicates data, messages, signals, etc. amongst one another).
Regarding Claim 8:
Phillips discloses The SoC of claim 1.
Phillips further discloses further comprising a switch to interface between the interconnect and the CPU (Phillips, Column 19. Lines 59-65, Phillips discloses the communication interface includes any circuits, components, or software, which may be accomplished using any type of protocol, protection scheme, encoding, formatting, packaging, etc.).
Regarding Claim 9:
Phillips discloses The SoC of claim 1.
Phillips further discloses further comprising a communication bus connected to the CPU (Phillips, Column 8, Lines 14-24, Phillips discloses the communication channel connects one or more buses together and communicates data, messages, signals, etc. amongst one another).
Regarding Claim 10:
Phillips discloses The SoC of claim 1.
Phillips further discloses further comprising a front end unit to read one or more commands and forward the one or more commands to one or more other units of the SoC (Phillips, Column 1, Lines 52-65, Phillips discloses one or more memory devices which received and store instructions when are then executed by the one or processors of the system).
Regarding Claim 11:
Phillips discloses The SoC of claim 1.
Phillips further discloses wherein the image data comprises data to indicate a location of the vehicle on the path (Phillips, Column 9 Lines 15-29, Phillips discloses the collected environmental data is processed to determine upcoming object’s properties, such properties include at least location of the object).
Regarding Claim 12:
The claim recites analogous limitations to claim 11 above, and is therefore rejected on the same premise.
Regarding Claim 13:
The claim recites analogous limitations to claim 5 above, and is therefore rejected on the same premise.
Regarding Claim 14:
The claim recites analogous limitations to claim 6 above, and is therefore rejected on the same premise.
Regarding Claim 15:
The claim recites analogous limitations to claim 3 above, and is therefore rejected on the same premise.
Regarding Claim 16:
The claim recites analogous limitations to claim 7 above, and is therefore rejected on the same premise.
Regarding Claim 17:
The claim recites analogous limitations to claim 8 above, and is therefore rejected on the same premise.
Regarding Claim 18:
The claim recites analogous limitations to claim 9 above, and is therefore rejected on the same premise.
Regarding Claim 19:
The claim recites analogous limitations to claim 10 above, and is therefore rejected on the same premise.
Regarding Claim 20:
The claim recites analogous limitations to claim 4 above, and is therefore rejected on the same premise.
Regarding Claim 21:
Phillips discloses a vehicle comprising: the system on a chip (SoC) of claim 1 (Phillips, Column 1, Lines 37-51, Phillips discloses a vehicle includes the system of claim 1).
Regarding Claim 22:
Phillips discloses wherein the SoC is a component of the vehicle (Phillips, Column 1, Lines 37-51, Phillips discloses a vehicle includes the system of claim 1).
Regarding Claim 23:
The claim recites analogous limitations to claim 21 above, and is therefore rejected on the same premise.
Regarding Claim 24:
The claim recites analogous limitations to claim 22 above, and is therefore rejected on the same premise.
Regarding Claim 25:
Phillips discloses the SoC of Claim 1.
Phillips further discloses wherein the path is a predicted path identified by the neural network form one or more images of a location of the vehicle (Phillips, Fig. 4C, Column 12 Lines 33-64, Phillips discloses controlling the vehicle based on the determined risk, from images, associated with the object within the path of the vehicle).
Regarding Claim 26:
Phillips discloses the SoC of Claim 1.
Phillips further discloses wherein the vehicle is to travel along the path (Phillips, Fig. 4C, Column 12 Lines 33-64, Phillips discloses controlling the vehicle based on the determined risk associated with the object within the path of the vehicle).
Response to Arguments
Applicant’s arguments, filed 12/18/2025, with respect to the nonstatutory double patenting have been fully considered and are persuasive. The nonstatutory double patenting rejection of claims 1-2 has been withdrawn.
Applicant's arguments filed 12/18/2025 have been fully considered but they are not persuasive.
In particular the applicant’s representative argue the cited art of Phillips fails to explicitly disclose “determining an orientation of a vehicle with respect to a centerline of a path utilizing image data and determine a lateral position of the vehicle with respect to the centerline of the path utilizing the image data”. However the examiner respectfully disagrees.
The examiner puts forth the amendment adding “a centerline” to the path of the vehicle adds no additional scope to the invention, because the examiner puts forth that any path or lane of travel would have a center line being traveled by the vehicle, and furthermore a path or lane of travel would inherently would be required to have a centerline. Furthermore the cited art of Phillips clearly discloses determining orientation of the vehicle and lateral positioning of the vehicle within the lane with respect to a centerline of a path. Support for this disclose can be found throughout Phillips, in particular, Column 12 Lines 10 – Column 14 Lines 33. Phillips clearly discloses determining positioning of the vehicle within the lane in order to determine how to avoid an upcoming collision. Necessary information such as the road width, positioning of the vehicle and object within the road, relative velocities and accelerations, and the like are all taken into account when determining the avoidance maneuver to be performed by the host vehicle. Furthermore these operations are clearly performed by any number or types of neural networks as disclosed by Phillips Column 17 Lines 44-54 using captured image data of the environment as disclosed by Phillips Column 3 Lines 45-67.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZACHARY JOSEPH WALLACE whose telephone number is (469)295-9087. The examiner can normally be reached 7:00 am - 5:00 pm, Monday - Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wade Miles can be reached at (571) 270-7777. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Z.J.W./Examiner, Art Unit 3656
/WADE MILES/Supervisory Patent Examiner, Art Unit 3656
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