DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 10/27/2025 have been fully considered but they are not persuasive.
Applicant’s remarks filed 10/27/2025 failed to articulate how the claim amendments overcame the prior art of record and only addressed the previous non-compliant amendment action which was mailed.
In light of the previous remarks of 7/17/2025, it appears Applicant’s arguments are directed to the now-claimed-limitation of “the circuits are outside a footprint of the shield.”
Examiner respectfully disagrees that the limitation is not taught by Tiemeijer. Since the claims do not preclude the existence of the circuit under the shield, Tiemeijer teaches that there exists circuits outside the footprint of the shield as well as under the shield and meets each of these claimed limitations.
Claim 15 indicator should be changed to “original.”
The rejection has been updated to include the amended portions of the claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tiemeijer (US PGPub 2010/0224958).
Re claim 1: Tiemeijer teaches (e.g. figs. 1 and 2) an integrated circuit, comprising: a semiconductor substrate (Si substrate 5 of circuit die 1; e.g. paragraph 56) including circuits (circuits which are below wire bonding 7; e.g. paragraph 56; hereinafter “C”); a metal layer (metal layers within passivation 8; hereinafter “ML”) over the semiconductor substrate (5); an inductor (inductor 9; e.g. paragraph 56) in the metal layer (ML); and a shield (metal cover 4; e.g. paragraph 56) over the inductor (9), in which the circuits (C) are outside (there exists circuits C outside the footprint of 4) a footprint (area of 4) of the shield (4).
Re claim 2: Tiemeijer teaches the integrated circuit of claim 1, wherein: the metal layer (ML) is a first metal layer (ML is a first metal layer); and the shield (4) is in a second metal layer (4 is a second metal layer) over the first metal layer (9).
Re claim 8: Tiemeijer teaches the integrated circuit of claim 1, wherein the inductor (9) is a figure-8 inductor (as can be seen from fig. 1, inductor 9 is formed as a figure-8).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tiemeijer as applied to claim 1 above, and further in view of Brennan et al. (US PGPub 2002/0096736; hereinafter “Brennan”).
Re claim 3: Tiemeijer teaches substantially the entire structure as claimed in claim 1 except explicitly teaching the integrated circuit, wherein the shield includes a plurality of metal traves angled from metal traves of the inductor.
Brennan teaches (e.g. figs. 3 and 4) the integrated circuit, wherein the shield (shielding layer 302; e.g. paragraph 22) includes a plurality of traces (conductive traces 322) angled from (322 are at angles to 314; e.g. paragraph 23) metal traces (conductive traces 314) of the inductor (inductor 312; e.g. paragraph 21).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the orthogonal inductor traces and shield traces as taught by Brennan in the device of Tiemeijer in order to have the predictable result of minimizing eddy currents flowing within the shielding layers which better isolates the inductor from adjacent structures (see paragraph 23 of Brennan).
Claim(s) 9, 10 ,15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Burton et al. (US PGPub 2018/0108621; hereinafter “Burton”) in view of Tiemeijer and Korden (US PGPub 2009/0174497).
Re claim 9: Burton teaches (e.g. figs. 2A-4) an oscillator circuit, comprising: a resonator (resonators electromagnetically coupled via the transformer gap 206; e.g. paragraph 30; hereinafter “R”); an integrated circuit (131, 132, 133, 134) coupled to the resonator (R), and including: a transformer (transformer primary 132 and secondary 133 windings; e.g. paragraph 30) including: a winding (132, 133) coupled to the resonator (R) and the circuit (131, 134).
Burton is silent as to explicitly teaching the integrated circuit including: a semiconductor substrate including circuits; a metal layer over the semiconductor substrate; a transformer in the metal layer including: a winding coupled to the resonator and the circuit; and a shield over the transformer, in which the circuits are outside a footprint of the shield; and the resonator is a bulk acoustic wave (BAW) resonator.
Tiemeijer teaches (e.g. figs. 1 and 2) integrated circuit including: a semiconductor substrate (Si substrate 5 of circuit die 1; e.g. paragraph 56) including circuits (circuits which are below wire bonding 7; e.g. paragraph 56; hereinafter “C”); a metal layer (metal layers within passivation 8; hereinafter “ML”) over the semiconductor substrate (5); a transformer (inductor 9; e.g. paragraph 56) in the metal layer (ML) including: a winding (inductor 9; e.g. paragraph 56); and a shield (metal cover 4; e.g. paragraph 56) over the transformer (9), in which the circuits (C) are outside (there exists circuits C outside the footprint of 4) a footprint (area of 4) of the shield (4).
Korden teaches the common use of bulk acoustic wave resonators (e.g. paragraph 14).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results use the shielding structure above the inductor as taught by Tiemeijer and to use the BAW resonator as taught by Korden in the device of Burton in order to have the predictable result of better shielding of electrical fields (see paragraph 31 of Tiemeijer) and in order to have the predictable result of using a known type of resonator capable of being incorporated into a chip so that integration is easily achieved, respectively.
Re claim 10: Burton in view of Tiemeijer and Korden teaches the oscillator circuit of claim 9, wherein: the metal layer (ML of Tiemeijer) is a first metal layer; and the shield (4 of Tiemeijer) is in a second metal layer over the first metal layer.
Re claim 15: Burton in view of Tiemeijer and Korden teaches the oscillator circuit of claim 9, wherein the transformer is a figure-8 transformer (8 shaped; e.g. paragraph 64 of Tiemeijer or as shown in fig. 4 of Burton).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Burton in view of Tiemeijer and Korden as applied to claim 9 above, and further in view of Brennan et al. (US PGPub 2002/0096736; hereinafter “Brennan”).
Re claim 11: Burton in view of Tiemeijer and Korden teaches the oscillator circuit of claim 9, wherein the shield includes a plurality of metal traces angled from to metal traces of the winding.
Brennan teaches (e.g. figs. 3 and 4) the oscillator circuit, wherein the shield (shielding layer 302; e.g. paragraph 22) includes a plurality of metal traces (conductive traces 322) angled from (322 are at angles to 314; e.g. paragraph 23) to metal traces (conductive traces 314) of the winding (inductor 312; e.g. paragraph 21).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the orthogonal inductor traces and shield traces as taught by Brennan in the device of Burton in view of Tiemeijer and Korden in order to have the predictable result of minimizing eddy currents flowing within the shielding layers which better isolates the inductor from adjacent structures (see paragraph 23 of Brennan).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tiemeijer in view of Watanabe et al. (US PGPub 20160093570; hereinafter “Watanabe”).
Re claim 16: Tiemeijer teaches (e.g. figs. 1 and 2) a packaged integrated circuit, comprising: a semiconductor substrate(Si substrate 5 of circuit die 1; e.g. paragraph 56) including circuits (circuits which are below wire bonding 7; e.g. paragraph 56; hereinafter “C”); a metal layer (metal layers within passivation 8; hereinafter “ML”) over the semiconductor substrate (5); an inductor (inductor 9; e.g. paragraph 56) in the metal layer (ML); a shield (metal cover 4; e.g. paragraph 56) over the inductor (9), in which the circuits (C) are outside (there exists circuits C outside the footprint of 4) a footprint (area of 4) of the shield (4).
Tiemeijer is silent as to explicitly teaching a mold compound covering at least parts of the semiconductor substrate and the shield.
Watanabe teaches (e.g. fig. 9) a mold compound (MR) covering at least parts of the semiconductor substrate (5 of Tiemeijer) and the shield (4 of Tiemeijer).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the mold compound as taught by Watanabe in the device of Tiemeijer in order to have the predictable result of ensuring contaminants do not destroy the function of the IC device and improving device life.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tiemeijer in view of Watanabe as applied to claim 16 above, and further in view of Brennan.
Re claim 17: Tiemeijer teaches the packaged integrated circuit of claim 16, wherein: the metal layer (ML of Tiemeijer) is a first metal layer; the shield (4 of Tiemeijer) is in a second metal layer above the first metal layer (ML of Tiemeijer).
Tiemeijer is silent as to explicitly teaching the shield includes a plurality of metal strips substantially perpendicular to metal lines of the inductor.
Brennan teaches (e.g. figs. 3 and 4) the packaged integrated circuit, wherein: the shield (shielding layer 302; e.g. paragraph 22) includes a plurality of metal strips (conductive traces 322) substantially perpendicular (322 are orthogonal to 312; e.g. paragraph 23) to metal lines (conductive traces 314) of the inductor (inductor 312; e.g. paragraph 21).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the orthogonal inductor traces and shield traces as taught by Brennan in the device of Tiemeijer in view of Watanabe in order to have the predictable result of minimizing eddy currents flowing within the shielding layers which better isolates the inductor from adjacent structures (see paragraph 23 of Brennan).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898