DETAILED ACTION
This Office action responds to the application filed on 06/30/2022.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Species 3, reading on figure 6, in the reply filed on November 30, 2025, is acknowledged. The applicant indicates that claims 1, 2, 3, 6, 7, 12, & 15 read on the elected species. The examiner disagrees.
The limitation “the first combsheet FET is a gate-all-around FET” recited in lines 1-2 of Claim 15 reads on figures 5a-c (see, e.g., para.0025) of non-elected species 1.
Accordingly, claims 4, 5, 8-11, & 13-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Claims 1, 2, 3, 6, 7, & 12 will be examined in this Office action.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 3, 6, 7, & 12 are rejected under 35 U.S.C. 103 as being unpatentable over Bao (US 20230197721) in view of Cheng (US 20200343361) & Peidous (US 20080242014) and further in view of Ching (US 20190067284).
Regarding Claim 1, Bao (see, e.g., fig. 8a) shows an integrated circuit structure comprising:
a semiconductor substrate 226 (see, e.g., para.0083);
a first plurality of semiconductor nanosheets 110 (see, e.g., para.0058)
Bao, however, fails to show
a first combsheet field effect transistor (FET), which comprises:
the semiconductor substrate;
the first plurality of semiconductor nanosheets
that extend along a <101> crystallographic direction
and that have horizontal surfaces oriented in (100) crystallographic planes and vertical sidewalls oriented in (110) crystallographic planes;
and a semiconductor fin that is integrally attached to the nanosheets,
extends along the nanosheets,
and has horizontal sidewalls oriented in (100) crystallographic planes and vertical surfaces oriented in (110) crystallographic planes.
Cheng (see, e.g., fig. 20), in a similar device to Bao, shows an integrated circuit structure comprising:
a first combsheet field effect transistor (FET), which comprises:
a semiconductor substrate 101 (comprised of layers 110 & 120, see, e.g., para.0033);
a first plurality of semiconductor nanosheets 146 (see, e.g., para.0092)
and a semiconductor fin 170 (see, e.g., para.0047, para.0069) that is integrally attached to the nanosheets,
extends along the nanosheets,
Cheng (see, e.g., para.0069) states this configuration of the semiconductor fin 170 and the nanosheets 146 forming a first combsheet field effect transistor (FET) would increase effective charge carrying capacity.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the combsheet field effect transistor configuration of Cheng in the device of Bao to increase effective charge carrying capacity.
Bao, in view of Cheng, however, fails to show
the first plurality of semiconductor nanosheets
that extend along a <101> crystallographic direction
and that have horizontal surfaces oriented in (100) crystallographic planes and vertical sidewalls oriented in (110) crystallographic planes;
and the semiconductor fin that is integrally attached to the nanosheets,
and has horizontal sidewalls oriented in (100) crystallographic planes and vertical surfaces oriented in (110) crystallographic planes.
Peidous (see, e.g., fig. 4, para.0003, para.0019), in a similar device to Bao, in view of Cheng, teaches that the optimal crystallographic direction of a semiconductor material is <011> or equivalent <101> and would allow for the highest hole mobility.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the <101> crystallographic direction of Peidous in the device of Bao, in view of Cheng, to allow for the highest hole mobility.
Bao, in view of Cheng & Peidous, however, fails to show
the first plurality of semiconductor nanosheets
and that have horizontal surfaces oriented in (100) crystallographic planes and vertical sidewalls oriented in (110) crystallographic planes;
and the semiconductor fin that is integrally attached to the nanosheets,
and has horizontal sidewalls oriented in (100) crystallographic planes and vertical surfaces oriented in (110) crystallographic planes.
Ching (see, e.g., fig. 7b, fig. 17b, para.0053), in a similar device to Bao, in view of Cheng & Peidous, teaches FINFETs wherein the crystallographic orientations of horizontal surfaces on (100) crystallographic planes and vertical surfaces on (110) crystallographic planes would provide better performance via better electron mobility relative to fin width.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the crystallographic orientations of horizontal surfaces on (100) crystallographic planes and vertical surfaces on (110) crystallographic planes of Ching in the device of Bao, in view of Cheng & Peidous, to provide better performance via better electron mobility relative to fin width.
Regarding Claim 2, Bao, in view of Cheng & Peidous and further in view of Ching, shows the structure as claimed in claim 1, further comprising:
a second combsheet FET (combsheet FET formed of semiconductor nanosheets 120, see, e.g., fig. 8a) vertically stacked with the first combsheet FET.
Regarding Claim 3, Bao (see, e.g., para.0062), in view of Cheng & Peidous and further in view of Ching, shows the structure as claimed in claim 2,
wherein the second combsheet FET is of a different shape than the first combsheet FET.
Bao (see, e.g., para.0062) state the first plurality of semiconductor nanosheets 110 of the first combsheet FET and the plurality of semiconductor nanosheets 120 (pertaining to the second combsheet FET) can be formed of different thicknesses. Therefore, the shapes of the first and second combsheet FETs are different.
Regarding Claim 6, Bao, in view of Cheng & Peidous and further in view of Ching, shows the structure as claimed in claim 2,
wherein the semiconductor fin of the first combsheet FETs has a top end that protrudes above an upper surface of an upper nanosheet (see, e.g., annotated figure 1).
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Regarding Claim 7, Bao, in view of Cheng & Peidous and further in view of Ching, shows the structure as claimed in claim 2,
wherein the second combsheet FET is of a different chemical composition than the first combsheet FET.
Bao (see, e.g., para.0062) state the first plurality of semiconductor nanosheets 110 of the first combsheet FET can be silicon, and the plurality of semiconductor nanosheets 120 (pertaining to the second combsheet FET) can be silicon germanium. Therefore, the chemical compositions of the first and second combsheet FETs are different
Regarding Claim 12, Bao, in view of Cheng & Peidous and further in view of Ching, shows the structure as claimed in claim 1,
wherein an upper surface of the semiconductor fin of the first combsheet FET protrudes above a topmost nanosheet of the first combsheet FET 110 (topmost 110, see, e.g., annotated figure 1).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached on 571-272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO JOSE RAMOS-DIAZ/ Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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