DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Continued Examination Under 37 CFR 1.114
5. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/14/2025 has been entered.
Response to Arguments
6. Applicant’s arguments, see Claim Rejections under 35 U.S.C. § 102, filed 10/14/2025, with respect to the rejections of claims 1 and 9 under 35 U.S.C. § 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Chittipeddi, Sailesh et al. (Pub No. US 5986343 A) (hereinafter, Chittipeddi) in view of Choi, Jayoung et al. (Pub No. US 20060207790 A1) (hereinafter, Choi).
7. Applicant's arguments filed 10/14/2025 have been fully considered but they are not persuasive. Applicant argues Li, Yu-Hsien et al. (Pub No. US 20220367554 A1) (hereinafter, Li) does not disclose “the first conductive layer is above the semiconductor substrate.”
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., the first conductive layer is above the semiconductor substrate) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Further, claim 16 requires that “depositing one or more conductive layers, including a second conductive layer, and one or more insulation layers, including a top insulation layer, above the semiconductor substrate.” This process is shown in Fig 29 before the IC Chip is flipped, the conductive layers are formed above the semiconductor substrate.
8. Applicant’s arguments with respect to claim(s) 2, 4, 7, 12 and 14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. Claims 1, 3, 6, 8-11, 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chittipeddi, Sailesh et al. (Pub No. US 5986343 A) (hereinafter, Chittipeddi), and further in view of Choi, Jayoung et al. (Pub No. US 20060207790 A1) (hereinafter, Choi).
Chittipeddi, Fig 6: Embodiment of Bond Pad Design for Integrated Circuits
PNG
media_image1.png
477
533
media_image1.png
Greyscale
Re Claim 1 (Currently Amended), Chittipeddi teaches the semiconductor package (Fig 6), comprising:
a bond pad surface layer (Bond pad; 103; Fig 6; Col 4 ln 35-40);
a second conductive layer (Third metal layer; 223; Fig 6; Col 4 ln 40-45) positioned below the bond pad surface layer;
a perforated plate (Fourth metal layer; 624; Fig 6; Col 6 ln 45-50) positioned between with the bond pad surface layer and the second conductive layer, the perforated plate having a conductive member (Fourth metal layer; 624; Fig 6; Col 6 ln 45-50) and multiple insulation members (Sixth dielectric layer 616 deposited into openings 310/320/330/340/350/360; Fig 6; Col 6 ln 47-50) embedded within the conductive member, the insulation members having thicknesses approximately equivalent (Thicknesses of dielectric layer 616 in openings approximately equal to thickness of perforated fourth metal layer 624; Fig 6) to that of the conductive member;
a semiconductor substrate (Substrate; 201; Fig 6; Col 4 ln 38-40) including a circuit (Active semiconductor device; 203; Fig 6; Col ln 49-52), the semiconductor substrate positioned below the second conductive layer.
However, Chittipeddi does not teach the conductive member in direct contact with the bond pad surface layer and the second conductive layer.
In the same field of endeavor, Choi teaches the conductive member (Via arrays; 340; Fig 8; ¶[0064]) in direct contact with the bond pad surface layer (Metal pad; 350; Fig 8; ¶[0064]) and the second conductive layer (Metal pad; 320; Fig 8; ¶[0064]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the bond pad structure as disclosed by Chittipeddi by modifying the conductive member to be in direct contact with the bond pad surface layer and second conductive layer, as disclosed by Choi. One of ordinary skill in the art would have been motivated to make this modification such that the direct connection between the bond pad surface layer and conductive member can form an improved electrical connection between an external circuit and an integrated circuit through the bond pad, as suggested by Choi (¶[0005]).
Re Claim 3 (Previously Presented), Chittipeddi teaches the semiconductor package of claim 1, wherein the insulation members (Sixth dielectric layer 616 deposited into openings 310/320/330/340/350/360; Fig 6; Col 6 ln 47-50) are composed of an oxide, a nitride, or an oxynitride (Oxides or nitrides; Col 5 ln 10-15]).
Re Claim 6 (Original), Chittipeddi teaches the semiconductor package of claim 1, further comprising a passivation layer (Seventh dielectric layer; 101; Fig 6; Col 4 ln 40-45) on a top surface (Upper surface of 103; Fig 6) of the bond pad surface layer (Bond pad; 103; Fig 6; Col 4 ln 35-40), the passivation layer having a gap defining a bond window (Exposed portion; 105; Fig 6; Col 4 ln 45-48) of the bond pad surface layer, the second conductive layer (Third metal layer; 223; Fig 6; Col 4 ln 40-45) having a segment vertically coincident (Vertically disposed underneath; Fig 6) with the bond window of the bond pad surface layer.
Re Claim 8 (Original), Chittipeddi teaches the semiconductor package of claim 1, wherein the perforated plate (Fourth metal layer; 624; Fig 6; Col 6 ln 45-50) has a horizontal area (Horizontal length of 624; Fig 6) at least as large (Spans beyond edges of exposed portion 105; Fig 6) as a horizontal area (Horizontal length of 105) of a bond window (Exposed portion; 105; Fig 6; Col 4 ln 45-48) defined by a passivation layer (Seventh dielectric layer; 101; Fig 6; Col 4 ln 40-45) abutting the bond pad surface layer (Bond pad; 103; Fig 6; Col 4 ln 35-40).
Re Claim 9 (Currently Amended), Chittipeddi teaches a semiconductor package (Fig 6), comprising:
a first conductive layer (Bond pad; 103; Fig 6; Col 4 ln 35-40);
a second conductive layer (Third metal layer; 223; Fig 6; Col 4 ln 40-45) positioned below the first conductive layer;"
a perforated plate (Fourth metal layer; 624; Fig 6; Col 6 ln 45-50) positioned between the first and second conductive layers, the perforated plate having a conductive member (Fourth metal layer; 624; Fig 6; Col 6 ln 45-50) configured to distribute a force (Bond pad support layers, i.e. metal layer 624 act as a force transducer for internal and bonding stresses; Col 2 ln 25-35) applied to the first conductive layer across an area of the second conductive layer, the conductive member having insulation members (Sixth dielectric layer 616 deposited into openings 310/320/330/340/350/360; Fig 6; Col 6 ln 47-50) embedded therein;
one or more conductive layers (First/second metal layers; 221/222; Fig 6; Col 4 ln 40-45) positioned below the second conductive layer and separated from each other by insulation layers (Third/fourth dielectric layer; 213/214; Fig 6; Col 4 ln 40-45); and
a semiconductor substrate (Substrate; 201; Fig 6; Col 4 ln 38-40) including a circuit (Active semiconductor device; 203; Fig 6; Col ln 49-52), the semiconductor substrate positioned below the one or more conductive layers.
However, Chittipeddi does not teach the conductive member in direct contact with the bond pad surface layer and the second conductive layer.
In the same field of endeavor, Choi teaches the conductive member (Via arrays; 340; Fig 8; ¶[0064]) in direct contact with the bond pad surface layer (Metal pad; 350; Fig 8; ¶[0064]) and the second conductive layer (Metal pad; 320; Fig 8; ¶[0064]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the bond pad structure as disclosed by Chittipeddi by modifying the conductive member to be in direct contact with the bond pad surface layer and second conductive layer, as disclosed by Choi. One of ordinary skill in the art would have been motivated to make this modification such that the direct connection between the bond pad surface layer and conductive member can form an improved electrical connection between an external circuit and an integrated circuit through the bond pad, as suggested by Choi (¶[0005]).
Re Claim 10 (Previously Presented), Chittipeddi teaches the semiconductor package of claim 9, further comprising a wirebond (Wire; 230; Fig 6; Col 4 ln 45-49) on a top surface (Upper surface of 103; Fig 6) of the first conductive layer (Bond pad; 103; Fig 6; Col 4 ln 35-40).
Re Claim 11 (Original), Chittipeddi teaches the semiconductor package of claim 9, wherein the semiconductor substrate (Substrate; 201; Fig 6; Col 4 ln 38-40) abuts (Connected via windows 251; Fig 6; Col 4 ln 50-55; Note: The windows are for electrically connecting substrate 201 and metal layer 221) one of the one or more conductive layers (First/second metal layers; 221/222; Fig 6; Col 4 ln 40-45).
Re Claim 13 (Original), Chittipeddi teaches the semiconductor package of claim 9, further comprising a passivation layer (Seventh dielectric layer; 101; Fig 6; Col 4 ln 40-45) on a top surface (Upper surface of 103; Fig 6) of the first conductive layer (Bond pad; 103; Fig 6; Col 4 ln 35-40), the passivation layer having a gap defining a bond window (Exposed portion; 105; Fig 6; Col 4 ln 45-48) of the first conductive layer, the second conductive layer (Third metal layer; 223; Fig 6; Col 4 ln 40-45) having a segment vertically coincident (Vertically disposed underneath; Fig 6) with the bond window of the first conductive layer.
Re Claim 15 (Original), Chittipeddi teaches the semiconductor package of claim 9, wherein the perforated plate (Fourth metal layer; 624; Fig 6; Col 6 ln 45-50) has a horizontal area (Horizontal length of 624; Fig 6) at least as large (Spans beyond edges of exposed portion 105; Fig 6) as a horizontal area (Horizontal length of 105) of a bond window (Exposed portion; 105; Fig 6; Col 4 ln 45-48) defined by a passivation layer (Seventh dielectric layer; 101; Fig 6; Col 4 ln 40-45) abutting the first conductive layer (Bond pad; 103; Fig 6; Col 4 ln 35-40).
11. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Chittipeddi, Sailesh et al. (Pub No. US 5986343 A) (hereinafter, Chittipeddi) and Choi, Jayoung et al. (Pub No. US 20060207790 A1) (hereinafter, Choi) as applied to claim 1, and further in view of Li, Yu-Hsien et al. (Pub No. US 20220367554 A1) (hereinafter, Li).
Re Claim 2 (Original), Chittipeddi teaches the semiconductor package of claim 1, the conductive member (Fourth metal layer; 624; Fig 6; Col 6 ln 45-50).
However, Chittipeddi in view of Choi does not teach a first vertical segment and a second vertical segment, and wherein the first and second vertical segments are orthogonal to each other in a top-down view.
In the same field of endeavor, Li teaches a first vertical segment (Column of openings 1102; Fig 12; ¶[0079]) and a second vertical segment (Rows of openings 1102; Fig 12; ¶[0079]), and wherein the first and second vertical segments are orthogonal (Perpendicular i.e. intersect at 90 degrees in a square/rectangular lattice) to each other in a top-down view.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the bond pad structure as disclosed by Chittipeddi in view of Choi by adding first and second vertical segments that are orthogonal to each other in a top-down view, as disclosed by Li. One of ordinary skill in the art would have been motivated to make this modification due to reduce the shear force on the bond pad structure by having high density inter-wire bond vias in an evenly distributed pattern. Furthermore, this addresses the issue with bond pad structures wherein the combination of small wire thickness and low via density resulting in the columnar structure being weak proximate the bond pad structure, whereby the columnar structure has a high likelihood of peeling and hence failure in response to shear force on the bond pad structure, as suggested by Li (¶¶[0027, 0159]).
12. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chittipeddi, Sailesh et al. (Pub No. US 5986343 A) (hereinafter, Chittipeddi) and Choi, Jayoung et al. (Pub No. US 20060207790 A1) (hereinafter, Choi) as applied to claim 1, and further in view of Hsia, Chin-Chiu et al. (Pub No. US 20070205508 A1) (hereinafter, Hsia).
Re Claim 4 (Original), Chittipeddi in view of Choi does not teach the semiconductor package of claim 1, wherein the semiconductor substrate abuts the second conductive layer.
In the same field of endeavor, Hsia teaches the semiconductor package of claim 1, wherein the semiconductor substrate (Semiconductor Chip; 70; Fig 6; ¶[0032]) abuts (Connected through IMD layer 52 which typically includes conducting lines, vias, and/or wires (not shown for simplicity) per ¶[0026]) the second conductive layer (M.sub.top-1 plate; 26; Fig 6; ¶¶[0009,0022])
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the bond pad structure as disclosed by Chittipeddi in view of Choi by making the semiconductor substrate abut the second conductive layer, as disclosed by Hsia. One of ordinary skill in the art would have been motivated to make this modification such that active devices, i.e. the semiconductor chip or semiconductor substrate including circuitry, disposed under solid metal plates receive the lowest stress during bonding processes, as suggested by Hsia (¶[0033]).
13. Claims 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Chittipeddi, Sailesh et al. (Pub No. US 5986343 A) (hereinafter, Chittipeddi) and Choi, Jayoung et al. (Pub No. US 20060207790 A1) (hereinafter, Choi) as applied to claims 1 and 9, and further in view of Yang, Chin-Tien et al. (Pub No. US 20060091566 A1) (hereinafter, Yang).
Re Claim 7 (Original), Chittipeddi in view of Choi does not teach the semiconductor package of claim 1, wherein the conductive member is composed of tungsten.
In the same field of endeavor, Yang teaches the semiconductor package of claim 1, wherein the conductive member (Conductive vias; 78; Fig 6; ¶[0038]) is composed of tungsten (Tungsten; ¶[0038]; Per ¶[0038] additionally including (but not limited to): aluminum, gold, silver, nickel, copper, tungsten, titanium, tantalum, compounds thereof, alloys thereof, multiple layers thereof, composites thereof)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the bond pad structure as disclosed by Chittipeddi in view of Choi by making the conductive member composed of tungsten, as disclosed by Yang. One of ordinary skill in the art would have been motivated to make this modification in order for the bond pad structure to sustain and better disperse the stresses exerted on it by a wire bonding process, as tungsten is noteably stronger, denser, and more resistant to thermal deformation and conductive vias 78 are used mainly for increasing structural strength, as disclosed by Yang (¶¶[0004, 0038]).
Re Claim 14 (Previously Presented), Chittipeddi in view of Choi does not teach the semiconductor package of claim 9, wherein the conductive member is composed of tungsten.
In the same field of endeavor, Yang teaches the semiconductor package of claim 1, wherein the conductive member (Conductive vias; 78; Fig 6; ¶[0038]) is composed of tungsten (Tungsten; ¶[0038]; Per ¶[0038] additionally including (but not limited to): aluminum, gold, silver, nickel, copper, tungsten, titanium, tantalum, compounds thereof, alloys thereof, multiple layers thereof, composites thereof)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the bond pad structure as disclosed by Chittipeddi in view of Choi by making the conductive member composed of tungsten, as disclosed by Yang. One of ordinary skill in the art would have been motivated to make this modification in order for the bond pad structure to sustain and better disperse the stresses exerted on it by a wire bonding process, as tungsten is noteably stronger, denser, and more resistant to thermal deformation and conductive vias 78 are used mainly for increasing structural strength, as disclosed by Yang (¶¶[0004, 0038]).
14. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Chittipeddi, Sailesh et al. (Pub No. US 5986343 A) (hereinafter, Chittipeddi) and Choi, Jayoung et al. (Pub No. US 20060207790 A1) (hereinafter, Choi) as applied to claim 9, and further in view of Maccioni, Alberto et al. (Pub No. US 20210389786 A1) (hereinafter, Maccioni).
Re Claim 12 (Previously Presented), Chittipeddi in view of Choi teaches the semiconductor package of claim 9, the perforated plate (Fourth metal layer; 624; Fig 6; Col 6 ln 45-50).
However, Chittipeddi in view of Choi does not teach the conductive member has a honeycomb structure in a top-down view.
In the same field of endeavor, Maccioni teaches the conductive member (Plasmonic layer (not shown) above membrane 62 with hexagonal pattern; Fig 5B; ¶[0097]; Note: Per ¶[0097] the an additional plasmonic layer is patterned with metal or dielectric material, embedded in membrane 62, in a periodic pattern) has a honeycomb structure (Periodic hexagonal pattern of holes; ¶[0097]) in a top-down view.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the bond pad structure as disclosed by Chittipeddi in view of Choi by modifying the perforated plate to have a honeycomb structure, as disclosed by Maccioni. One of ordinary skill in the art would have been motivated to make this modification such that porous material such as a hexagonal/honeycomb pattern may improve the emissivity and/or spectrum profile of heat being dissipated through the bond pad structure layers, as suggested by Maccioni (¶[0097]).
15. Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Li, Yu-Hsien et al. (Pub No. US 20220367554 A1) (hereinafter, Li) and further in view of Chittipeddi, Sailesh et al. (Pub No. US 5986343 A) (hereinafter, Chittipeddi).
Re Claim 16 (Previously Presented), Li teaches a method of manufacturing a semiconductor package (Figs 1 and 17-35; Note: Figs 17-35 are drawn to a method of manufacturing a semiconductor package, Fig 1 is an embodiment of a semiconductor package according to Li), comprising:
forming a semiconductor die (IC Chip; 1700; Fig 17; ¶[0102]), including:
forming a circuit (Semiconductor device; 1402; Fig 17; ¶[0088]; Per ¶[0088] semiconductor device 1402 forms circuitry supporting operation of pixel sensors) in a semiconductor substrate (108; Fig 17; ¶[0103]);
depositing one or more conductive layers (Wires; 110; Fig 29; ¶[0084]), including a second conductive layer (Uppermost wire; 110; Fig 29; ¶[0084]), and
one or more insulation layers (Intermediate dielectric layers, i.e. IMD layers; 122; Figs 1/29; ¶[0047]), including a top insulation layer (Interlayer dielectric layer, i.e. ILD layer; 116; Figs 1/29), above the semiconductor substrate, the top insulation layer above and abutting the second conductive layer;
etching (Patterning 122u; Fig 27; ¶[0120]) a plurality of trenches (Openings; 2704; Fig 27; ¶[0120]) in the top insulation layer (Upper IMD layer; 122u; ¶[0120]) to form multiple insulation members (Wire openings; 2702; Fig 27; ¶[0120]);
depositing a conductive material (Depositing a metal layer covered upper IMD 112u to fill wire openings 2702; Figs 27/28; ¶[0122]) in the plurality of trenches to form a conductive member (Inter-wire vias; 112; Fig 28; ¶[0121]), the multiple insulation members embedded within the conductive member; and
depositing a first conductive layer (Wires and bond pad structure; 110/102; Fig 28; ¶[0123]; Note: See Fig 35 of Li below) above and abutting the conductive member and the multiple insulation members;
covering the semiconductor die (3500; Fig 35) and the bond wire (Bond wires; 110b; Fig 35; ¶[0030]) with a mold compound (Backside dielectric layer; 128; Fig 35; ¶[0132]).
Li, Fig 35: Embodiment of semiconductor package illustrating first conductive layer
PNG
media_image2.png
436
666
media_image2.png
Greyscale
However, Li does not teach bonding a bond wire to a top surface of the first conductive layer.
In the same field of endeavor, Chittipeddi teaches bonding a bond wire (Wire; 230; Fig 6; Col 4 ln 45-49) to a top surface of the first conductive layer (Bond pad; 103; Fig 6; Col 4 ln 35-40).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the bond pad structure as disclosed by Li by adding the bond wire to a top surface of the first conductive layer, as disclosed by Chittipeddi. One of ordinary skill in the art would have been motivated to make this modification such that wires must ultimately be attached to the bond pads to connect to the external pins of the completed integrated circuit package, as suggested by Chittipeddi (Col 1 ln 30-35)
16. Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Li, Yu-Hsien et al. (Pub No. US 20220367554 A1) (hereinafter, Li) in view of Chittipeddi, Sailesh et al. (Pub No. US 5986343 A) (hereinafter, Chittipeddi) as applied to claim 16, and further in view of Yang, Chin-Tien et al. (Pub No. US 20060091566 A1) (hereinafter, Yang).
Re Claim 18 (Original), Li in view of Chittipeddi does not teach the method of claim 16, wherein the conductive member is composed of tungsten.
In the same field of endeavor, Yang teaches the semiconductor package of claim 1, wherein the conductive member (Conductive vias; 78; Fig 6; ¶[0038]) is composed of tungsten (Tungsten; ¶[0038]; Per ¶[0038] additionally including (but not limited to): aluminum, gold, silver, nickel, copper, tungsten, titanium, tantalum, compounds thereof, alloys thereof, multiple layers thereof, composites thereof)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the bond pad structure as disclosed by Li in view of Chittipeddi by making the conductive member composed of tungsten, as disclosed by Yang. One of ordinary skill in the art would have been motivated to make this modification in order for the bond pad structure to sustain and better disperse the stresses exerted on it by a wire bonding process, as tungsten is noteably stronger, denser, and more resistant to thermal deformation and conductive vias 78 are used mainly for increasing structural strength, as disclosed by Yang (¶¶[0004, 0038]).
17. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Li, Yu-Hsien et al. (Pub No. US 20220367554 A1) (hereinafter, Li) in view of Chittipeddi, Sailesh et al. (Pub No. US 5986343 A) (hereinafter, Chittipeddi) as applied to claim 16, and further in view of Maccioni, Alberto et al. (Pub No. US 20210389786 A1) (hereinafter, Maccioni).
Re Claim 20 (Original), Li in view of Chittipeddi teaches the method of claim 16, wherein, in a top-down view, the conductive member (Fourth metal layer; 624; Fig 6; Col 6 ln 45-50 of Chittipeddi).
However, Li in view of Chittipeddi does not teach the method of claim 16, wherein, in a top-down view, the conductive member has a honeycomb structure.
In the same field of endeavor, Maccioni teaches the method of claim 16, wherein, in a top-down view, the conductive member (Plasmonic layer (not shown) above membrane 62; Fig 5B; ¶[0097]; Note: Per ¶[0097] the an additional plasmonic layer is patterned with metal or dielectric material, embedded in membrane 62, in a periodic pattern) has a honeycomb structure (Periodic hexagonal pattern of holes; ¶[0097]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the bond pad structure as disclosed by Li in view of Chittipeddi by modifying the perforated plate to have a honeycomb structure, as disclosed by Maccioni. One of ordinary skill in the art would have been motivated to make this modification such that porous material such as a hexagonal/honeycomb pattern may improve the emissivity and/or spectrum profile of heat being dissipated through the bond pad structure layers, as suggested by Maccioni (¶[0097]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOTHY EDWARD DUREN whose telephone number is (703)756-1426. The examiner can normally be reached 07:30 - 17:00 PST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/T.E.D./
Examiner
Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817