CTFR 17/855,573 CTFR 100840 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim and Specification Status The Examiner acknowledges the amendments to claims 1 and 11 in the Applicant’s response dated 19 February 2026. The claim amendments have been addressed below. The Examiner acknowledges the amendments to withdrawn claims 6 and 16 in the Applicant’s response dated 19 February 2026. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-2 and 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Daniel Tekleab et al. (US 2012/0217468 A1; hereinafter “Tekleab”) in view of Bunmi T. Adekore (US 2013/0043468 A1; hereinafter “Adekore”) . Regarding Claim 1 , Tekleab teaches an integrated circuit structure, comprising: a channel structure (30, Fig. 13, para [0038] describes a semiconductor layer comprised of a semiconducting material 30) on a drain contact layer (31, Fig. 13, para [0035] describes a highly conductive electrical layer 31 further described in para [0057] as contacts made to a drain 31), the channel structure having an opening extending there through (Fig. 14, para [0053] describes digging a trench through the channel layer 30); a gate dielectric layer on a bottom and along sides of the opening (25 and 26, Fig. 15, para [0054] describes a gate dielectric layer 26 wherein dielectric layer 25 is comprised of a same dielectric material forming a gate dielectric 25 and 26), the gate dielectric layer laterally surrounded by the channel structure (30, Fig. 18, wherein channel structure 30 can be seen laterally surrounding gate dielectric side walls 25); a gate electrode on and laterally surrounded by the gate dielectric layer (61, Fig. 18, para [0055] describes an inner gate structure 61); and a source contact layer on sides of a portion of the gate dielectric layer extending above the channel structure (35, Fig. 18, para [0050] describes monosilicon layer 35 further described in para [0057] as contacts made to a source 35). Tekleab fails to explicitly disclose the source contact layer having an uppermost surface above an uppermost surface of the gate dielectric layer. However, Adekore teaches a similar integrated circuit structure, comprising a source contact layer (510, Fig. 5, para [0108] describes a source contact electrode 510) having an uppermost surface above an uppermost surface of the gate dielectric layer (506, Fig. 5, para [0108] describes an insulating layer 506 which surrounds a gate electrode 508 wherein the source contact layer 510 can be seen extending above gate dielectric layer 506 in Fig. 5 and further wherein source contact layer 510 further includes electrical connections 514 which are disposed along an upper surface of a passivation layer 120 as describes in para [0117] wherein said passivation layer is disposed along an upper surface of the gate dielectric putting source contact layer extensions 514 further above an upper surface of the gate dielectric 506). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Tekleab with Adekore to further disclose an integrated circuit comprising a source contact layer having an uppermost surface above an uppermost surface of a gate dielectric layer in order to provide the well-known advantage of enabling a source contact layer to extend beyond a gate dielectric layer so as to decrease the chances of current leakage between device components when further metallization layers are deposited wherein said current leakage could reduce reliability and create undesirable effects in the integrated circuit structure. Regarding Claim 2 , the combination of Tekleab and Adekore teaches the integrated circuit structure of claim 1, wherein the opening extends partially into the drain contact layer (Tekleab, para [0053] describes etching a trench partially through drain contact layer 31). Regarding Claim 4 , the combination of Tekleab and Adekore teaches the integrated circuit structure of claim 1, wherein the source contact layer is continuous around the portion of the gate dielectric layer extending above the channel structure (Tekleab, 35, Fig. 22, para [0059] depicts wherein layer 35 may be continuously wrapped around the gate structure as shown in Fig. 22 wherein Fig. 22 is a further depiction of Fig. 21 and Fig. 18). Regarding Claim 5 , the combination of Tekleab and Adekore teaches the integrated circuit structure of claim 1, wherein the source contact layer includes discrete portions around the portion of the gate dielectric layer extending above the channel structure (Tekleab, Fig. 18 depicts discrete portions of the source contact layer 35 around gate dielectric layer 25 when viewed from cut A-A of Fig. 20 with gate dielectric layer 25 separating the two discrete portions of layer 35) . 07-21-aia AIA Claim s 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Bunmi T. Adekore (US 2013/0043468 A1; hereinafter “Adekore”) in view of Aaron Lilak et al. (US 2020/0006573 A1; hereinafter “Lilak”) . Regarding Claim 11 , Adekore teaches an integrated circuit structure, comprising: a channel structure (502 and 504, Fig. 5, para [0109] describes bilayers 502 and 504 which may create a channel region) on a drain contact layer (512, Fig. 5, para [0108] describes a drain electrode 512 wherein the channel structure 502 and 504 is on drain contact layer 512 through electrical connection between drift layer 106, buffer layer 104 and substrate 102), the channel structure having an opening extending there through (502 and 504, Fig. 5, para [0111] describes wherein channel layers 502 and 504 may have comprise a recessed trench forming an opening for a gate dielectric 506 and gate electrode 508 to be formed in); a gate dielectric layer on a bottom and along sides of the opening (506, Fig. 5, para [0111] describes an insulating layer 506 for a gate electrode 508 deposited in the opening formed along a bottom surface and along sides of the opening formed in channel layers 502 and 504 and drift layer 106), the gate dielectric layer laterally surrounded by the channel structure (506, 502 and 504, Fig. 5, para [0111] describes wherein the gate dielectric layer 506 is disposed between portions of channel layer 502 and 504 resulting in the channel layers 502 and 504 laterally surrounding gate dielectric layer 506); a gate electrode on and laterally surrounded by the gate dielectric layer (508 and 506, Fig. 5, para [0113] describes forming a gate electrode 508 on the gate dielectric layer 506 wherein the gate dielectric 506 laterally surrounds the gate electrode 508 as shown in Fig. 5); and a source contact layer on sides of a portion of the gate dielectric layer extending above the channel structure (510, Fig. 5, para [0108] describes source electrodes 510 on sides of a portion of the gate dielectric layer 508 and extending above the channel layers 502 and 504), the source contact layer having an uppermost surface above an uppermost surface of the gate dielectric layer (506, Fig. 5 depicts wherein the source contact layer 510 can be seen extending above gate dielectric layer 506 and further wherein source contact layer 510 further includes electrical connections 514 which are disposed along an upper surface of a passivation layer 120 as describes in para [0117] wherein said passivation layer is disposed along an upper surface of the gate dielectric putting source contact layer extensions 514 further above an upper surface of the gate dielectric 506). Adekore fails to teach a computing device comprising a board; and a component coupled to the board, the component including an integrated circuit structure. However, Lilak teaches a similar integrated circuit structure, wherein Lilak teaches a computing device (800, Fig. 8, para [0100] describes a computing device 800) comprising: a board (802, Fig. 8, para [0100] describes a board 802); and a component coupled to the board (804, Fig. 8, para [0100] describes a processor coupled to the board 802), the component including an integrated circuit structure (para [0103] describes the processor including an integrated circuit die). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Adekore with Lilak to further disclose a computing device comprising a board and a component including an integrated circuit coupled to the board in order to provide the advantage of enabling an integrated circuit structure to be used in larger scale electronic devices such as in computer systems or personal electronics (Lilak, para [0099] and para [0106]). Regarding Claim 12 , the combination of Adekore and Lilak teaches the computing device of claim 11, further comprising: a memory coupled to the board (Lilak, DRAM, Fig. 8, para [0101] describes memory such as volatile memory DRAM, non-volatile memory ROM and/or flash memory coupled to the board 802). Regarding Claim 13 , the combination of Adekore and Lilak teaches the computing device of claim 11, further comprising: a communication chip coupled to the board (Lilak, 806, Fig. 8, para [0100] describes a communication chip 806 coupled to board 802). Regarding Claim 14 , the combination of Adekore and Lilak teaches the computing device of claim 11, wherein the component is a packaged integrated circuit die (Lilak, 804, Fig.8, para [0103] describes wherein the processor 804 of the computing device 800 includes an integrated circuit board packaged within the processor). Regarding Claim 15 , the combination of Adekore and Lilak teaches the computing device of claim 11, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor (Lilak, 804, Fig.8, para [0103] describes wherein a component coupled to the board 802 is a processor 804 of the computing device 800 which includes an integrated circuit board packaged within the processor). Response to Arguments Applicant’s arguments with respect to claims 1-2, 4-5 and 11-15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Friday 8:00 am - 4:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571(272)-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898 Application/Control Number: 17/855,573 Page 2 Art Unit: 2898 Application/Control Number: 17/855,573 Page 3 Art Unit: 2898 Application/Control Number: 17/855,573 Page 4 Art Unit: 2898 Application/Control Number: 17/855,573 Page 5 Art Unit: 2898 Application/Control Number: 17/855,573 Page 6 Art Unit: 2898 Application/Control Number: 17/855,573 Page 7 Art Unit: 2898 Application/Control Number: 17/855,573 Page 8 Art Unit: 2898 Application/Control Number: 17/855,573 Page 9 Art Unit: 2898
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