CTFR 17/855,608 CTFR 89298 DETAILED ACTION This Office Action is sent in response to Applicant’s Communication received 04 Feb 2026 for application number 17/855,608. The Office hereby acknowledges receipt of the following and placed of record in file: Applicant Arguments/Remarks, and Claims. Claims 1-20 are presented for examination. Elected claims 1, 3-5, and 11-15 are examined below; non-elected claims 2, 6-10, and 16-20 have been withdrawn. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Objections 07-29-01 AIA Claim s 11-15 are objected to because of the following informalities: regarding claim 11, the phrase, “the gate electrode having an uppermost surface below uppermost surface of the channel structure”, on lines 8-10, seems grammatically incorrect (an “an” should replace the “and”, similar to the amendment of claim 1). Dependent claims 12-15 are objected to because they inherit the deficiency . Appropriate correction is required. Response to Arguments The objections to claims 1 and 3-5 have been removed in light of amendments. Examiner respectfully requests attention to the objection to claims 11-15. Regarding arguments to the 102/103 rejections, Applicant contends that the prior art does not teach, “ a channel structure having a recess…of the surface of the channel structure ”; Examiner respectfully disagrees. Chen teaches An integrated circuit structure, comprising: a channel structure [channel regions around recesses; Figs. 15A, 18, para 0059] having a recess [recess 100; Figs. 15A, 18, para 0059] extending partially there through; a gate dielectric layer [gate dielectric 112; Figs. 15G, 18, para 0084] on a bottom and along sides of the recess [100] , the gate dielectric layer [112] laterally surrounded by the channel structure [channel region] ; a gate electrode [gate electrode 114; Figs. 15G, 18, para 0084] on and laterally surrounded by the gate dielectric layer [112] , the gate electrode [114] having an uppermost surface below an uppermost surface of the channel structure [Fig. 18 depicts the upper most surface of 114 below the uppermost surface of the channel region] . Applicant seems to argue that, “a recess extending partially there through” does not exist. Examiner respectfully disagrees. A recess 100 is clearly present in Chen. The current claim language does not further specify the nature of the recess, i.e. no language exists specifying whether the recess is filled, and/or what material the recess is filled with. In Chen, a recess 100 is created and present, but is filled with material. Therefore, broadly and reasonably interpreting the current claim language, the prior art teaches, “ a channel structure having a recess…of the surface of the channel structure .” Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim(s) 1 and 3-5 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen et al. [hereinafter as Chen] (US 2024/0266397 A1) . In reference to claim 1 , Chen teaches An integrated circuit structure, comprising: a channel structure [channel regions around recesses; Figs. 15A, 18, para 0059] having a recess [recess 100; Figs. 15A, 18, para 0059] extending partially there through; a gate dielectric layer [gate dielectric 112; Figs. 15G, 18, para 0084] on a bottom and along sides of the recess [100] , the gate dielectric layer [112] laterally surrounded by the channel structure [channel region] ; a gate electrode [gate electrode 114; Figs. 15G, 18, para 0084] on and laterally surrounded by the gate dielectric layer [112] , the gate electrode [114] having an uppermost surface below an uppermost surface of the channel structure [Fig. 18 depicts the upper most surface of 114 below the uppermost surface of the channel region] . In reference to claim 3 , Chen teaches The integrated circuit structure of claim 1, wherein the channel structure [channel region] is a nanowire-based channel structure [para 0011 discloses a nanowire structure] . In reference to claim 4 , Chen teaches The integrated circuit structure of claim 1, wherein the gate electrode [114] has a rounded profile [Figs. 15G, 18, para 0085 disclose that 114 has a rounded profile (last sentence)] . In reference to claim 5 , Chen teaches The integrated circuit structure of claim 1, further comprising an insulating material [upper portion 81U of spacer 81; Figs. 15G, 18, para 0085] along upper portions of the recess [100] . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim (s) 11-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Ramaswamy et al. [hereinafter as Ramaswamy] (US 2019/0348516 A1) In reference to claim 11 , Chen teaches an integrated circuit structure, comprising: a channel structure [channel regions; Figs. 15A, 18, para 0059] having a recess [recess 100; Figs. 15A, 18, para 0059] extending partially there through; a gate dielectric layer [gate dielectric 112; Figs. 15G, 18, para 0084] on a bottom and along sides of the recess [100] , the gate dielectric layer [112] laterally surrounded by the channel structure [channel region] ; a gate electrode [ gate electrode 114; Figs. 15G, 18, para 0084] on and laterally surrounded by the gate dielectric layer [112] , the gate electrode [114] having an uppermost surface below uppermost surface of the channel structure [Fig. 18 depicts the upper most surface of 114 below the uppermost surface of the channel region] . However, Chen does not explicitly teach A computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure . Ramaswamy teaches A computing device [computing device 2300; Fig. 8, para 0097] , comprising: a board [circuit board 2202; Figs. 7-8, paras 0093-0094] ; and a component coupled to the board [2202] , the component including an integrated circuit structure [IC device assembly 2200; Figs. 7-8, paras 0093-0094] . It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Chen and Ramaswamy before the effective filing date of the claimed invention, to include the computing device and component as disclosed by Ramaswamy into the device of Chen in order to obtain a computing device coupled to an integrated circuit structure. One of ordinary skill in the art would be motivated to obtain a computing device coupled to an integrated circuit structure to provide the predictable result of providing increased performance, energy efficiency, and miniaturization in a computing device. In reference to claim 12 , Chen and Ramaswamy teach the invention of claim 11. Ramaswamy teaches The computing device of claim 11, further comprising: a memory [memory 2304; Fig. 8, para 0097] coupled to the board [2202] . In reference to claim 13 , Chen and Ramaswamy teach the invention of claim 11. Ramaswamy teaches The computing device of claim 11, further comprising: a communication chip [communication chip 2312; Fig. 8, para 0098] coupled to the board [2202] . In reference to claim 14 , Chen and Ramaswamy teach the invention of claim 11. Ramaswamy teaches The computing device of claim 11, wherein the component is a packaged integrated circuit die [IC package 2220; para 0090] . In reference to claim 15 , Chen and Ramaswamy teach the invention of claim 11. Ramaswamy teaches The computing device of claim 11, wherein the component is selected from the group consisting of a processor [processing device 2302; Fig. 8, para 0097] , a communications chip [2312] , and a digital signal processor [digital signal processor; para 0097] . Examiner’s Note 07-96 AIA The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure as follows. Applicant is reminded that in amending in response to a rejection of claims, the patentable novelty must be clearly shown in view of the state of the art disclosed by the references cited and the objections made. Applicant must also show how the amendments avoid such references and objections. See 37 CFR § 1.111(0) . Ramaswamy et al. (US-20190348516-A1) discloses channel regions with recesses [Fig. 4H] . Conclusion 07-39 AIA THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW CHUNG whose telephone number is (571)272-5237. The examiner can normally be reached M-F 9-5pm . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached on 571-272-2339 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANDREW CHUNG/ Examiner, Art Unit 2898 Application/Control Number: 17/855,608 Page 2 Art Unit: 2898 Application/Control Number: 17/855,608 Page 3 Art Unit: 2898 Application/Control Number: 17/855,608 Page 4 Art Unit: 2898 Application/Control Number: 17/855,608 Page 5 Art Unit: 2898 Application/Control Number: 17/855,608 Page 6 Art Unit: 2898 Application/Control Number: 17/855,608 Page 7 Art Unit: 2898 Application/Control Number: 17/855,608 Page 8 Art Unit: 2898
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