DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 35 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
In claim 35, line 3, the limitation “the surface of the 2D layer” renders the claim indefinite because it is unclear as to which surface of the 2D layer applicant refers (i.e., the first surface or the second surface). For examination purposes, the limitation in question will be interpreted as: at least one of the first surface and the second surface of the 2D layer. Correction is respectfully requested.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 26-34 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 26 and 28-31 of copending Application No. 17/855,626 (reference application) in view of US 2022/0285345 A1 (hereinafter “Hung”).
This is a provisional nonstatutory double patenting rejection.
Line numbers cited below refer to the Listing of Claims filed October 6, 2025 in the reference application.
Regarding instant claim 26, claim 26 of the reference application recites a transistor structure comprising (line 1):
a 2D layer (line 6);
a cap layer with a first side and a second side opposite the first side (line 7);
a dielectric layer, wherein a side of the dielectric layer is on the second side of the cap layer (lines 9-10);
a source that extends through the dielectric layer and through the cap layer to the surface of the 2D layer (lines 11-12);
a drain that extends through the dielectric layer and through the cap layer to the surface of the 2D layer (lines 13-14);
wherein a portion of the source extends along a first portion of the side of the dielectric layer, wherein a portion of the drain extends along a second portion of the side of the dielectric layer, and wherein a portion of the cap layer is between the portion of the source and the portion of the drain (lines 15-18).
Claim 26 of the reference application does not recite the 2D layer having a first surface vertically above a second surface, the first side of the cap layer is on the first surface of the 2D layer, a gate electrode below the second surface of the 2D layer, and a metal contact beneath and coupled to the gate electrode.
Hung teaches in Fig. 15 and related text the 2D layer (140a; [0042]) having a first surface (S140t; [0085]) vertically above a second surface (a bottom surface), the first side of the cap layer (150; [0085]) is on the first surface of the 2D layer, a gate electrode (120; [0030]) below the second surface of the 2D layer, and a metal contact (104; [0029]) beneath and coupled to the gate electrode.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the 2D layer to have a first surface vertically above a second surface, to arrange the first side of the cap layer to be on the first surface of the 2D layer, to provide a gate electrode below the second surface of the 2D layer, and to provide a metal contact beneath and coupled to the gate electrode, as taught by Hung, in order to obtain a field effect transistor structure in which a gate electrode is used to control the conductance of a channel located in the 2D layer, wherein the metal contact provides a gate voltage to the gate electrode.
Regarding instant claim 27, claim 26 of the reference application in view of Hung recites the transistor structure of instant claim 26.
Claims 26 and 27 of the reference application do not recite the source and the drain are substantially perpendicular to a plane of the first surface of the 2D layer.
Hung teaches in Fig. 15 and related text the source (160 (one of the two shown); [0053]) and the drain (160 (the other of the two shown); [0053]) are substantially perpendicular to a plane of the first surface (S140t; [0085]) of the 2D layer (140a; [0042]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the source and the drain to be substantially perpendicular to a plane of the first surface of the 2D layer, as taught by Hung, in order to minimize a parasitic capacitance between the gate electrode and each of the source and the drain.
Regarding instant claim 28, claim 28 of the reference application recites the source and the drain are substantially parallel to each other (lines 1-2).
Regarding instant claim 29, claim 29 of the reference application recites the source and the drain extend into the 2D layer (lines 1-2).
Regarding instant claim 30, claim 30 of the reference application recites the cap layer includes a selected one or more of: Al, La, Hf, Ti, Zr, O, Al2O3, La2O3, HfO2, ZrO2, and/or TiO2 (lines 1-2).
Regarding instant claim 31, claim 31 of the reference application recites the dielectric layer includes a selected one or more of: silicon, oxygen, or nitrogen (lines 1-2).
Regarding instant claim 32, claim 26 of the reference application recites an oxide layer (line 5); and wherein the 2D layer is on the oxide layer (line 6).
Regarding instant claim 33, claim 26 of the reference application does not explicitly recite the oxide layer is between the 2D layer and the gate electrode.
Hung teaches in Fig. 15 and related text the oxide layer (130; [0039]) is between the 2D layer (140a; [0042]) and the gate electrode (120; [0030]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to arrange the oxide layer to be between the 2D layer and the gate electrode, as taught by Hung, in order to use the oxide layer as a gate dielectric layer of a field effect transistor.
Regarding instant claim 34, claim 32 of the reference application does not explicitly recite the gate electrode includes one or more of: copper, aluminum, cobalt, titanium, nitrogen, or tungsten.
Hung teaches in Fig. 15 and related text the gate electrode (120; [0030]) includes one or more of: copper, aluminum, cobalt, titanium, nitrogen, or tungsten ([0035]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the gate electrode to include one or more of: copper, aluminum, cobalt, titanium, nitrogen, or tungsten, as taught by Hung, in order to ensure a sufficiently high electrical conductivity of the gate electrode.
Claims 37 and 38 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 26 of copending Application No. 17/855,626 (reference application) in view of Hung, and further in view of US 2020/0091156 A1 (hereinafter “Sharma”).
This is a provisional nonstatutory double patenting rejection.
Regarding instant claim 37, claim 26 of the reference application in view of Hung recites the transistor structure of instant claim 26.
Claim 26 of the reference application does not recite a capacitor structure on the transistor structure, wherein the capacitor structure is electrically coupled with the drain.
Sharma teaches in Fig. 4A and related text a capacitor structure (232; [0076]) on the transistor structure (210; [0031] and [0076]), wherein the capacitor structure is electrically coupled with the drain (412; [0052], [0066] and [0076]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form a capacitor structure on the transistor structure, wherein the capacitor structure is electrically coupled with the drain, as taught by Sharma, in order to form a 2T (i.e., two transistor) memory cell having an improved retention time and a high integration density (Sharma: [0024]-[0025] and [0029]).
Regarding instant claim 38, claim 26 of the reference application in view of Hung, and further in view of Sharma, recites the transistor structure of instant claim 37.
Claim 26 of the reference application does not recite the transistor structure is included in a plurality of transistor structures, wherein the capacitor structure is included in a plurality of capacitor structures, and wherein the plurality of transistor structures and capacitor structures are physically coupled with each other.
Sharma teaches in Fig. 4A and related text the transistor structure is included in a plurality of transistor structures (210; [0076]), wherein the capacitor structure is included in a plurality of capacitor structures (232; [0076]), and wherein the plurality of transistor structures and capacitor structures are physically coupled with each other ([0051] and [0077]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to provide a plurality of transistor structures including the transistor structure, and to provide a plurality of capacitor structures including the capacitor structure, wherein the plurality of transistor structures and capacitor structures are physically coupled with each other, as taught by Sharma, in order to form an array of 2T (i.e., two transistor) memory cells having an improved retention time and a high integration density (Sharma: [0024]-[0025], [0029] and [0066]).
Allowable Subject Matter
Claim 35 would be allowable if rewritten to overcome the rejection under 35 U.S.C. 112(b) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the claims of copending application 17/855,626 do not explicitly recite, and the prior art of record does not teach, “the second oxide layer at least partially surrounds the source, the drain, the dielectric layer, the 2D layer, the first oxide layer, and the gate electrode” as recited in claim 35.
Response to Arguments
Applicant’s arguments with respect to claim(s) 26 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M ALBRECHT whose telephone number is (571)272-7813. The examiner can normally be reached M-F 9:30 AM - 6:30 PM (CT).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at (571) 272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER M ALBRECHT/Primary Examiner, Art Unit 2811