DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pihlman (USPGPUB DOCUMENT: 2017/0290158, hereinafter Pihlman) in view of Nelson (USPGPUB DOCUMENT: 2017/0077029, hereinafter Nelson) and Lo (USPGPUB DOCUMENT: 20190384185, hereinafter Lo).
Re claim 1 Pihlman discloses an apparatus comprising: a substrate(package substrate)[0027]; a plurality of devices(201/125) on the substrate(package substrate)[0027]; a plurality of electrically conductive traces(left/right 235A) on the substrate(package substrate)[0027], wherein each of the plurality of electrically conductive traces(left/right 235A) has a first end(outermost end) and a second end opposite the first end(outermost end), and wherein each of the plurality of electrically conductive traces(left/right 235A) is electrically coupled(by way of 341/351/352) at the first end(outermost end), respectively, with each of the plurality of devices(201/125);, and wherein the each of the plurality of electrically conductive traces(left/right 235A) are not directly electrically coupled with each other; and wherein the plurality of devices(201/125) are electrically coupled(by way of 236/351/341/331) with a ground(235C/235D/204)[0035].
Pihlman does not disclose a wafer substrate; a plurality of devices on the wafer substrate; a plurality of electrically conductive traces(left/right 235A) on the wafer substrate, wherein the second end of the each of the plurality of electrical traces(235A) is within a scan area on the substrate(package substrate)[0027],
Nelson disclose in Fig 33 wherein the second end of the each of the plurality of electrical traces(3312) is within a scan area[0085 of Nelson][0139] on the substrate[0205],
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Nelson to the teachings of Pihlman in order to enable increased densities of functional units on the limited real estate of semiconductor chips [0003, Nelson].
Pihlman and Nelson does not disclose a wafer substrate; a plurality of devices on the wafer substrate; a plurality of electrically conductive traces(left/right 235A) on the wafer substrate,
Lo disclose in Fig 6/7 a wafer substrate[0018,0021,0040,0046]; a plurality of devices(multiple 600)[0040] on the wafer substrate;
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Lo to the teachings of Pihlman in order to have the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology [0001, Lo]. In doing so, a plurality of electrically conductive traces(left/right 235A) on the wafer substrate[0018,0021,0040,0046 of Lo],
Re claim 2 Pihlman and Nelson and Lo disclose the apparatus of claim 1, wherein the plurality of electrically conductive traces(left/right 235A) is a first plurality of electrically conductive traces(left/right 235A); and further comprising: a second plurality of electrically conductive traces(left/right 235A) on the wafer substrate[0018,0021,0040,0046 of Lo], wherein each of the second plurality of electrically conductive traces(left/right 235A) is electrically coupled, respectively, with each of the plurality of devices(201/125); and wherein each of the second plurality of electrically conductive traces(left/right 235A) is electrically coupled with the ground(235C/235D/204)[0035].
Re claim 3 Pihlman and Nelson and Lo disclose the apparatus of claim 1, wherein the plurality of devices(201/125) include components of a transistor[0149 of Nelson] structure.
Re claim 4 Pihlman and Nelson and Lo disclose the apparatus of claim 1, wherein a first port of each of the plurality of devices(201/125) is directly electrically coupled, respectively, with the first end(outermost end) of the each of the plurality of electrically conductive traces(left/right 235A), and wherein a second port of each of the plurality devices(201/125) is electrically coupled with the ground(235C/235D/204)[0035].
Re claim 5 Pihlman and Nelson and Lo disclose the apparatus of claim 1, wherein the ground(235C/235D/204)[0035] is a ground(235C/235D/204)[0035] of the wafer substrate[0018,0021,0040,0046 of Lo].
Re claim 6 Pihlman and Nelson and Lo disclose the apparatus of claim 1, wherein the plurality of devices(201/125), the plurality of electrically conductive traces(left/right 235A), and the scan area[0085 of Nelson] are on a same side of the wafer substrate[0018,0021,0040,0046 of Lo].
Re claim 7 Pihlman and Nelson and Lo disclose the apparatus of claim 1, wherein a dimension of the scan area[0085 of Nelson] is 1000 pm2 or less.
Re claim 8 Pihlman and Nelson and Lo disclose the apparatus of claim 1, wherein the first end(outermost end) of each of the plurality of electrically conductive traces(left/right 235A) includes a structure to facilitate electrical coupling with its respective device.
Re claim 9 Pihlman and Nelson and Lo disclose the apparatus of claim 1, wherein the second end of the each of the plurality of electrically conductive traces(left/right 235A) are arranged in a grid pattern within the scan area[0085 of Nelson].
Re claim 10 Pihlman and Nelson and Lo disclose the apparatus of claim 1, wherein the plurality of devices(201/125) are arranged on the wafer substrate[0018,0021,0040,0046 of Lo] in a grid pattern(see Fig 33 of Nelson).
Re claim 11 Pihlman and Nelson and Lo disclose the apparatus of claim 1, wherein each of the plurality of devices(201/125) further include a plurality of sub devices(201/125).
Re claim 12 Pihlman and Nelson and Lo disclose the apparatus of claim 11, wherein a first of the each of the plurality of sub devices(201/125) is electrically coupled with the ground(235C/235D/204)[0035], wherein a second of the each of the plurality of sub devices(201/125) is electrically coupled with one of the plurality of electrically conductive traces(left/right 235A), and wherein the plurality of sub devices(201/125) are electrically coupled with each other in series[0042].
Re claim 13 Pihlman and Nelson and Lo disclose the apparatus of claim 11, wherein each of the plurality of sub devices(201/125) is electrically coupled with the ground(235C/235D/204)[0035], and each of the plurality of sub devices(201/125) is electrically coupled with one of the plurality of electrically conductive traces(left/right 235A).
Re claim 14 Pihlman and Nelson and Lo disclose the apparatus of claim 1, wherein a brightness of a second end of one of the electrically conductive traces(left/right 235A) during an electronic beam scan identifies whether the device corresponding with the one of the plurality of electrically conductive traces(left/right 235A) has a short defect[0102 of Nelson] or an open defect.
Re claim 15 Pihlman and Nelson and Lo disclose the apparatus of claim 1, wherein the plurality of electrically conductive traces(left/right 235A) include signal lines that include a metal.
Re claim 16 Pihlman and Nelson and Lo disclose the apparatus of claim 15, wherein the metal includes copper[0147 of Nelson].
Re claim 17 Pihlman discloses a wafer(wafer)[0027] comprising: a plurality of areas(areas of 201/125) on a surface of the wafer(wafer)[0027]; and a plurality of electrically conductive traces(left/right 235A), each of the plurality of electrically conductive traces(left/right 235A) extending, respectively, to an electrical contact(by way of 341/351/352) in each of the plurality of areas(areas of 201/125), wherein the plurality of electrically conductive traces(left/right 235A) are not directly electrically coupled with each other.
Pihlman does not disclose a plurality of areas on a surface of a wafer substrate; a scan area on the surface of the wafer substrate; a scan area[0085 of Nelson] on the surface of the wafer(wafer)[0027]; each of the plurality of electrically conductive traces(left/right 235A) extending from the scan area[0085 of Nelson],
Nelson disclose in Fig 33 a scan area[0085 of Nelson] on the surface of the wafer(wafer)[0137]; each of the plurality of electrically conductive traces(top/middle/bottom 3312) extending from the scan area[0085 of Nelson][0139],
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Nelson to the teachings of Pihlman in order to enable increased densities of functional units on the limited real estate of semiconductor chips [0003, Nelson].
Pihlman and Nelson does not disclose a plurality of areas on a surface of a wafer substrate; a scan area on the surface of the wafer substrate;
Lo disclose in Fig 6/7 a plurality of areas on a surface of a wafer substrate[0018,0021,0040,0046]; a scan area on the surface of the wafer substrate(scan area at top of 704/705)[0044];
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Lo to the teachings of Pihlman in order to have the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology [0001, Lo].
Re claim 18 Pihlman and Nelson and Lo disclose the wafer(wafer)[0027] of claim 17, further comprising a plurality of devices(201/125), wherein one or more of the plurality of devices(201/125) are located, respectively, in each of the plurality of areas(areas of 201/125) on the surface of the wafer substrate[0018,0021,0040,0046 of Lo].
Re claim 19 Pihlman and Nelson and Lo disclose the wafer [0018,0021,0040,0046 of Lo] of claim 18, wherein for each of the plurality of areas(areas of 201/125) on the surface of the wafer substrate[0018,0021,0040,0046 of Lo], the one or more of the plurality of devices(201/125) is electrically coupled with the electrical contact.
Re claim 20 Pihlman and Nelson and Lo disclose the wafer(wafer)[0027] of claim 17, wherein the plurality of areas(areas of 201/125) are arranged in a grid pattern.
Re claim 21 Pihlman and Nelson and Lo disclose the wafer(wafer)[0027] of claim 17, wherein the scan area[0085 of Nelson] is separate and distinct from the plurality of areas(areas of 201/125), and wherein a dimension of the scan area[0085 of Nelson] has a length of 100 pm or less and a width of 100 pm or less.
Re claim 22 Pihlman and Nelson and Lo disclose the wafer(wafer)[0027] of claim 17, wherein the electrical contact in the each of the plurality of areas(areas of 201/125) at least partially surrounds the each of the plurality of areas(areas of 201/125).
Response to Arguments
Applicant’s arguments with respect to claim 1 & 17 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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