DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/10/2026 has been entered.
Status of the Application
Acknowledgement is made of the amendment received on 6/10/2026. Claims 1-20 and 22-25 are pending in this application. Claims 1 and 15 are amended. Claims 23-25 remain withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 9, 15-17, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Guha et al. (US 2020/0091348; hereinafter ‘Guha’) in view of THEN et al. (US 2017/0263708; hereinafter ‘THEN’).
Regarding claim 1, Guha teaches a transistor (300, FIG. 3, [0010, 0055]), comprising:
a channel (a vertical arrangement of 154, FIG. 1B, [0031]; hereinafter ‘CH’) with a first end (a left end of CH; hereinafter LCH) and a second end (a right end of CH; hereinafter RCH) opposite from the first end (RCH opposite from LCH);
a first spacer (left 162; hereinafter ‘L162’) around the first end of the channel (L162 around LCH);
a second spacer (right 162; hereinafter ‘R162’) around the second end of the channel (R162 around RCH);
a gate stack (160) over the channel (160 over CH), wherein the gate stack is between the first spacer and the second spacer (160 is between L162 and R162);
a first extension (left 170; hereinafter ‘L170’) contacting the first end of the channel (L170 contacting LCH);
a second extension (right 170; hereinafter ‘R170’) contacting the second end of the channel (R170 contacting RCH); and
conductive layers (155 and 157; hereinafter ‘CL’) over the first extension and the second extension outside of the first spacer and the second spacer (CL over L170 and R170 outside of L162 and R162).
Guha does not teach the transistor comprising the conductive layers having a bottommost surface at a same level as a bottommost surface of the gate stack in a cross-sectional view, the conductive layers having an uppermost surface at a same level as an uppermost surface of the gate stack in the cross-sectional view, and the conductive layers continuous from the uppermost surface of the gate stack to the bottommost surface of the gate stack in the cross-sectional view.
THEN teaches a transistor (FIG. 4E, [0013]) comprising
the conductive layers (222A and 232A, [0027-0028]; hereinafter ‘CL’) having a bottommost surface at a same level as a bottommost surface of the gate stack in a cross-sectional view (CL having a bottommost surface at a same level as a bottommost surface of the gate stack 250A, FIG. 4E, [0025]),
the conductive layers having an uppermost surface at a same level as an uppermost surface of the gate stack in the cross-sectional view (CL having an uppermost surface at a same level as an uppermost surface of 250A, FIG. 4E), and
the conductive layers continuous from the uppermost surface of the gate stack to the bottommost surface of the gate stack in the cross-sectional view (CL continuous from the uppermost surface of 250A to the bottommost surface of 250A, FIG. 4E).
As taught by THEN, one of ordinary skill in the art would utilize and modify the above teaching into Guha to obtain and achieve the transistor comprising the conductive layers having a bottommost surface at a same level as a bottommost surface of the gate stack in a cross-sectional view, the conductive layers having an uppermost surface at a same level as an uppermost surface of the gate stack in the cross-sectional view, and the conductive layers continuous from the uppermost surface of the gate stack to the bottommost surface of the gate stack in the cross-sectional view as claimed, because continuous structures provide low-resistance conductive paths throughout the vertically stacked source and drain regions, while their limited vertical extend avoids unnecessary extension beyond the active device height and helps maintain a compact device structure, [0004, 0006, 0027-0028].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by THEN in combination with Guha due to the above reason.
Regarding claim 2, Guha in view of THEN teaches the transistor of claim 1, wherein the channel is a nanoribbon channel (Guha: CH interpreted to include a nanoribbon, [0026-0027]).
Regarding claim 3, Guha in view of THEN teaches the transistor of claim 1, wherein the channel is a nanowire channel (Guha: CH includes nanowire, [0031]).
Regarding claim 9, Guha in view of THEN teaches the transistor of claim 1, but does not explicitly teach the transistor wherein a width of the first extension and the second extension is up to approximately half of a width of the conductive layers.
Guha, however, provides FIG. 1B clearly depicting that the extensions 170 are formed significantly narrower than the conductive layers 155 and 157—approximately within the claimed proportion—thus inherently disclosing the claimed width relationship.
It would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose particular width of the first extension and the second extension, because applicant has not disclosed that, in view of the applied prior art, the width differences are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. For that matter, applicant has not disclosed that the width of the first extension and the second extension differences are for any purpose or produce any result. Moreover, it appears prima facie that the process would possess utility using another width differences. Indeed, it has been held that mere limitation is prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 15, Guha teaches a transistor device (300, FIG. 3, [0010, 0055]), comprising:
a stack of semiconductor channels (a stack of 154, FIG. 1B, [0031]; hereinafter ‘S154’);
a gate stack (160) over and around the stack of semiconductor channels (160 over and around S154);
spacers (162) at opposite ends of the gate stack (162 at opposite ends of 160);
extensions (170) at ends of individual ones of the semiconductor channels (170 at ends of individual ones of 154); and
conductive layers (155 and 157) around the extensions (170).
Guha does not teach the transistor comprising the conductive layers having a bottommost surface at a same level as a bottommost surface of the gate stack in a cross-sectional view, the conductive layers having an uppermost surface at a same level as an uppermost surface of the gate stack in the cross-sectional view, and the conductive layers continuous from the uppermost surface of the gate stack to the bottommost surface of the gate stack in the cross-sectional view.
THEN teaches a transistor (FIG. 4E, [0013]) comprising
the conductive layers (222A and 232A, [0027-0028]; hereinafter ‘CL’) having a bottommost surface at a same level as a bottommost surface of the gate stack in a cross-sectional view (CL having a bottommost surface at a same level as a bottommost surface of the gate stack 250A, FIG. 4E, [0025]),
the conductive layers having an uppermost surface at a same level as an uppermost surface of the gate stack in the cross-sectional view (CL having an uppermost surface at a same level as an uppermost surface of 250A, FIG. 4E), and
the conductive layers continuous from the uppermost surface of the gate stack to the bottommost surface of the gate stack in the cross-sectional view (CL continuous from the uppermost surface of 250A to the bottommost surface of 250A, FIG. 4E).
As taught by THEN, one of ordinary skill in the art would utilize and modify the above teaching into Guha to obtain and achieve the transistor comprising the conductive layers having a bottommost surface at a same level as a bottommost surface of the gate stack in a cross-sectional view, the conductive layers having an uppermost surface at a same level as an uppermost surface of the gate stack in the cross-sectional view, and the conductive layers continuous from the uppermost surface of the gate stack to the bottommost surface of the gate stack in the cross-sectional view as claimed, because continuous structures provide low-resistance conductive paths throughout the vertically stacked source and drain regions, while their limited vertical extend avoids unnecessary extension beyond the active device height and helps maintain a compact device structure, [0004, 0006, 0027-0028].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by THEN in combination with Guha due to the above reason.
Regarding claim 16, Guha in view of THEN teaches the transistor device of claim 15, wherein the extensions merge together to form a single body (Guha: 170 describes as non-discrete structures, [0035]).
Regarding claim 17, Guha in view of THEN teaches the transistor device of claim 15, wherein the extensions directly contact semiconductor channels and the spacers (Guha: 170 directly contact 154 and 162, FIG. 1B).
Regarding claim 22, Guha in view of THEN teaches the transistor device of claim 15, wherein a width of the conductive layers is approximately twice a width of the extensions or greater (Guha: the width of CL is greater than a width of 170, FIG. 1B).
Claims 4-5, 11, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Guha (US 2020/0091348) in view of THEN (US 2017/0263708) as applied to claims 1 and 15 above, and further in view of Naylor et al. (US 2022/0102499; hereinafter ‘Naylor’).
Regarding claim 4, Guha in view of THEN the transistor device of claim 1, but does not teach the transistor wherein the channel is a transition metal dichalcogenide (TMD).
Naylor teaches a transistor (100, FIG. 1, [0033]) wherein the channel (102) is a TMD (102 is a TMD, [0034]).
As taught by Naylor, one of ordinary skill in the art would utilize and modify the above teaching into Guha in view of THEN to obtain and achieve the transistor wherein the channel is a TMD as claimed, because a TMD is a two-dimensional semiconductor having strong electrostatic gate control, an atomically thin body, and a tunable bandgap, which enables further channel length scaling while suppressing short-channel effects and leakage current [0028, 0033-0036]. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Naylor in combination with Guha in view of THEN due to the above reason.
Regarding claim 5, Guha in view of THEN and Naylor teaches the transistor of claim 4, but Guha in view of THEN does not teach the transistor wherein the first extension and the second extension are metallic phase TMDs.
Naylor teaches the transistor wherein the first extension and the second extension (left 104 and right 104, FIG. 1, [0033]) are metallic phase TMDs (104 includes TMD that exhibit metallic behavior by doping or compositional modification, [0034, 0047]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Naylor to obtain and achieve the transistor, wherein the first extension and the second extension are metallic phase TMDs as claimed, because metallic phase TMDs provide low-resistance contacts to the semiconducting TMD channel, thereby improving carrier injection and overall transistor performance [0036, 0059].
Regarding claim 11, Guha in view of THEN teaches the transistor of claim 1, but Guha in view of THEN does not teach the transistor further comprising: a surface treatment layer over the first extension and the second extension.
Naylor teaches a transistor (100, FIG. 11, [0049]) further comprising: a surface treatment layer (a surface treatment layer, [0049]) over the first extension and the second extension (left 128 and right 128, [0047]).
As taught by Naylor, one of ordinary skill in the art would utilize and modify the above teaching into Guha in view of THEN to obtain and achieve the transistor further comprising: a surface treatment layer over the first extension and the second extension as claimed, because the surface treatment on the extensions is performed to improve the contact and interface properties, thereby reducing contact resistance and enhancing carrier injection.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Naylor in combination with Guha in view of THEN due to the above reason.
Regarding claim 19, Guha in view of THEN teaches the transistor device of claim 15, but does not teach the transistor device wherein the stack of semiconductor channels comprise transition metal dichalcogenide (TMD) materials.
Naylor teaches a transistor device (100, FIG. 22A, [0062]) wherein the stack of semiconductor channel (the stack of 102) comprise TMD materials (102 is a TMD, [0034]).
As taught by Naylor, one of ordinary skill in the art would utilize and modify the above teaching into Guha in view of THEN to obtain and achieve the transistor device wherein the stack of semiconductor channels comprise TMD materials as claimed, because a TMD is a two-dimensional semiconductor having strong electrostatic gate control, an atomically thin body, and a tunable bandgap, which enables further channel length scaling while suppressing short-channel effects and leakage current [0028, 0033-0036]. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Naylor in combination with Guha in view of THEN due to the above reason.
Regarding claim 20, Guha in view of THEN and Naylor teaches the transistor device of claim 19, but Guha in view of THEN does not explicitly teach the transistor device wherein the extensions comprise metallic phase TMD materials.
Naylor teaches the transistor device wherein the extensions (104, FIG. 1, [0033]) comprise metallic phase TMD materials (104 includes TMD that exhibit metallic behavior by doping or compositional modification, [0034, 0047]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Naylor to obtain and achieve the transistor device, wherein the extensions comprise metallic phase TMD materials as claimed, because metallic phase TMDs provide low-resistance contacts to the semiconducting TMD channel, thereby improving carrier injection and overall transistor performance [0036, 0059].
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Guha (US 2020/0091348) in view of THEN (US 2017/0263708) as applied to claim 1 above, and further in view of Alptekin et al. (US 2012/0273798; hereinafter ‘Alptekin’).
Regarding claim 6, Guha in view of THEN the transistor of claim 1, but does not teach the transistor wherein the first extension and the second extension have semicircular cross-sections.
Alptekin teaches a transistor (100, FIG. 1A, [0026]), wherein the first extension and the second extension (the left 104 and the right 104) have semicircular cross-sections (shown in FIG. 1A).
As taught by Alptekin, one of ordinary skill in the art would utilize and modify the above teaching into Guha in view of THEN to obtain and achieve the transistor wherein the first extension and the second extension have semicircular cross-sections as claimed, because a semicircular structure maximizes the contact area between the extension and the contact layer, thereby reducing contact resistance and improving current flow uniformity [0007, 0035].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Alptekin in combination with Guha in view of THEN due to the above reason.
Regarding claim 7, Guha in view of THEN and Alptekin teaches the transistor of claim 6, wherein portions of the first extension and the second extension contact the first spacer or the second spacer (Guha: portions of L170 and R170 contact L162 or R162, FIG. 1B).
Claims 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Guha (US 2020/0091348) in view of THEN (US 2017/0263708) as applied to claim 1, and further in view of Cheng et al. (US 202080266060; hereinafter Cheng).
Regarding claim 8, Guha in view of THEN teaches the transistor of claim 1, but does not teach the transistor, wherein a height of the first extension and the second extension is between approximately 5 nm and approximately 10 nm.
Cheng teaches a transistor (10, FIG. 1A, [0035]), wherein a height of the first extension and the second extension is between approximately 5 nm and approximately 10 nm (140 has a height of 10 to 17 nm in the gate direction, considering that 112, 114, and 116 have a thickness of 6 to 9 nm, and the thickness of 140 is 2 to 4 nm, [0048, 0063]).
As taught by Cheng, one of ordinary skill in the art would utilize and modify the above teaching into Guha in view of THEN to obtain and achieve the transistor wherein a height of the first extension and the second extension is between approximately 5 nm and approximately 10 nm as claimed, because applicant has not disclosed that, in view of the applied prior art, the height differences are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. For that matter, applicant has not disclosed that the height of the first extension and the second extension differences are for any purpose or produce any result. Moreover, it appears prima facie that the process would possess utility using another height differences. Indeed, it has been held that mere limitation(s) is prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Cheng in combination with Guha in view of THEN due to the above reason.
Regarding claim 10, Guha in view of THEN teaches the transistor of claim 9, but does not teach the transistor, wherein the width of the first extension and the second extension is approximately 5 nm or less.
Cheng teaches a transistor (10, FIG. 1A, [0035]), wherein a width of the first extension and the second extension is approximately 5 nm or less (140 has a width of 2 to 4 nm, where the width is defined based on the lateral direction extending from the channel, [0063]).
As taught by Cheng, one of ordinary skill in the art would utilize and modify the above teaching into Guha in view of THEN to obtain and achieve the transistor wherein the width of the first extension and the second extension is approximately 5 nm or less as claimed, because applicant has not disclosed that, in view of the applied prior art, the width differences are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. For that matter, applicant has not disclosed that the width of the first extension and the second extension differences are for any purpose or produce any result. Moreover, it appears prima facie that the process would possess utility using another width differences. Indeed, it has been held that mere limitation(s) is prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Cheng in combination with Guha in view of THEN due to the above reason.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Guha (US 2020/0091348) in view of THEN (US 2017/0263708) and Naylor (US 2022/0102499) as applied to claim 11 above, and further in view of Fan et al. (US 2021/0082707; hereinafter ‘Fan’).
Regarding claim 12, Guha in view of THEN and Naylor teaches the transistor of claim 11, but does not teach the transistor, wherein the surface treatment layer comprises nitrogen.
Fan teaches a transistor (FIG. 11, [0032]), wherein the surface treatment layer (90, [0077]) comprises nitrogen (90 is formed by a nitrogen treatment).
As taught by Fan, one of ordinary skill in the art would utilize and modify the above teaching into Guha in view of THEN and Naylor to obtain and achieve the transistor wherein the surface treatment layer comprises nitrogen as claimed, because forming a nitrogen-containing layer around the channel region induces the formation of Si-N bonds, which reduce the Schottky barrier height between the semiconductor and the metal contact [0081], and also lowers the oxygen content at the interface, thereby improving the contact resistance [0123].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Fan in combination with Guha in view of THEN and Naylor due to the above reason.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Guha (US 2020/0091348) in view of THEN (US 2017/0263708) as applied to claim 1 above, and further in view of Moriwaki et al. (US 2016/0027778; hereinafter ‘Moriwaki’).
Regarding claim 13, Guha in view of THEN teaches the transistor of claim 1, but does not teach the transistor wherein the first spacer and the second spacer comprise aluminum and oxygen.
Moriwaki teaches a transistor (FIG. 19, [0012]), wherein the first spacer and the second spacer comprise aluminum and oxygen (the left SD sidewall and the right SD sidewall comprises aluminum oxide).
As taught by Moriwaki, one of ordinary skill in the art would utilize and modify the above teaching into Guha in view of THEN to obtain and achieve the transistor wherein the first spacer and the second spacer comprise aluminum and oxygen as claimed, because selecting aluminum oxide as the sidewall spacer material suppresses the induction of negative fixed charges and prevents an increase in the equivalent oxide thickness of the gate insulating film thereby avoiding a threshold voltage shift [0009]. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Moriwaki in combination with Guha in view of THEN due to the above reason.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Guha (US 2020/0091348) in view of THEN (US 2017/0263708) as applied to claim 1 above, and further in view of Nourbakhsh et al. (Nano Lett. 2016, 16, 12, 7798–7806; hereinafter ‘Nourbakhsh’).
Regarding claim 14, Guha in view of THEN teaches the transistor of claim 1, but does not teach the transistor wherein a channel length of the channel is approximately 10 nm or less.
Nourbakhsh teaches a transistor (ABSTRACT), wherein a channel length of the channel is approximately 10 nm or less (channel length is sub 10 nm).
As taught by Nourbakhsh, one of ordinary skill in the art would utilize and modify the above teaching into Guha in view of THEN to obtain and achieve the transistor, wherein a channel length of the channel is approximately 10 nm or less as claimed, because shorter channels reduce the carrier transit time and channel resistance, enable stronger electric fields at lower voltages, and enable higher device density (p.7798).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Nourbakhsh in combination with Guha in view of THEN due to the above reason.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Guha (US 2020/0091348) in view of THEN (US 2017/0263708) as applied to claim 15 above, and further in view of Naylor (US 2022/0102499) and Fan et al. (US 2021/0082707; hereinafter ‘Fan’).
Regarding claim 18, Guha in view of THEN teaches the transistor device of claim 15, but does not teach the transistor device wherein the extensions have a surface treatment layer comprising nitrogen.
Naylor teaches a transistor device (100, FIG. 11, [0049]), wherein the extensions (128, [0047]) have a surface treatment layer (a surface treatment layer).
As taught by Naylor, one of ordinary skill in the art would utilize and modify the above teaching into Guha in view of THEN to obtain and achieve the transistor device wherein the extensions have a surface treatment layer as claimed, because the surface treatment on the extensions is performed to improve the contact and interface properties, thereby reducing contact resistance and enhancing carrier injection.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Naylor in combination with Guha in view of THEN due to the above reason.
Guha in view of THEN and Naylor does not teach the transistor device, wherein the surface treatment layer comprises nitrogen.
Fan teaches a transistor device (FIG. 11, [0032]), wherein the surface treatment layer (90, [0077]) comprises nitrogen (90 is formed by a nitrogen treatment).
As taught by Fan, one of ordinary skill in the art would utilize and modify the above teaching into Guha in view of THEN and Naylor to obtain and achieve the transistor device, wherein the surface treatment layer comprises nitrogen as claimed, because forming a nitrogen-containing layer around the channel region induces the formation of Si-N bonds, which reduce the Schottky barrier height between the semiconductor and the metal contact [0081], and also lowers the oxygen content at the interface, thereby improving the contact resistance [0123].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Fan in combination with Guha in view of THEN and Naylor due to the above reason.
Response to Arguments
Applicant's arguments with respect to claims have been considered but are moot in view of the new grounds of rejection based on newly applied prior art. The claims were not amended in a manner that overcomes the newly applied rejections. Response to arguments on newly added limitations are responded to in the above rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure in that Jambunathan et al. (US 2020/0273998) and Majhi et al. (US 2020/0105940) teach semiconductor structure including conductive layers adjacent to a gate stack.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIYOUNG OH whose telephone number is (703)756-5687. The examiner can normally be reached Monday-Friday, 9AM-5PM EST.
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 9/3/26
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