DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Rejections under 35 U.S.C. § 103, filed 11/19/2025, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as detailed below.
Examiner Suggestion
Claim 5 contains allowable subject matter and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 13 contains allowable subject matter and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-3 & 7 are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al. (US 2017/0330825) [Hereinafter Chou], Zong et al. (CN111491456A) [Hereinafter Zong], & Ramanuja et al. (US 2006/0060845) [Hereinafter Ramanuja].
Regarding claim 1, Chou teaches A package substrate comprising:
a substrate core [fig. 3G, insulative layer 111, para 22],
the package substrate to support a semiconductor die [para 15, “One or more semiconductor devices can be attached to the package substrate.”];
a build-up layer [annotated fig. 3G], the build-up layer including:
a dielectric layer [fig. 3G, insulative layer 114, para 22], and
a conductive layer [fig. 3G, patterned conductive layer 21, para 33] between the substrate core (fig. 3G, 111) and the dielectric layer (fig. 3G, 114),
the conductive layer (fig. 3G, 21) including first [fig. 3G, conductive trace 142, para 33] and second traces [fig. 3G, conductive trace 143, para 33] separated by a space therebetween [fig. 3G]; and
a film [fig. 3G, insulative layer 113, para 22] between the dielectric layer (fig. 3G, 114) and the first (fig. 3G, 142) and second traces (fig. 3G, 143) of the conductive layer (fig. 3G, 21),
the film (fig. 3G, 113) extending across the space between the first (fig. 3G, 142) and second (fig. 3G, 143) traces of the conductive layer (fig. 3G, 21) to separate the dielectric layer (fig. 3G, 114) from the substrate core (fig. 3G, 111).
Chou fails to explicitly disclose the conductive layer having a surface roughness of less than 1 micrometer (µm).
However, Zong teaches the conductive layer [fig. 4, conductive layer 102] having a surface roughness of less than 1 micrometer (µm) [“the surface roughness Ra of the first conductive layer is less than 100nm”.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the conductive layer to have a surface roughness of less than 1 micrometer to improve adhesion between the conductive material and insulative material. Furthermore Zong teaches an range which lies within the claimed invention range, therefore a prima facie case of obviousness exists.
Chou/Zong fails to explicitly disclose the film including silicon and nitrogen and being substantially free of hydrogen.
While Chou notes the film (fig. 3G, 113, para 22) may include a flowable dielectric material in a hardened or semi-hardened state, such as, for example, a liquid crystal polymer, prepreg, an Ajinomoto build-up film (ABF), a resin, an epoxy compound, or the like.
However, Ramanuja teaches a film [fig. 2C, dielectric layer 242, para 24] including silicon and nitrogen and being substantially free of hydrogen [para 24, silicon nitride].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the film layer to comprise silicon-nitride to protect and seal against contamination, thereby improving reliability of the package substrate.
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ANNOTATED FIG. 3G
Regarding claim 2, Chou/Zong/Ramanuja teaches The package substrate of claim 1,
wherein the surface roughness is approximately between 0.01 micrometers (µm) and 0.5 micrometers (µm).
Zong specifically teaches the conductive layer [fig. 4, conductive layer 102] having a surface roughness of less than 1 micrometer (µm) [“the surface roughness Ra of the first conductive layer is less than 100nm”.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the conductive layer to have a surface roughness of less than 100nm micrometer to improve adhesion between the conductive material and insulative material. Furthermore Zong teaches an range which overlaps the claimed invention (between 0.01 micrometers (µm) and 0.5 micrometers (µm). In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists (MPEP 2144.05).
Regarding claim 3, Chou/Zong/Ramanuja teaches The package substrate of claim 1,
wherein the film includes an adhesion promotor film [Ramanuja, fig. 2C, dielectric layer 242, para 24; “a dielectric layer 242 (as shown in FIG. 2C) that may be silicon-oxide, silicon-nitride, silicon carbide, polymer, spin on glass, and/or resins; wherein spin on glass & resin is an adhesive promoter].
Regarding claim 7, Chou/Zong/Ramanuja teaches The package substrate of claim 1,
wherein the substrate core includes an organic material [Chou, fig. 3G, insulative layer 11asse1, para 22], includes an organic material and the film includes an inorganic material [Chou, para 22, “In other embodiments, one or more of the insulative layers 111 , 112 , 113 , 114 , 115 , 116 and 117 include multiple resin layers; for example, a first sub-layer formed of a resin and a second sub-layer formed of an enhanced resin (such as a resin enhanced by glass fibers or Kevlar fibers).”]. and the film includes an inorganic material.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chou, Zong, & Ramanuja as applied to claims 1-3 & 7 and further in view of Rosch et al. (US 2019/0393143) [Herein Rosch].
Regarding claim 4, Chou/Zong/Ramanuja teaches The package substrate of claim 1.
Chou/Zong/Ramanuja fails to explicitly disclose a via in the dielectric layer,
a portion of the conductive layer exposed by the via,
at least one of a via wall or the portion of the conductive layer exposed by the via substantially free of fluorine.
However, Rosch teaches a via [fig. 1A, via 141, para 23] in the dielectric layer [fig. 1A, dielectric layer 110, para 23],
a portion of the conductive layer [fig. 1A, pad 131a, para 25] exposed by the via (fig. 1A, 141),
at least one of a via wall or the portion of the conductive layer exposed by the via substantially free of fluorine [para 27 discloses the conductive layer 131 to be comprised of Copper, which is substantially free of fluorine].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the package substrate to comprise vias in the dielectric layer to provide routing/coupling between contacts/layers. Furthermore for the vias/conductive layers to be free of fluorine improving environmental sustainability while also enabling better electrical performance through lower loss and noise.
Claims 8, 11-12, & 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chou, Ramanuja, & Rosch.
Regarding claim 8, Chou teaches An integrated circuit package comprising:
an integrated circuit chip [Fig. 7, semiconductor device 71, para 51; wherein fig. 7 illustrates a cross sectional view of a flip chip semiconductor package structure]:
a package substrate [fig. 7, package substrate 71, para 51] to carry to the integrated circuit chip (fig. 7, 71), the package substrate including:
Chou fails to explicitly disclose in fig. 7 a core,
the core including an organic material;
a dielectric layer separating first and second conductive layers, the first conductive layer between the core and the dielectric layer;
a film between the dielectric layer and the first conductive layer,
However Chou teaches in fig. 3G a core [fig. 3G, insulative layer 111, para 22],,
the core including an organic material [para 22, “one or more of the insulative layers 111 , 112 , 113 , 114 , 115 , 116 and 117 include multiple resin layers; for example, a first sub-layer formed of a resin and a second sub-layer formed of an enhanced resin (such as a resin enhanced by glass fibers or Kevlar fibers).”; wherein resin is organic material);
a dielectric layer [fig. 3G, insulative layer 114, para 22], separating first [fig. 3G, patterned conductive layer 21, para 33] and second conductive layers[fig. 3G, patterned conductive layer 22, para 26],
the first conductive layer (fig. 3G, 21) between the core (fig. 3G, 111) and the dielectric layer (fig. 3G, 114);
a film [fig. 3G, insulative layer 113, para 22] between the dielectric layer (fig. 3G, 114) and the first conductive layer (fig. 3G, 21).
Chou fails to explicitly disclose the film including silicon and nitrogen.
However, Ramanuja teaches a film [fig. 2C, dielectric layer 242, para 24] including silicon and nitrogen.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the film layer to comprise silicon-nitride to protect and seal against contamination, thereby improving reliability of the package substrate.
Chou/Ramanuja fails to explicitly disclose a via provided in the dielectric layer,
the via extending from the second conductive layer to the first conductive layer,
at least one of a surface of the dielectric layer, a via wall defining the via, or the first conductive layer exposed inside the via substantially free of fluorine.
However, Rosch teaches a via [fig. 1A, via 141, para 23] in the dielectric layer [fig. 1A, dielectric layer 110, para 23],
the via (fig. 1A, 141) extending from the second conductive layer [fig. 1A, conductive layer 130, para 28] to the first conductive layer [fig. 1A, conductive layer 131, para 28],
at least one of a surface of the dielectric layer, a via wall defining the via, or the first conductive layer inside the via substantially free of fluorine [para 27 discloses the conductive layer 130 & 131 to be comprised of Copper, which is substantially free of fluorine].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the package substrate to comprise vias in the dielectric layer to provide routing/coupling between contacts/layers. Furthermore for the vias/conductive layers to be free of fluorine improving environmental sustainability while also enabling better electrical performance through lower loss and noise.
Regarding claim 11, Chou/Ramanuja/Rosch teaches The package assembly of claim 8,
wherein the film is an adhesion promotor film and includes silicon nitride (SiNx) [Ramanuja, fig. 2C, dielectric layer 242, para 24; “a dielectric layer 242 (as shown in FIG. 2C) that may be silicon-oxide, silicon-nitride, silicon carbide, polymer, spin on glass, and/or resins; wherein resin is an adhesive promoter].
Regarding claim 12, Chou/Ramanuja/Rosch teaches The package assembly of claim 8,
wherein the film is substantially free of hydrogen.
Ramanuja specifically teaches a film [fig. 2C, dielectric layer 242, para 24] including silicon and nitrogen and being substantially free of hydrogen [para 24, silicon nitride].
Regarding claim 15, Chou/Ramanuja/Rosch teaches The package assembly of claim 8,
wherein the substrate [Chou, fig. 3G, insulative layer 111, para 22], includes an organic material and the film includes an inorganic material [Chou, para 22, “In other embodiments, one or more of the insulative layers 111 , 112 , 113 , 114 , 115 , 116 and 117 include multiple resin layers; for example, a first sub-layer formed of a resin and a second sub-layer formed of an enhanced resin (such as a resin enhanced by glass fibers or Kevlar fibers).”].
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chou, Ramanuja, & Rosch as applied to claims 8, 11-12, & 15 and further in view of Lin (US 2010/0301450).
Regarding claim 9, Chou/Ramanuja/Rosch teaches The package assembly of claim 8.
Chou/Ramanuja/Rosch fails to explicitly disclose wherein the conductive layer has a smooth, non-roughened surface finish.
However, Lin teaches wherein the conductive layer [fig. 3D, smooth conductive layer 124, para 38] has a smooth, non-roughened surface finish.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the conductive layer to have a smooth, non-roughened surface finish to reduce particles and hill-locks thereby improving performance and reliability.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chou, Ramanuja, & Rosch as applied to claims 8, 11-12, & 15 and further in view of Zong.
Regarding claim 10, Chou/Ramanuja/Rosch teaches The package assembly of claim 8.
Chou/Ramanuja/Rosch fails to explicitly disclose wherein the conductive layer has a surface roughness of less than 1 micrometers.
wherein the conductive layer has a surface roughness of less than 1 micrometers (µm).
However, Zong teaches the conductive layer [fig. 4, conductive layer 102] having a surface roughness of less than 1 micrometer (µm) [“the surface roughness Ra of the first conductive layer is less than 100nm”.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the conductive layer to have a surface roughness of less than 1 micrometer to improve adhesion between the conductive material and insulative material. Furthermore Zong teaches an range which overlaps the claimed invention. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists (MPEP 2144.05).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Chou, Lin, & Camacho et al. (US 2012/0326337).
Regarding claim 16, Chou teaches A method for manufacturing a package assembly, the method comprising:
providing a conductive layer [fig. 3G, conductive layer 21, para 18] on a core [fig. 3G, insulative layer 111/ reference layer 121/insulative layer 112, para 19/22] of a package substrate [fig. 3G, package substrate 3g, para 33],
the conductive layer (fig. 3G, 21) including different traces [fig. 3G, trace 142/143, para 33];
depositing, a adhesion promotor layer [fig. 3G, insulative layer 113, para 22] to the conductive layer (fig. 3G, 21) and exposed surfaces of the core (fig. 3G, 111/121/112) between the different traces (fig. 3G, 142, 143),
and
applying a dielectric layer [fig. 3G, insulative layer 114, para 22] on the promotor layer (fig. 3G, 113).
Chou fails to explicitly disclose the conductive layer having a smooth, non-roughed surface finish.
However, Lin teaches wherein the conductive layer [fig. 3D, smooth conductive layer 124, para 38] has a smooth, non-roughened surface finish.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the conductive layer to have a smooth, non-roughened surface finish to reduce particles and hill-locks thereby improving performance and reliability.
Chou/Lin fails to explicitly disclose depositing, via physical vapor deposition, a non-roughening adhesion promotor layer
the adhesion promotor layer being substantially free of hydrogen.
Camacho teaches depositing, via physical vapor deposition [para 44-45], a non-roughening adhesion promotor layer [fig. 5a, adhesive layer 134, para 44-45]
the adhesion promotor layer being substantially free of hydrogen [para 45; wherein SiO2, Si3N4, SiON, Ta2O5, Al2O3 are substantially hydrogen-free materials].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the adhesion promoter layer to be deposited via physical vapor deposition and smooth to aid with later formation of conductive layers by increasing bonding and ensuring a uniform interface which is crucial for reliability and performance.
Allowable Subject Matter
Claims 5-6, 13-14, & 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5, Chou/Zong/Ramanuja/Rosch teaches The package substrate of claim 4.
The prior art of record singularly and/or in combination fails to explicitly disclose a seed layer provided on the dielectric layer, the via wall, and the portion of the conductive layer exposed by the via.
Thereby claim 5 contains allowable subject matter and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 6 contains allowable subject matter at least based upon dependency on claim 5.
Regarding claim 13, Chou/Ramanuja/Rosch teaches The package assembly of claim 12.
The prior art of record fails to explicitly disclose including a seed layer on the dielectric layer, the via wall, and a portion of the first conductive layer exposed by the via.
Thereby claim 13 contains allowable subject matter and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 14 contains allowable subject matter at least based upon dependency on claim 13.
Regarding claim 17, Chou/Lin/Camacho teaches The method of claim 16.
The prior art singularly and/or in combination fails to explicitly disclose including providing a via between a first side of the dielectric layer and a second side of the dielectric layer opposite the first side to expose a portion of the non-roughening adhesion promotor layer in the via.
Thereby claim 17 contains allowable subject matter and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 18-20 contain allowable subject matter at least based upon dependency on claim 17.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FELIX B ANDREWS whose telephone number is (703)756-1074. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FELIX B ANDREWS/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812