Prosecution Insights
Last updated: April 20, 2026
Application No. 17/856,185

ALIGNMENT VIA-PAD AND VIA-PLANE STRUCTURES

Non-Final OA §102
Filed
Jul 01, 2022
Examiner
LIU, BENJAMIN T
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
2 (Non-Final)
74%
Grant Probability
Favorable
2-3
OA Rounds
3y 1m
To Grant
87%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allow Rate
511 granted / 687 resolved
+6.4% vs TC avg
Moderate +13% lift
Without
With
+12.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
48 currently pending
Career history
735
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
56.9%
+16.9% vs TC avg
§102
32.8%
-7.2% vs TC avg
§112
9.2%
-30.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 687 resolved cases

Office Action

§102
DETAILED ACTION Office action sent 8/12/2025 withdrawn and new rejection recited below. Response to Arguments Applicant’s arguments with respect to claims 1, 7, 8, 10, 12-13, 16, and 19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-2, 4-6, 9-10, 14-16, 18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Alcoe (US 2004/0238970). With regard to claim 1, figs. 3-3A of Alcoe discloses an integrated circuit (IC) package support 11”, comprising: a conductive structure 15A having an aperture 16; and a conductive via 19” at least partially nested in the aperture 16 in the conductive structure 15A; and a conductive bridge (“portion of the layer 15A coupled to via 19” ”, par [0037]) spanning between and in contact with the conductive structure 15A and the conductive via 19”, wherein the conductive bridge (“portion of the layer 15A coupled to via 19” ”, par [0037]) connects to the conductive structure 15a at an angle that is greater than 90 degrees (180 degrees). With regard to claim 2, figs. 3-3A of Alcoe discloses that the conductive structure 15A is a conductive pad or a conductive plane 15A. With regard to claim 4, figs. 3-3A of Alcoe discloses that the conductive structure 15A, the conductive via 19”, and the conductive bridge (“portion of the layer 15A coupled to via 19””, par [0037]) are in a layer of dielectric material (“organic laminate”, par [0032]). With regard to claim 5, figs. 3-3A of Alcoe discloses that the dielectric material (“organic laminate”, par [0032]) includes an organic material (“organic laminate”, par [0032]). With regard to claim 6, figs. 3-3A of Alcoe discloses that the conductive structure 15A and the conductive via 19” include copper (“copper”, par [0032]). With regard to claim 9, figs. 3-3A of Alcoe discloses a cross-section of the conductive via 19” is circular (conductive via 19” is circle shaped in fig. 3), rectangular, triangular, oval, elliptical, or oblong. With regard to claim 10, figs. 3-3A of Alcoe discloses an electronic assembly, comprising: an integrated circuit (IC) package support 11”, including a conductive via 19” at least partially nested in an aperture 16 in a conductive plane 15A; and a conductive bridge (“portion of the layer 15A coupled to via 19””, par [0037]) spanning between and in contact with the conductive plane 15A and the conductive via 19”, wherein the conductive bridge (“portion of the layer 15A coupled to via 19” ”, par [0037]) connects to the conductive structure 15a at an angle that is greater than 90 degrees (180 degrees). With regard to claims 14 and 20, figs. 3-3A and 9 of Alcoe discloses that the IC package support 11’ further includes conductive contacts 21’ and the electronic assembly 51 further includes one or more dies (“semiconductor chip 65”, par [0046]) coupled to the conductive contacts (“corresponding conductive elements on a receiving substrate”, par [0046]). With regard to claim 15, figs. 3-3A and 9 of Alcoe discloses that the IC package support 11’ is included in an IC package 11’, the electronic assembly 51 further includes a circuit board 63, and the IC package 11’ is coupled to the circuit board 63. With regard to claim 16, figs. 3-3A of Alcoe discloses an electronic assembly, comprising: an integrated circuit (IC) package support 11”, including a conductive via 16” at least partially nested in an aperture 16 in a conductive pad 15A, wherein the conductive via 19” is separated from the conductive pad 15A by a gap (separation in space between 19” and 16); and a conductive bridge (“portion of the layer 15A coupled to via 19””, par [0037]) spanning the gap (separation in space between 19” and 16) and connecting the conductive pad 15A and the conductive via 19”, wherein the conductive bridge (“portion of the layer 15A coupled to via 19” ”, par [0037]) connects to the conductive structure 15a at an angle that is greater than 90 degrees (180 degrees).. With regard to claim 18, figs. 3-3A of Alcoe discloses that the conductive pad 15A, the conductive via 19”, and the conductive bridge (“portion of the layer 15A coupled to via 19””, par [0037]) are in a layer of dielectric material (“organic laminate”, par [0032]). Claims 7-8, 12-13, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Topacio et al. (US 2015/0279794) (“Topacio”). With regard to claim 7, figs. 10-11 of Topacio discloses an integrated circuit (IC) package support 60, comprising: a conductive structure 75 having an aperture (185, 190, 195, 180); and a conductive via 100 at least partially nested in the aperture (185, 190, 195, 180) in the conductive structure 175; and a conductive bridge 115 spanning between and in contact with the conductive structure 75 and the conductive via 100, wherein the conductive bridge 115 is one of a plurality of conductive bridges (120, 115, 110, 105) spanning between and in contact with the conductive structure 75 and the conductive via 100. With regard to claim 8, figs. 1 and 10-11 of Topacio discloses an integrated circuit (IC) package support 60, comprising: a conductive structure 75 having an aperture (185, 190, 195, 180); and a conductive via 100 at least partially nested in the aperture (185, 190, 195, 180) in the conductive structure 75; and a conductive bridge 115 spanning between and in contact with the conductive structure 75 and the conductive via 100, wherein the aperture (185, 190, 195, 180) in the conductive structure 75 is a first aperture ((185, 190, 195, 180) for 35), the conductive via 100 is a first conductive via (100 for 35), and the conductive bridge 115 is a first conductive bridge (115 of 35), and the IC package support further comprising: a second conductive via (100 for 40) at least partially nested in a second aperture ((185, 190, 195, 180) for 40) in the conductive structure 75; and a second conductive bridge (115 of 40) spanning between and in contact with the conductive structure 75 and the second conductive via (100 of 40). With regard to claim 12, figs. 10-11 of Topacio discloses an electronic assembly 15 comprising: an integrated circuit (IC) package support 60, comprising: a conductive structure 75 having an aperture (185, 190, 195, 180); and a conductive via 100 at least partially nested in the aperture (185, 190, 195, 180) in the conductive structure 175; and a conductive bridge 115 spanning between and in contact with the conductive structure 75 and the conductive via 100, wherein the conductive bridge 115 is one of a plurality of conductive bridges (120, 115, 110, 105) spanning between and in contact with the conductive structure 75 and the conductive via 100. With regard to claim 13, figs. 1 and 10-11 of Topacio discloses a an electronic assembly 15, comprising: an integrated circuit (IC) package support 60, comprising: a conductive structure 75 having an aperture (185, 190, 195, 180); and a conductive via 100 at least partially nested in the aperture (185, 190, 195, 180) in the conductive structure 75; and a conductive bridge 115 spanning between and in contact with the conductive structure 75 and the conductive via 100, wherein the aperture (185, 190, 195, 180) in the conductive structure 75 is a first aperture ((185, 190, 195, 180) for 35), the conductive via 100 is a first conductive via (100 for 35), and the conductive bridge 115 is a first conductive bridge (115 of 35), and the IC package support further comprising: a second conductive via (100 for 40) at least partially nested in a second aperture ((185, 190, 195, 180) for 40) in the conductive structure 75; and a second conductive bridge (115 of 40) spanning between and in contact with the conductive structure 75 and the second conductive via (100 of 40). With regard to claim 19, figs. 1 and 10-11 of Topacio discloses an electronic assembly 15, comprising: an integrated circuit (IC) package support 60, including a conductive via 100 at least partially nested in an aperture (185, 190, 195, 180) in a conductive pad 75, wherein the conductive via 100 is separated from the conductive pad 75 by a gap (185, 190, 195, 180); and a conductive bridge 115 spanning the gap (185, 190, 195, 180) and connecting the conductive pad 75 and the conductive via 100, wherein the conductive bridge 115 is one of a plurality of conductive bridges (115, 120, 105, 110) spanning the gap (185, 190, 195, 180) and connecting the conductive pad 75 and the conductive via 100. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN T LIU whose telephone number is (571)272-6009. The examiner can normally be reached Monday-Friday 11:00am-7:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J Green can be reached at 571 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BENJAMIN TZU-HUNG LIU/ Primary Examiner, Art Unit 2893
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Prosecution Timeline

Jul 01, 2022
Application Filed
Feb 24, 2023
Response after Non-Final Action
Aug 09, 2025
Non-Final Rejection — §102
Oct 28, 2025
Response Filed
Feb 14, 2026
Non-Final Rejection — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
74%
Grant Probability
87%
With Interview (+12.6%)
3y 1m
Median Time to Grant
Moderate
PTA Risk
Based on 687 resolved cases by this examiner. Grant probability derived from career allow rate.

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