Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Attorney Docket Number: AE1622-US
Filling Date: AE1622-US
Inventor: Haratipour et al
Examiner: Bilkis Jahan
DETAILED ACTION
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over More et al (US 2018/0174913 A1) in view of Glass et al (US 2013/0248999 A1).
Regarding claim 1, More discloses a semiconductor die (Figs. 16 and 21), comprising: a substrate 50 (Para. 22); a channel layer 56 (Para. 19) on the substrate 50; a gate structure 94 (Para. 53) over the channel layer 56; a source region 82 (left, Para. 30) and a drain region 82 (right), the source region 82 (left) coupled to the channel layer 56 on a first side of the gate structure 94 and the drain region 82 (right) coupled to the channel layer 56 on a second side of the gate structure 94, the source region 82 (left) and the drain region 82 (right) comprising silicon and germanium (Para. 30); a first cap layer 84 (Para. 33, 30, B-doped SiGe, left) on at least one of the source region 82 (left) or the drain region, the first cap layer 84; and a second cap layer (liner, Para. 45) on the first cap layer 84 and above at least one of the source region 82 or the drain region 82, the second cap layer comprising a refractory metal (Para. 45, tantalum).
More does not explicitly disclose the first cap layer comprising germanium and boron.
However, Glass discloses the cap layer comprising germanium and boron 317, 319 (Fig. 3, Para. 42). Glass teaches the above modification is used to Improve contact resistance (Para. 42). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to substitute More cap layer material with Glass cap layer material as suggested above to Improve contact resistance (Para. 42).
Regarding claim 2, More discloses the semiconductor die of Claim 1, wherein the refractory metal comprises molybdenum, niobium, rhenium, tantalum (Para. 45, liner), or tungsten.
Regarding claim 3, More discloses the semiconductor die of Claim 1, wherein: the first cap layer 84 is on the source region 82 (left) and the drain region 82 (right), wherein the first cap layer includes a first source cap 84 (Paras. 30, 33, left) and a first drain cap 84 (right), wherein the first source cap 84 (left) is on the source region 82 (left) and the first drain cap 84 (right) is on the drain region 82 (right); and the second cap layer (liner, Para. 45) is above the source region 82 and the drain region 82, wherein the second cap layer includes a second source cap (liner, Para. 45, left) and a second drain cap (liner, Para. 45, right), wherein the second source cap (liner, Para. 45) is on the first source cap 84 (left) and the second drain cap (liner, Para. 45) is on the first drain cap 84 (right).
Regarding claim 4, More discloses the semiconductor die of Claim 3, further comprising: a first conductive contact 120 (Para. 52) on the second source cap (liner, Para. 45); and a second conductive contact 120 (right) on the second drain cap (liner, Para. 45).
Regarding claim 5, More discloses the semiconductor die of Claim 1, wherein the gate structure includes: a gate electrode 94 (Para. 53); a first dielectric sidewall spacer 86 (Fig. 10B, Para. 27) on a first side of the gate electrode 94; and a second dielectric sidewall spacer 86 on a second side of the gate electrode 94.
Regarding claim 6, More discloses the semiconductor die of Claim 1, wherein the source region 82 and the drain region 82 are p-type doped with boron (Para. 30) or gallium.
Regarding claim 7, More discloses the semiconductor die of Claim 1, wherein the channel layer 50, 56 comprises silicon (Para. 14).
Regarding claim 8, More discloses the semiconductor die of Claim 1, further comprising a transistor (Fig. 21B), wherein the transistor includes the channel layer 56, the gate structure 94, the source region 82, the drain region 82, the first cap layer 84, and the second cap layer 84.
Regarding claim 9, More discloses the semiconductor die of Claim 8, wherein the transistor is a P-type transistor (Para. 30).
Claim(s) 10-19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over More et al (US 2018/0174913 A1) in view of Monchiero et al (US 2010/0194470 A1) and further in view of Glass et al (US 2013/0248999 A1).
Regarding claim 10, More discloses an integrated circuit (Figs. 16 and 21), comprising: the integrated circuit die (Figs. 16 and 21) includes one or more transistors, wherein at least one transistor (Figs. 16B, 21B) includes: a channel layer 56 (Para. 19); a gate electrode 94 (Para. 53) over the channel layer 56; a source region 82 (Para. 30, left) and a drain region 82 (right), the source region 82 coupled to the channel layer 56 on a first side of the gate electrode 94 and the drain region 82 (right) coupled to the channel layer 56 on a second side of the gate electrode 94, the source region 82 and the drain region 82 comprising silicon and germanium (Para. 30); a first source cap 84 (Paras. 30, 33, left) and a first drain cap 84 (right), wherein the first source cap 84 (left) is on the source region 82 and the first drain cap 84 (right) is on the drain region 82, a second source cap (liner, Para. 45) and a second drain cap (liner, Para. 45), wherein the second source cap (liner is on 84) is on the first source cap 84 (left) and the second drain cap (liner is on 84) is on the first drain cap 84 (right), wherein the second source cap and the second drain cap comprise a refractory metal (liner, Para. 45).
More does not explicitly disclose a package substrate; and an integrated circuit die coupled to the package substrate.
However, Monchiero discloses a package substrate 415 (Fig. 4, Para. 41) ; and an integrated circuit die 405 (Para. 38) coupled to the package substrate 415. Monchiero teaches the above modification is used to make package and reduce current leak of the device (Fig. 4, Para. 44). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to combine More structure with Monchiero Package substrate as suggested above to make package and reduce current leak of the device (Fig. 4, Para. 44).
More does not explicitly disclose the first source cap and the first drain cap comprise germanium and boron.
However, Glass discloses the first source cap and the first drain cap comprise germanium and boron 317, 319 (Fig. 3, Para. 42). Glass teaches the above modification is used to Improve contact resistance (Para. 42). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to substitute More cap layer material with Glass cap layer material as suggested above to Improve contact resistance (Para. 42).
Regarding claim 11, More discloses the integrated circuit of Claim 10, wherein the refractory metal comprises molybdenum, niobium, rhenium, tantalum, or tungsten (liner, Para. 45).
Regarding claim 12, More discloses the integrated circuit of Claim 10, further comprising: a first conductive contact 120 on the second source cap (liner, Para. 45); and a second conductive contact (liner, Para. 45) on the second drain cap (liner, Para. 45).
Regarding claim 13, More discloses the integrated circuit of Claim 10, wherein the source region 82 and the drain region 82 are p-type doped with boron (Para. 30) or gallium.
Regarding claim 14, More discloses the integrated circuit of Claim 10, wherein the channel layer 56, 50 comprises silicon (Para. 14).
Regarding claim 15, More discloses the integrated circuit of Claim 10, wherein the at least one transistor is a p-channel metal–oxide–semiconductor transistor (Para. 15).
Regarding claim 16, More discloses an electronic device (Figs. 16 and 21), comprising: the integrated circuit includes one or more transistors, wherein at least one transistor (Figs. 16B, 21B) includes: a channel layer 56 (Para. 19); a gate electrode 94 (Para. 53) over the channel layer 56; a source region 82 (Para. 30, left) and a drain region 82 (Para. 30, right), the source region 82 coupled to the channel layer 56 on a first side of the gate electrode 94 and the drain region 82 coupled to the channel layer 56 on a second side of the gate electrode 94, the source region 82 and the drain region 82 comprising silicon and germanium (Para. 30); a first source cap 84 (Paras. 30, 33, left) and a first drain cap 84 (Paras. 30, 33, right), wherein the first source cap 84 is on the source region 82 and the first drain cap 84 is on the drain region 82, a second source cap (liner, Para. 45, left) and a second drain cap (liner, Para. 45, right), wherein the second source cap (liner, Para. 45, left) is on the first source cap 84 (left) and the second drain cap (liner, Para. 45, right) is on the first drain cap 84 (right), wherein the second source cap and the second drain cap comprise a refractory metal ((liner, Para. 45).
More does not explicitly disclose a board 415 (Fig. 4, Paras. 41, 19, 25); and an integrated circuit 405 (Para. 38) coupled to the board 415.
Monchiero teaches the above modification is used to make package and reduce current leak of the device (Fig. 4, Para. 44). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to combine More structure with Monchiero board as suggested above to make package and reduce current leak of the device (Fig. 4, Para. 44).
More does not explicitly disclose the first source cap and the first drain cap comprise germanium and boron.
However, Glass discloses the first source cap and the first drain cap comprise germanium and boron 317, 319 (Fig. 3, Para. 42). Glass teaches the above modification is used to Improve contact resistance (Para. 42). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to substitute More cap layer material with Glass cap layer material as suggested above to Improve contact resistance (Para. 42).
Regarding claim 17, More discloses the electronic device of Claim 16, wherein the refractory metal comprises molybdenum, niobium, rhenium, tantalum, or tungsten (liner, Para. 45).
Regarding claim 18, More discloses the electronic device of Claim 16, wherein the at least one transistor further includes: a first conductive contact 120 (left) on the second source cap (liner, Para. 45); and a second conductive contact 120 (right) on the second drain cap (liner, Para. 45).
Regarding claim 19, Monchiero discloses the electronic device of Claim 16, wherein the integrated circuit further includes processing circuitry, communications circuitry, or memory circuitry (Para. 25), wherein the at least one transistor is included in the processing circuitry, the communications circuitry, or the memory circuitry (Para. 22).
Regarding claim 20, Monchiero discloses the electronic device of Claim 16, wherein the electronic device is a mobile device, a wearable device, a computer (Para. 13), a server, a video playback device, a video game console, a display device, a camera, or an appliance.
Claim(s) 26 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over More et al (US 2018/0174913 A1) in view of Glass et al (US 2013/0248999 A1) and further in view of Wang et al (US 2021/0272956 A1).
Regarding claim 26, More in view of Glass does not explicitly disclose the semiconductor die of Claim 1, wherein the second cap layer encapsulates the first cap layer.
However, Wang disclose the second cap layer 1310, 1330 (Fig. 22, Para. 36) encapsulates the first cap layer 436 (Para. 22). Wang teaches the above modification is used to reduce contact resistance of the device (Para. 2). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to substitute More in view of Glass first and second cap layers with Wang first and second cap layers as suggested above to reduce contact resistance of the device (Para. 2).
Regarding claim 27, More in view of Glass does not explicitly disclose the semiconductor die of Claim 1, wherein the second cap layer 1310, 1330 conformally covers the first cap layer 436.
Wang teaches the above modification is used to reduce contact resistance of the device (Para. 2). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to substitute More in view of Glass first and second cap layers with Wang first and second cap layers as suggested above to reduce contact resistance of the device (Para. 2).
Conclusion
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BILKIS . JAHAN
Primary Examiner
Art Unit 2817
/BILKIS JAHAN/Primary Examiner, Art Unit 2817
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