DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to claims filed 06/08/2026.
Claims 1-20 are pending.
Claim Objections
Claim 5 is objected to because of the following informalities: “in response to predicting at least one of a workload release at an end of the workload being processed” should read “in response to predicting . Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 6, 7, 9-13, 15-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Malaya (US 2022/0318056 A1) in view of Zhang (US 2023/0353049 A1).
Regarding Claim 1, Malaya teaches:
A device, comprising: one or more circuits, including hardware, to dynamically adjust a load profile of one or more processing devices processing a workload in a bulk-synchronous mode, “Full-scale workloads, such as workloads used in machine learning training applications, sometimes include periods of heavy power loads on devices followed by periods where the same devices are idle. For example, parallel computing workloads often include periods of synchronized high-powered computation (on the order of seconds) and low-powered communication of computed results (on the order of seconds)” [Malaya ¶ 7]. “In various embodiments, each of computing devices 102-106 includes one or more processors such as a parallel processor (e.g., vector processors, graphics processing units (GPUs), general-purpose GPUs (GPGPUs), non-scalar processors, highly-parallel processors, artificial intelligence (AI) processors, inference engines, machine learning processors, other multithreaded processing units, and the like)” [Malaya ¶ 10 Examiner notes ¶ 29 of the specification discusses examples of bulk-synchronous workloads which includes workloads for artificial intelligence].
wherein, in response to power consumed by the one or more processing devices dropping below a first power threshold, “In this manner, the GPU 202 hardware autonomously starts running power burn workloads when the hardware itself detects changes in power usage falling below the predetermined power floor threshold (first power threshold)” [Malaya ¶ 25].
the one or more circuits are to dynamically adjust the load profile by operating an on-die current sink circuit independently of the one or more processing devices executing software instructions to: draw current to raise the power consumed by the one or more processing devices to the first power threshold; “For example and with respect to FIG. 2, in various embodiments, the command processor 204 is capable of launching multiple different kernels of target power workload (e.g., designed to burn 100 W, 200 W, 300 W, 400 W, and 500 W of power) on the design of the GPU 202 and for targeting particular target power usage levels. In various embodiments, the SMU 210 instructs the GPU 202 to operate at that threshold power floor level until the command processor 204 is instructed to begin processing productive workloads” [Malaya ¶ 30]. “At block 410, based on receiving the power dip condition signal from the command processor 204 submits work to target a certain power load, whether that is at the previous level or a floor level” [Malaya ¶ 38]. “In some embodiments, the system driver 212 defines and communicates to the SMU 210 an amount of time that the SMU 210 needs to ensure that the power floor is maintained subsequent to a power dip condition” [Malaya ¶ 23]. “The method of claim 2, wherein assigning one or more target power workloads includes the workload scheduler assigning one or more target power workloads to raise the power draw by the processor device to meet or exceed the target power draw” [Malaya Claim 5].
and gradually reduce the drawn current to cause a corresponding reduction in the power consumed by the one or more processing devices to gradually drop from the first power threshold. “Additionally, it is not necessary to indefinitely perform target power workloads for the purposes of power burn. In some embodiments, the command processor 204 and the SMU 210 gradually decrease power usage by running a first power burn kernel of a higher power usage (e.g., a target power workload designed to power burn at 500 W) for a first period of time, switching to a second power burn kernel of a lower power usage (e.g., a target power workload designed to power bum at 400 W), and so forth, thereby decreasing the amount of power consumed by GPU 202 over time” [Malaya ¶ 24].
Malaya fails to explicitly teach operating an on-die current sink circuit independently of the one or more processing devices executing software instructions.
However, Zhang teaches operating an on-die current sink circuit independently of the one or more processing devices executing software instructions to: “Electronic systems, such as computers or computing systems, typically include power management integrated circuits for regulating the power usage of the electronic systems. Furthermore, electronic systems incorporating integrated circuits typically employ voltage regulators to convert a main bus voltage from a power source supplying the system to one or more voltages necessary for driving the integrated circuits therein” [Zhang ¶ 2]. “The normal operation of the switching regulator includes positive current operation where the power stage sources current (positive current) to the load and negative current operation where the power stage sinks current (negative current) from the load. In some applications, negative current operation is used to improve performance of the host system, such as by performing load release (changing the load current from a high current value to a low current value or negative voltage transitions (changing the output voltage from a high value to a low value by discharging the output node)” [Zhang ¶ 6]. “In some applications, the switching regulator may be employed in computing systems to supply power to processors, or microprocessors, or CPU or GPU” [Zhang ¶ 20].
Zhang is considered to be analogous to the claimed invention because it is in the same field of system power management. Malaya includes power burn kernels run at the hardware to consume target amounts of excess power; this can be combined with the teachings of Zhang which provides a switching regulator operated independently of the processors which it supplies. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Malaya to incorporate the teachings of Zhang and include operating an on-die current sink circuit independently of the one or more processing devices executing software instructions. Doing so would allow for the sinking of excess current without having to disrupt currently processing operations. “As will be appreciated by those skilled in the art, in some embodiments, the GPU 202 should not continue its previous workload that was running prior to the SMU 210 detecting the power dip condition. Although the previous workload may maintain a particular power level, such computations risk generating unintended answers and ruining the results of previous computations if intermingled” [Malaya ¶ 19].
Regarding Claim 3, Malaya in view of Zhang teaches the device of claim 1, as referenced above. Malaya further teaches wherein the power consumed dropping below the first power threshold is caused at least in part by a workload release at an end of the workload being processed. “At time=T0, the processing device is in a low power draw state due to, for example, computations for a previous productive workload ending and causing power draw by the processing device to fall below a threshold power floor level (labeled as Ptarget in FIG. 3).” [Malaya ¶ 28].
Malaya fails to explicitly teach a workload release at an end of the workload being processed.
However, Zhang teaches a workload release at an end of the workload being processed. “The normal operation of the switching regulator includes positive current operation where the power stage sources current (positive current) to the load and negative current operation where the power stage sinks current (negative current) from the load. In some applications, negative current operation is used to improve performance of the host system, such as by performing load release (changing the load current from a high current value to a low current value or negative voltage transitions (changing the output voltage from a high value to a low value by discharging the output node)” [Zhang ¶ 6].
Regarding Claim 6, Malaya in view of Zhang teaches the device of claim 1 as referenced above. Malaya further teaches wherein an amount of time between the power consumed dropping below the first power threshold before being raised back to the first power threshold by the drawn current is less than 1ms. “The SMU 210 monitors a power usage of the GPU 202 over a period of time (e.g., on a short granularity, such as a millisecond or shorter) to determine whether power load on the GPU 202 dips below the power floor level over the specified period of time (e.g., di/dt time rate of change of current consumption, such as over a few milliseconds)” [Malaya ¶ 35]. “As will be appreciated, the action time scale of the dynamic system load management described herein is limited only by the time scale of measurement interval, which can include milliseconds or microseconds” [Malaya ¶ 44].
Regarding Claim 7, Malaya in view of Zhang teaches the device of claim 1 as referenced above. Malaya further teaches:
wherein the one or more circuits raise the power consumed by the one or more processing devices “The method of claim 2, wherein assigning one or more target power workloads includes the workload scheduler assigning one or more target power workloads to raise the power draw by the processor device to meet or exceed the target power draw” [Malaya Claim 5].
by injecting additional work after the workload. “In addition, it is difficult to prevent large dips in power consumption (resulting from dip in current as computations end, causing voltage spikes) as even higher power states cannot easily maintain a similar amount of dynamic power usage as a fully loaded processor (e.g., having a 500 W GPU board drawing maximum power for seconds or minutes after the GPU chip becomes idle and stops processing productive workloads would be difficult)” [Malaya ¶ 12]. “A workload scheduler (such as the command processor) is provided with a plurality of power burn kernels of known power draw (e.g., target power workloads). In some embodiments, a target power workload includes an idle power burn kernel used when there is no driver-initiated productive workloads” [Malaya ¶ 38].
Regarding Claim 9, Malaya teaches:
A cluster manager, comprising: at least one processor; and memory including instructions that when executed by the at least one processor cause the at least one processor to: “As shown, the GPU 202 includes a command processor 204 that receives commands in a command stream from, for example, a corresponding device driver (not shown) and coordinates processing within the GPU 202 … In various embodiments, the GPU 202 also includes a local memory 208 (e.g., on-chip RAM) for storing register data, storing workload code, and the like. In various embodiments, the GPU 202 also implements various system monitoring and power saving functions” [Malaya ¶ 14-15-16].
determine, based on one or more power delivery specifications, one or more load profiles for one or more processing devices “For example, in some embodiments, the GPU 202 includes a microcontroller 210 such as a system management unit (SMU) that is configured for enforcing numerous protection mechanisms (e.g., chip-wide and device block thermal constraints, di/dt (rate of change of the charge current (i) over time (t)) limits, voltage droop mitigation, etc.), in addition to performing a plethora of dynamic performance optimizations” [Malaya ¶ 16]. “In various embodiments, a job scheduler (not shown) or other management tool communicates a power floor and a unit of time that the power floor should be maintained (power delivery specification) via a system driver 212. The system driver 212 communicates the power floor and unit of time information to the SMU 210 through a number of techniques such as memory-mapped input/output (MMIO) or in-memory mailboxes” [Malaya ¶ 18]. “The command processor 204, upon receiving a power dip condition signal 212, launches target power workload(s) to the CUs 206. As described in more detail below, target power workloads are designed to burn predetermined, fixed amounts of power to enable reaching and maintaining a target power draw” [Malaya ¶ 19]. “The system driver 212 communicates information regarding one or more target power workloads including pre-compiled kernels of known power load (load profile) (such as double-precision matrix-matrix multiplication (DGEMM) kernels) and stores the target power workload code at the local memory module 208 of the GPU 202” [Malaya ¶ 20].
that process a workload in a bulk- synchronous mode; “Full-scale workloads, such as workloads used in machine learning training applications, sometimes include periods of heavy power loads on devices followed by periods where the same devices are idle. For example, parallel computing workloads often include periods of synchronized high-powered computation (on the order of seconds) and low-powered communication of computed results (on the order of seconds)” [Malaya ¶ 7]. “In various embodiments, each of computing devices 102-106 includes one or more processors such as a parallel processor (e.g., vector processors, graphics processing units (GPUs), general-purpose GPUs (GPGPUs), non-scalar processors, highly-parallel processors, artificial intelligence (AI) processors, inference engines, machine learning processors, other multithreaded processing units, and the like)” [Malaya ¶ 10 Examiner notes ¶ 29 of the specification discusses examples of bulk-synchronous workloads which includes workloads for artificial intelligence].
and send the one or more load profiles to the one or more processing devices, “The system driver 212 communicates information regarding one or more target power workloads including pre-compiled kernels of known power load (such as double-precision matrix-matrix multiplication (DGEMM) kernels) and stores the target power workload code at the local memory module 208 of the GPU 202” [Malaya ¶ 20]. “The command processor 204, upon receiving a power dip condition signal 212, launches target power workload(s) to the CUs 206. As described in more detail below, target power workloads are designed to burn predetermined, fixed amounts of power to enable reaching and maintaining a target power draw” [Malaya ¶ 19].
wherein at least one load profile of the one or more load profiles causes, in response to power consumed by the one or more processing devices dropping below a first power threshold, “In this manner, the GPU 202 hardware autonomously starts running power burn workloads when the hardware itself detects changes in power usage falling below the predetermined power floor threshold (first power threshold)” [Malaya ¶ 25].
one or more on-die current sink circuits to operate independently of the one or more processing devices executing software instructions to: draw current to raise the power consumed by the one or more processing devices to the first power threshold; “For example and with respect to FIG. 2, in various embodiments, the command processor 204 is capable of launching multiple different kernels of target power workload (e.g., designed to burn 100 W, 200 W, 300 W, 400 W, and 500 W of power) on the design of the GPU 202 and for targeting particular target power usage levels. In various embodiments, the SMU 210 instructs the GPU 202 to operate at that threshold power floor level until the command processor 204 is instructed to begin processing productive workloads” [Malaya ¶ 30]. “At block 410, based on receiving the power dip condition signal from the command processor 204 submits work to target a certain power load, whether that is at the previous level or a floor level” [Malaya ¶ 38]. “In some embodiments, the system driver 212 defines and communicates to the SMU 210 an amount of time that the SMU 210 needs to ensure that the power floor is maintained subsequent to a power dip condition” [Malaya ¶ 23]. “The method of claim 2, wherein assigning one or more target power workloads includes the workload scheduler assigning one or more target power workloads to raise the power draw by the processor device to meet or exceed the target power draw” [Malaya Claim 5].
and gradually reduce the drawn current to cause a corresponding reduction in the power consumed by the one or more processing devices to gradually drop from the first power threshold. “Additionally, it is not necessary to indefinitely perform target power workloads for the purposes of power burn. In some embodiments, the command processor 204 and the SMU 210 gradually decrease power usage by running a first power burn kernel of a higher power usage (e.g., a target power workload designed to power burn at 500 W) for a first period of time, switching to a second power burn kernel of a lower power usage (e.g., a target power workload designed to power bum at 400 W), and so forth, thereby decreasing the amount of power consumed by GPU 202 over time” [Malaya ¶ 24].
Malaya fails to explicitly teach one or more on-die current sink circuits to operate independently of the one or more processing devices executing software instructions.
However, Zhang teaches one or more on-die current sink circuits to operate independently of the one or more processing devices executing software instructions “Electronic systems, such as computers or computing systems, typically include power management integrated circuits for regulating the power usage of the electronic systems. Furthermore, electronic systems incorporating integrated circuits typically employ voltage regulators to convert a main bus voltage from a power source supplying the system to one or more voltages necessary for driving the integrated circuits therein” [Zhang ¶ 2]. “The normal operation of the switching regulator includes positive current operation where the power stage sources current (positive current) to the load and negative current operation where the power stage sinks current (negative current) from the load. In some applications, negative current operation is used to improve performance of the host system, such as by performing load release (changing the load current from a high current value to a low current value or negative voltage transitions (changing the output voltage from a high value to a low value by discharging the output node)” [Zhang ¶ 6]. “In some applications, the switching regulator may be employed in computing systems to supply power to processors, or microprocessors, or CPU or GPU” [Zhang ¶ 20].
Zhang is considered to be analogous to the claimed invention because it is in the same field of system power management. Malaya includes power burn kernels run at the hardware to consume target amounts of excess power; this can be combined with the teachings of Zhang which provides a switching regulator operated independently of the processors which it supplies. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Malaya to incorporate the teachings of Zhang and include one or more on-die current sink circuits to operate independently of the one or more processing devices executing software instructions. Doing so would allow for the sinking of excess current without having to disrupt currently processing operations. “As will be appreciated by those skilled in the art, in some embodiments, the GPU 202 should not continue its previous workload that was running prior to the SMU 210 detecting the power dip condition. Although the previous workload may maintain a particular power level, such computations risk generating unintended answers and ruining the results of previous computations if intermingled” [Malaya ¶ 19].
Regarding Claim 10, Malaya in view of Zhang teaches the cluster manager of claim 9 as referenced above. Malaya further teaches wherein the one or more processing devices comprise a plurality of processing devices. “For example, in various embodiments, the computing devices 102-106 includes processing units such as graphics processing units (GPUs), central processing units (CPUs), field programmable gate arrays (FPGAs), and the like on the same board or on separate carrier boards that are connected to each other via a backplane” [Malaya ¶ 9].
Regarding Claim 11, Malaya in view of Zhang teaches the cluster manager of claim 10 as referenced above. Malaya further teaches wherein the plurality of processing devices comprise a plurality of Graphics Processing Units (GPUs). “For example, in various embodiments, the computing devices 102-106 includes processing units such as graphics processing units (GPUs), central processing units (CPUs), field programmable gate arrays (FPGAs), and the like on the same board or on separate carrier boards that are connected to each other via a backplane” [Malaya ¶ 9]. “In various embodiments, each of computing devices 102-106 includes one or more processors such as a parallel processor (e.g., vector processors, graphics processing units (GPUs), general-purpose GPU s (GPGPUs), non-scalar processors, highly-parallel processors, artificial intelligence (AI) processors, inference engines, machine learning processors, other multithreaded processing units, and the like)” [Malaya ¶ 10].
Regarding Claim 12, Malaya in view of Zhang teaches the cluster manager of claim 10 as referenced above. Malaya further teaches wherein additional work is injected to at least some of the plurality of processing devices after the workload is processed “In addition, it is difficult to prevent large dips in power consumption (resulting from dip in current as computations end, causing voltage spikes) as even higher power states cannot easily maintain a similar amount of dynamic power usage as a fully loaded processor (e.g., having a 500 W GPU board drawing maximum power for seconds or minutes after the GPU chip becomes idle and stops processing productive workloads would be difficult)” [Malaya ¶ 12]. “A workload scheduler (such as the command processor) is provided with a plurality of power burn kernels of known power draw (e.g., target power workloads). In some embodiments, a target power workload includes an idle power burn kernel used when there is no driver-initiated productive workloads” [Malaya ¶ 38].
to control their respective load profiles. “The method of claim 2, wherein assigning one or more target power workloads includes the workload scheduler assigning one or more target power workloads to raise the power draw by the processor device to meet or exceed the target power draw” [Malaya Claim 5].
Regarding Claim 13, Malaya in view of Zhang teaches the cluster manager of claim 9, as referenced above. Malaya further teaches:
wherein the at least one load profile corresponds to a ramp-down load profile “In other embodiments, the SMU 210 and command processor 204 instruct the CUs 206 to process the same target power workload (load profile) while walking down the voltage-frequency points at which the GPU 202 operates (e.g., gradually decreases power usage (ramp-down) by running the same power-bum kernel), such as by utilizing power management techniques including dynamic voltage and frequency scaling (DVFS) to dynamically adjust an operating voltage and frequency point (referred to as a "p-state") across GPU 202 components during run time” [Malaya ¶ 24].
applied at an end of the workload. “At time=T0, the processing device is in a low power draw state due to, for example, computations for a previous productive workload ending and causing power draw by the processing device to fall below a threshold power floor level (labeled as Ptarget in FIG. 3).” [Malaya ¶ 28]. “At time=T1, the power monitor of the processing device (e.g., SMU 210 or other power monitoring firmware at the GPU 202 of FIG. 2) detects the power dip condition by observing that power utilized by the GPU 202 dips below the power floor over a specified period of time (e.g., di/dt time rate of change of current consumption, such as over a few milliseconds). Accordingly, the SMU 210 notifies the command processor 204 of the power dip condition and the command processor 204 begins launching target power workloads (precompiled kernels for execution to generate dynamic work by producing results to be discarded for the purposes of burning power) to the CUs 206.” [Malaya ¶ 29].
Regarding Claim 15, Malaya teaches:
A Graphics Processing Unit (GPU), “Additionally, although described with respect to FIG. 2 in the context of a GPU 202 device, those skilled in the art will recognize that the concepts disclosed herein are applicable to various processors, including datacenters with heterogeneous system architectures (HSA) where compute systems are expected to be used for a variety of compute intensive models using combinations of any of the following: CPUs, GPUs, FPGAs, custom ASICs, and the like” [Malaya ¶ 26].
comprising: an on-die current sink circuit; “The GPU 202 includes a plurality of compute units (CUs) 206 that are generally configured to execute sets of instructions (e.g., computer programs) that manipulate the circuitry of the GPU 202 to carry out defined tasks” [Malaya ¶ 15]. “The command processor 204, upon receiving a power dip condition signal 212, launches target power workload(s) to the CUs 206. As described in more detail below, target power workloads are designed to burn predetermined, fixed amounts of power to enable reaching and maintaining a target power draw” [Malaya ¶ 19].
and one or more circuits, including hardware, to dynamically adjust a load profile for the GPU “For example and with respect to FIG. 2, in various embodiments, the command processor 204 is capable of launching multiple different kernels of target power workload (e.g., designed to burn 100 W, 200 W, 300 W, 400 W, and 500 W of power) on the design of the GPU 202 and for targeting particular target power usage levels. In various embodiments, the SMU 210 instructs the GPU 202 to operate at that threshold power floor level until the command processor 204 is instructed to begin processing productive workloads” [Malaya ¶ 30].
when the GPU is operated to process a workload in a bulk-synchronous mode with one or more other GPUs, “Full-scale workloads, such as workloads used in machine learning training applications, sometimes include periods of heavy power loads on devices followed by periods where the same devices are idle. For example, parallel computing workloads often include periods of synchronized high-powered computation (on the order of seconds) and low-powered communication of computed results (on the order of seconds)” [Malaya ¶ 7]. “In various embodiments, each of computing devices 102-106 includes one or more processors such as a parallel processor (e.g., vector processors, graphics processing units (GPUs), general-purpose GPUs (GPGPUs), non-scalar processors, highly-parallel processors, artificial intelligence (AI) processors, inference engines, machine learning processors, other multithreaded processing units, and the like)” [Malaya ¶ 10 Examiner notes ¶ 29 of the specification discusses examples of bulk-synchronous workloads which includes workloads for artificial intelligence].
wherein, in response to power consumed by the GPU dropping below a first power threshold, “In this manner, the GPU 202 hardware autonomously starts running power burn workloads when the hardware itself detects changes in power usage falling below the predetermined power floor threshold (first power threshold)” [Malaya ¶ 25].
the one or more circuits are to dynamically adjust the load profile by operating the on-die current sink circuit independently of the GPU executing software instructions to: raise the power consumed by the GPU to the first power threshold; “For example and with respect to FIG. 2, in various embodiments, the command processor 204 is capable of launching multiple different kernels of target power workload (e.g., designed to burn 100 W, 200 W, 300 W, 400 W, and 500 W of power) on the design of the GPU 202 and for targeting particular target power usage levels. In various embodiments, the SMU 210 instructs the GPU 202 to operate at that threshold power floor level until the command processor 204 is instructed to begin processing productive workloads” [Malaya ¶ 30]. “At block 410, based on receiving the power dip condition signal from the command processor 204 submits work to target a certain power load, whether that is at the previous level or a floor level” [Malaya ¶ 38]. “In some embodiments, the system driver 212 defines and communicates to the SMU 210 an amount of time that the SMU 210 needs to ensure that the power floor is maintained subsequent to a power dip condition” [Malaya ¶ 23]. “The method of claim 2, wherein assigning one or more target power workloads includes the workload scheduler assigning one or more target power workloads to raise the power draw by the processor device to meet or exceed the target power draw” [Malaya Claim 5].
and gradually reduce the drawn current to cause a corresponding reduction in the power consumed by the GPU to gradually drop from the first power threshold. “Additionally, it is not necessary to indefinitely perform target power workloads for the purposes of power burn. In some embodiments, the command processor 204 and the SMU 210 gradually decrease power usage by running a first power burn kernel of a higher power usage (e.g., a target power workload designed to power burn at 500 W) for a first period of time, switching to a second power burn kernel of a lower power usage (e.g., a target power workload designed to power bum at 400 W), and so forth, thereby decreasing the amount of power consumed by GPU 202 over time” [Malaya ¶ 24].
Malaya fails to explicitly teach operating the on-die current sink circuit independently of the GPU executing software instructions.
However, Zhang teaches operating the on-die current sink circuit independently of the GPU executing software instructions “Electronic systems, such as computers or computing systems, typically include power management integrated circuits for regulating the power usage of the electronic systems. Furthermore, electronic systems incorporating integrated circuits typically employ voltage regulators to convert a main bus voltage from a power source supplying the system to one or more voltages necessary for driving the integrated circuits therein” [Zhang ¶ 2]. “The normal operation of the switching regulator includes positive current operation where the power stage sources current (positive current) to the load and negative current operation where the power stage sinks current (negative current) from the load. In some applications, negative current operation is used to improve performance of the host system, such as by performing load release (changing the load current from a high current value to a low current value or negative voltage transitions (changing the output voltage from a high value to a low value by discharging the output node)” [Zhang ¶ 6]. “In some applications, the switching regulator may be employed in computing systems to supply power to processors, or microprocessors, or CPU or GPU” [Zhang ¶ 20].
Zhang is considered to be analogous to the claimed invention because it is in the same field of system power management. Malaya includes power burn kernels run at the hardware to consume target amounts of excess power; this can be combined with the teachings of Zhang which provides a switching regulator operated independently of the processors which it supplies. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Malaya to incorporate the teachings of Zhang and include operating the on-die current sink circuit independently of the GPU executing software instructions. Doing so would allow for the sinking of excess current without having to disrupt currently processing operations. “As will be appreciated by those skilled in the art, in some embodiments, the GPU 202 should not continue its previous workload that was running prior to the SMU 210 detecting the power dip condition. Although the previous workload may maintain a particular power level, such computations risk generating unintended answers and ruining the results of previous computations if intermingled” [Malaya ¶ 19].
Regarding Claim 16, Malaya in view of Zhang teaches the GPU of claim 15 as referenced above. Malaya further teaches wherein the one or more circuits receive information for the load profile from a cluster manager that manages the GPU and the one or more other GPUs. “In various embodiments, a job scheduler (not shown) or other management tool communicates a power floor and a unit of time that the power floor should be maintained via a system driver 212 (cluster manager). The system driver 212 communicates the power floor and unit of time information to the SMU 210 through a number of techniques such as memory-mapped input/output (MMIO) or in-memory mailboxes” [Malaya ¶ 18]. “For example, in various embodiments, the workload scheduler logic is implemented at least in part at a host processor driver or at a processor core external to the GPU 202. Additionally, although described with respect to FIG. 2 in the context of a GPU 202 device, those skilled in the art will recognize that the concepts disclosed herein are applicable to various processors, including datacenters with heterogeneous system architectures (HSA) where compute systems are expected to be used for a variety of compute intensive models using combinations of any of the following: CPUs, GPUs, FPGAs, custom ASICs, and the like” [Malaya ¶ 26].
Regarding Claim 17, Malaya in view of Zhang teaches the GPU of claim 16, as referenced above.
Malaya further teaches wherein the information comprises the first power threshold. “In various embodiments, a job scheduler (not shown) or other management tool communicates a power floor (first power threshold) and a unit of time that the power floor should be maintained via a system driver 212. The system driver 212 communicates the power floor and unit of time information to the SMU 210 through a number of techniques such as memory-mapped input/output (MMIO) or in-memory mailboxes” [Malaya ¶ 18]. “In some embodiments, each of one or more device (e.g., a GPU 202 of FIG. 2) includes a control system by which power and compute loads are monitored and varied to enable reaching and maintaining a target power draw in accordance with a user specified threshold power level and/or rate of change in power usage” [Malaya ¶ 36].
Regarding Claim 18, Malaya in view of Zhang teaches the GPU of claim 17, as referenced above. Malaya further teaches wherein the information comprises slope information that governs how the one or more circuits dynamically adjust the load profile. “In various embodiments, a job scheduler (not shown) or other management tool communicates a power floor and a unit of time that the power floor should be maintained via a system driver 212. The system driver 212 communicates the power floor and unit of time information to the SMU 210 through a number of techniques such as memory-mapped input/output (MMIO) or in-memory mailboxes” [Malaya ¶ 18]. “In other embodiments, the power floor instruction is a user setting that does not specify particular target power usage levels but instead specifies the rate at which power usage of the GPU changes over a period of time. For example, in some embodiments, the power floor instruction includes a predetermined di/dt rate of change (slope information). This information is then provided to each of one or more processing devices (which may be CPUs, GPUs, ASICs, and the like) so they have a corresponding target power draw (or 'power load' as used interchangeably throughout this disclosure)” [Malaya ¶ 33].
Regarding Claim 20, Malaya in view of Zhang teaches the GPU of claim 17, as referenced above. Malaya further teaches:
wherein the information comprises a second power threshold, “In some embodiments, each of one or more device (e.g., a GPU 202 of FIG. 2) includes a control system by which power and compute loads are monitored and varied to enable reaching and maintaining a target power draw in accordance with a user specified threshold power level and/or rate of change in power usage (second power threshold)” [Malaya ¶ 36].
wherein the one or more circuits begin adjusting the load profile in response to power consumed by the GPU exceeding the second power threshold. “The method of claim 3, wherein identifying the power dip condition includes a determination by the power monitor of the power draw by the processor device falling below the threshold power floor level at a rate exceeding the threshold rate of power change” [Malaya Claim 4]. “A method, comprising: communicating a power dip condition to a workload scheduler of a processor device in response to identifying the power dip condition; and assigning, based at least in part on the power dip condition, one or more target power workloads for execution at the processor device, wherein each of the one or more target power workloads is associated with a known power load” [Malaya Claim 1].
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Malaya (US 2022/0318056 A1) in view of Zhang (US 2023/0353049 A1) in view of Whatmough (US 2023/0297432 A1) in view of Ernewein (US 2020/0073470 A1).
Regarding Claim 2, Malaya in view of Zhang teaches the device of claim 1, as referenced above. Malaya in view of Zhang fails to explicitly teach wherein, in response to the power consumed by the one or more processing devices exceeding a second power threshold, the one or more circuits are to dynamically adjust a ramp-up load profile of the one or more processing devices by controlling an on-die current throttle circuit to gradually source current.
However, Whatmough teaches:
wherein, in response to the power consumed by the one or more processing devices exceeding a second power threshold, the one or more circuits are to dynamically adjust a ramp-up load profile of the one or more processing devices “In some instances, these specialized hardware units achieve high utilization for various NN workloads and subsequently generate high current consumption. In various scenarios, when utilization increases (ramp-up) or decreases rapidly, there may be a corresponding step or spike in the current consumption” [Whatmough ¶ 11]. “At block 714, method 700 may determine di/dt events, such as, e.g., whether the actual current (Icurr) is greater than the previous current (Iprev). At decision block 718, method 700 may determine whether a di/dt event (e.g., rapid change in current or voltage) is likely. If no, then method 700 proceeds to block 720 so as to schedule the graph as normal, and method 700 may return to block 714 for further processing. If yes, then method may proceed to block 724 so as to modify scheduling of the graph through NOPs/clock-gating cycles as supported by the target hardware (HW). Thus, method 700 may modify the pre-determined scheduling graph dynamically with deliberate insertion of NOP operations or clock-gating cycles supported by the hardware” [Whatmough ¶ 60].
by controlling an on-die current throttle circuit to gradually source current “If yes, then method may proceed to block 724 so as to modify scheduling of the graph through NOPs/clock-gating cycles as supported by the target hardware (HW). Thus, method 700 may modify the pre-determined scheduling graph dynamically with deliberate insertion of NOP operations or clock-gating cycles supported by the hardware” [Whatmough ¶ 60 Examiner notes this interpretation of an on-die current throttle is in accordance with the examples given in paragraph 40 of the instant specification]. “At block 728, method 700 may modify the graph schedule and/or deploy an optimized graph to mitigate various di/dt events, such as, e.g., rapid voltage droops and/or current spikes” [Whatmough ¶ 63]. “In various implementations, dynamic scheduling techniques for neural networks may refer to a method that is configured to monitor the workload operations of the neural network for current spikes, insert dummy operations between workload operations, and measure current-demand of the neural network to identify load current transitions between the workload operations and dummy operations that result in rapid changes in load current consumption of the neural network … The method may modify the load scheduling of the neural network to smooth and stabilize the current transitions between workload operations and dummy operations” [Whatmough ¶ 64]. “Other types of management policy may also be controlled based on metadata, such as dynamic voltage or frequency scaling, requests to a voltage regulator for supply of more or less voltage, as well as a scheme for limiting the rate of change of power requirements by monitoring differences over time of expected power requirements and taking action to smooth changes in power demand when required, e.g., by either throttling the dispatch of data or instructions to the processing circuitry 520” [Whatmough ¶ 48].
Whatmough is considered to be analogous to the claimed invention because it is in the same field of system power management. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Malaya in view of Zhang to incorporate the teachings of Whatmough and include wherein, in response to the power consumed by the one or more processing devices exceeding a second power threshold, the one or more circuits are to dynamically adjust a ramp-up load profile of the one or more processing devices by controlling an on-die current throttle circuit to gradually source current. Doing so would allow for efficient workload management when processing device utilization rapidly increases. “In some instances, these specialized hardware units achieve high utilization for various NN workloads and subsequently generate high current consumption. In various scenarios, when utilization increases or decreases rapidly, there may be a corresponding step or spike in the current consumption” [Whatmough ¶ 11].
Malaya in view of Zhang in view of Whatmough fails to explicitly teach gradually source current until the power consumed by the one or more processing devices reaches a power level for processing the workload.
However, Ernewein teaches gradually source current until the power consumed by the one or more processing devices reaches a power level for processing the workload. “On the other hand, if the prediction is made that the compute array is transitioning from to idle to active (the YES branch of block 706) the frequency or rate of the core clock is incrementally increased over a time interval, i.e., incremented, (such as by clock rate controller 208) in block 712. For example, the clock frequency may be incremented over a time interval such that the clock frequency ramps up from an initial (lower frequency to a target (higher) frequency. The clock frequency may be incremented beginning at the time the computer array is predicted to become active (i.e., predicted to begin to perform computations upon operands)” [Ernewein ¶ 47].
Ernewein is considered to be analogous to the claimed invention because it is in the same field of system power management. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Malaya in view of Zhang in view of Whatmough to incorporate the teachings of Ernewein and include gradually source current until the power consumed by the one or more processing devices reaches a power level for processing the workload. Doing so would allow for the processing devices to only be activated when needed. “Such parallel operation of the computing elements can consume large amounts of power, and it is desirable to only activate the array/computing elements when needed. For example, as illustrated in FIG. 1, a parallel processor 102, which may be a neural processor, comprises an array of parallel computing elements 104, each computing element 104 able to independently operate on operands and to provide an output” [Ernewein ¶ 3].
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Malaya (US 2022/0318056 A1) in view of Zhang (US 2023/0353049 A1) in view of Ernewein (US 2020/0073470 A1).
Regarding Claim 4, Malaya in view of Zhang teaches the device of claim 1 as referenced above.
Malaya in view of Zhang fails to teach wherein the one or more circuits are to begin dynamically adjusting a ramp-up load profile of one or more processing devices in response to detecting a workload ramp-up at a beginning of the workload being processed.
However, Ernewein teaches wherein the one or more circuits are to begin dynamically adjusting a ramp-up load profile of one or more processing devices in response to detecting a workload ramp-up at a beginning of the workload being processed. “On the other hand, if the prediction is made that the compute array is transitioning from to idle to active (the YES branch of block 706) the frequency or rate of the core clock is incrementally increased over a time interval, i.e., incremented, (such as by clock rate controller 208) in block 712. For example, the clock frequency may be incremented over a time interval such that the clock frequency ramps up from an initial (lower frequency to a target (higher) frequency. The clock frequency may be incremented beginning at the time the computer array is predicted to become active (i.e., predicted to begin to perform computations upon operands)” [Ernewein ¶ 47]. “As will be understood, the current draw of such an array of parallel computing elements 104 in an active state differs greatly from the current draw of the computing elements 104 in an idle state. As a result, activating the array from idle as illustrated in FIG. 1, or idling the array from an active status, leads to large instantaneous changes in current (∆i/∆t). Such large ∆i/∆t can cause voltage spikes or droops or other events that lead to performance loss or even functional failure of the processor” [Ernewein ¶ 4].
Ernewein is considered to be analogous to the claimed invention because it is in the same field of system power management. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Malaya in view of Zhang to incorporate the teachings of Ernewein and include: the one or more circuits are to begin dynamically adjusting a ramp-up load profile of one or more processing devices in response to detecting a workload ramp-up at a beginning of the workload being processed. Doing so would allow for efficient workload management when processing devices transition from idle to active. “An exemplary method comprises monitoring the array of computing elements and determining a transition from a first activity level of the array to a second activity level of the array, such as an idle-to-active or active-to-idle transition” [Ernewein ¶ 6].
Regarding Claim 5, Malaya in view of Zhang teaches the device of claim 1 as referenced above. Malaya further teaches teach wherein the ramp-down load profile is dynamically adjusted “Referring now to FIG. 2, illustrated is a block diagram illustrating dynamic system load power management for smoothing system power usage at a GPU in accordance with some embodiments” [Malaya ¶ 9]. “Additionally, it is not necessary to indefinitely perform target power workloads for the purposes of power burn. In some embodiments, the command processor 204 and the SMU 210 gradually decrease power usage by running a first power burn kernel of a higher power usage (e.g., a target power workload designed to power burn at 500 W) for a first period of time, switching to a second power burn kernel of a lower power usage (e.g., a target power workload designed to power bum at 400 W), and so forth, thereby decreasing the amount of power consumed by GPU 202 over time” [Malaya ¶ 24].
Malaya in view of Zhang fails to teach wherein the ramp-down load profile is dynamically adjusted in response to predicting at least one of a workload release at an end of the workload being processed.
However, Ernewein teaches wherein the ramp-down load profile is dynamically adjusted in response to predicting at least one of a workload release at an end of the workload being processed. “If a prediction (such as by activity monitor 206) is made that the compute array is transitioning from active to idle (the NO branch of block 706) the frequency or rate of the core clock is incrementally decreased over a time interval, i.e., decremented, in block 708 (such as by clock rate controller 208) before the compute array transitions from the active state to the idle state. For example, the clock frequency may be decremented such that the clock frequency ramps down from an initial (higher) frequency to a target (lower) frequency” [Ernewein ¶ 46].
It would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Malaya in view of Zhang to incorporate the teachings of Ernewein and include: wherein the ramp-down load profile is dynamically adjusted in response to predicting at least one of a workload release at an end of the workload being processed. Doing so would allow for efficient workload management when processing devices transition from idle to active. “An exemplary method comprises monitoring the array of computing elements and determining a transition from a first activity level of the array to a second activity level of the array, such as an idle-to-active or active-to-idle transition” [Ernewein ¶ 6].
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Malaya (US 2022/0318056 A1) in view of Zhang (US 2023/0353049 A1) in view of Wang (US 2020/0097056 A1).
Regarding Claim 8, Malaya in view of Zhang teaches the device of claim 1 as referenced above. Malaya further teaches wherein the one or more processing devices comprise a plurality of Graphics Processing Units (GPUs), “For example, in various embodiments, the computing devices 102-106 includes processing units such as graphics processing units (GPUs), central processing units (CPUs), field programmable gate arrays (FPGAs), and the like on the same board or on separate carrier boards that are connected to each other via a backplane” [Malaya ¶ 9]. “In various embodiments, each of computing devices 102-106 includes one or more processors such as a parallel processor (e.g., vector processors, graphics processing units (GPUs), general-purpose GPU s (GPGPUs), non-scalar processors, highly-parallel processors, artificial intelligence (AI) processors, inference engines, machine learning processors, other multithreaded processing units, and the like)” [Malaya ¶ 10].
Malaya in view of Zhang fails to teach and wherein the one or more circuits comprise a Baseboard Management Controller.
However, Wang teaches and wherein the one or more circuits comprise a Baseboard Management Controller. “Such a determination, i.e., whether the GPUs 108 exceed a prescribed temperature, is made by a baseboard management controller (BMC) 104. In certain embodiments, the GPUs 108 can be in communication with a management bus 130 of the host computer system 100 to provide information regarding the GPUs' health, operating, and performance conditions to the BMC 104. Such information can include the GPU voltage and temperature” [Wang ¶ 24].
Wang is considered to be analogous to the claimed invention because it is in the same field of system power management. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Malaya in view of Zhang to incorporate the teachings of Wang and include: the one or more circuits comprise a Baseboard Management Controller. Doing so would allow for the system to use a management module to assist in the collection and analysis of operating and performance-related parameters. “A computer system typically employs one or more management modules to assist in the collection and analysis of information sensed by the various sensors measuring operating and performance-related parameters within the system. These management modules may be either software or hardware components, but typically encompass both hardware and software components that are implemented by service processors. One such management module is referred to as a "Baseboard Management Controller" (BMC)” [Wang ¶ 4].
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Malaya (US 2022/0318056 A1) in view of Zhang (US 2023/0353049 A1) in view of Cudak (US 9,442,770 B1).
Regarding Claim 14, Malaya in view of Zhang teaches the cluster manager of claim 13, as referenced above. Malaya in view of Zhang fails to explicitly teach wherein the one or more load profiles comprises a ramp-up load profile applied at a beginning of the workload.
However, Cudak teaches wherein the one or more load profiles comprises a ramp-up load profile applied at a beginning of the workload. “The second execution profile 420 includes a pre-execution time period 422 during which substantially no amount of a resource of a device is used. The second execution profile 420 includes a ramp up time period 424 during which the second execution profile 420 transitions from using substantially no amount of the resource of the device to using some amount of the resource of the device” [Cudak Col. 13 Lines 18-22 Fig. 4B Examiner notes that figure 4B depicts a profile with a ramp up period 424 at the beginning of the workload which is further illuminated by the preceding pre-execution time period 422].
Cudak is considered to be analogous to the claimed invention because it is in the same field of allocation of processing resources. It would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Malaya in view of Zhang to incorporate the teachings of Cudak and include that the one or more load profiles comprises a ramp-up load profile applied at a beginning of the workload. Doing so would allow for further detail in evaluations of system utilization. “The apparatus includes a comparison module that compares an execution profile of each job of the multiple jobs with a resource of a device of the computer system. The execution profile of each job includes an amount of a resource of a device used by the respective job over time” [Cudak Col. 1 Lines 29-32].
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Malaya (US 2022/0318056 A1) in view of Zhang (US 2023/0353049 A1) in view of Hansen (US 2023/0120165 A1).
Regarding Claim 19, Malaya in view of Zhang teaches the GPU of claim 16, as referenced above. Malaya further teaches wherein the information is based on a maximum power swing “These system-wide power swings (which can be on the magnitude of megawatts power over the course of a few seconds of time or fractions of a second) resulting from rapid changes in power demand risk damaging local power transformers, system circuitry, and also up-stream power transformers and generators” [Malaya ¶ 7]. “For example, in some embodiments, the GPU 202 includes a microcontroller 210 such as a system management unit (SMU) that is configured for enforcing numerous protection mechanisms (e.g., chip-wide and device block thermal constraints, di/dt (rate of change of the charge current (i) over time (t)) limits, voltage droop mitigation, etc.), in addition to performing a plethora of dynamic performance optimizations” [Malaya ¶ 16].
Malaya in view of Zhang fails to teach wherein the information is based on a maximum power swing of a power provider.
However, Hansen teaches wherein the information is based on a maximum power swing of a power provider. “Ramp rate in this context may be defined as the change in power output of a RES facility or RES-BESS facility (e.g., PV +S facility) in a given time interval (e.g., change per minute or change per hour)” [Hansen ¶ 162 Examiner notes this description of ramp rate is in accordance with the description of power swing given in ¶ 42 of the specification]. “If the plant production is less than the current RES production, then curtailment may be applied to make sure that the RES plant output does not violate the ramp limit… Firstly, if there is a sudden increase in RES production, this logic will control plant production so that total output increases in steps of power that are less than equal to the ramp rate up limit (maximum power swing)” [Hansen ¶ 163].
Hansen is considered to be analogous to the claimed invention because it is in the same field of system power control and allocation. While Hansen focuses on control of a power generating plant, the maximum power swing of a power provider can be applied to the management information of the processors of Malaya because both systems seek to account for power constraints in their control signals. Therefore, it would be obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Malaya in view of Zhang to incorporate the teachings of Hansen and include that the information is based on a maximum power swing of a power provider. Doing so would allow for system consideration of both the cost and operating parameters of the power source. “In some embodiments, assigning the score to each of the plurality of control algorithms comprises calculating the score for each of the plurality of control algorithms based on one or more variables associated with (i) one or more operating parameters of the power plant and/or (ii) energy market prices” [Hansen ¶ 6].
Response to Arguments
Applicant's arguments filed 06/08/26 have been fully considered but they are not persuasive. Applicant argues in substance:
I. The cited art does not disclose or suggest claim 1. Malaya is directed to power management for processing workloads and describes running power burn kernels to raise consumed power. Because Malaya uses software kernels to burn power, it may be said that Malaya's power management is software-based. By contrast, the amendments to claim 1 further emphasize the hardware-based nature of the claimed invention by reciting a step to "dynamically adjust the load profile by operating an on-die current sink circuit independently of the one or more processing devices executing software instructions to" draw current and gradually reduce the drawn current as claimed. Malaya does not disclose or suggest such features because Malaya's compute units run dummy software kernels, and thus, the compute units cannot operate an on-die current sink independently of executing software instructions as claimed. Moreover, the hardware-based nature of the claimed invention enables a fast response time to power fluctuations (e.g., less than 1ms) and avoids the costs associated with modifications to datacenter infrastructure and/or over-provisioning of protection circuits normally used to achieve the same purpose.
Karnik does not remedy the deficiencies of Malaya. Firstly, substituting Karnik's hardware testing circuit into Malaya is improper because it would defeat Malaya's principle of operation … The claimed on-die current sink circuit operates independently of the processing device executing software instructions to draw the current, ensuring guaranteed power smoothing without reliance on vulnerable software schedulers. Karnik provides no teaching or motivation to bridge this fundamental architectural gap.
Secondly, Applicant submits that Karnik is not analogous art … Given these differences, one of ordinary skill in the art would not consider Karnik's programmable current sinks for testing small IC devices to be in the same field of endeavor as the claimed invention which involves high performance, high power consumption processing devices operating in a bulk-synchronous mode to process a workload.
Thirdly, even Karnik is analogous art, which Applicant does not concede, Karnik does not remedy the deficiencies of Malaya noted above. For example, Karnik does not disclose or suggest "dynamically adjust[ing] the load profile by operating an on-die current sink circuit independently of the one or more processing devices executing software instructions to" draw current and gradually reduce the drawn current, as claimed.
Because Malaya and Karnik, taken alone or in combination, do not disclose or suggest each and every feature of claim 1, these documents do not anticipate or render obvious claim 1. The other cited references have not been relied upon to remedy the deficiencies of Malaya and Karnik and do not appear to do so. Accordingly, claim 1 and its associated dependent claims are patentable over the cited art. Claims 9 and 15 include features similar to those discussed above with respect to claim 1. Thus, claims 9 and 15 and their associated dependent claims are patentable over the cited art for at least the same reasons as those discussed above with respect to claim 1.
Examiner respectfully disagrees. Paragraph 39 of the instant specification states:
“Additionally or alternatively, a current sink circuit 212 may comprise one or more circuits that enable a GPU 202 to process an additional workload as part of applying the ramp-down load profile to the GPU 202 … In this case, a current sink circuit 212 may enable or be embodied by GPU processor(s) 224 running a preset algorithm or processing predefined data in a manner that causes power consumed by a GPU 202 to match an associated ramp-down load profile.”
Malaya teaches draw current to raise the power consumed by the one or more processing devices to the first power threshold [Malaya ¶ 30, 38, and claim 5] and gradually reduce the drawn current to cause a corresponding reduction in the power consumed by the one or more processing devices to gradually drop from the first power threshold [Malaya ¶ 24]. Malaya further states: “In this manner, the processor device itself smooths out potentially damaging high frequency variations in power use by leveraging existing processor hardware structures, without additional circuitry design changes, and without changes to the structure of productive workloads” [Malaya ¶ 8].
Applicant’s further arguments with respect to claim(s) 1, 9, and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The arguments have been considered but were not found to be persuasive.
II. Claim 2 is further patentable for these additional reasons. The rejection of claim 2 alleges that Malaya teaches beginning to adjust a load profile in response to exceeding a threshold by disclosing a step of identifying a power dip when a rate of power change exceeds a threshold. However, identifying the power dip is associated with a ramp-down operation, not a ramp-up operation as in claim 2.
Examiner respectfully disagrees. As detailed in the rejection above, Malaya is not relied upon to teach the argued limitations of claim 2. Instead, these limitations are taught through a combination with the cited prior arts of Whatmough and Ernewein. The arguments have been considered but were not found to be persuasive.
III. Claims 6 and 8 are further patentable at least because the cited art has not been shown to disclose or suggest the features added to this claim.
Examiner respectfully disagrees. As detailed in the rejection above, Malaya teaches the limitation of claim 6 of: wherein an amount of time between the power consumed dropping below the first power threshold before being raised back to the first power threshold by the drawn current is less than 1ms [Malaya ¶ 35, 44]. Further, Malaya teaches the limitation of claim 8 of: wherein the one or more processing devices comprise a plurality of Graphics Processing Units (GPUs), [Malaya ¶ 10]. And Wang teaches the limitation of claim 8 of: and wherein the one or more circuits comprise a Baseboard Management Controller. [Wang ¶ 24]. The arguments have been considered but were not found to be persuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Examiner respectfully requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist Examiner in prosecuting the application.
When responding to this Office Action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 CFR 1.111(c).
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/A.F.R./Examiner, Art Unit 2197
/BRADLEY A TEETS/Supervisory Patent Examiner, Art Unit 2197
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