DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s amendments to the claims 1 – 5, 7, 9, 10, 12 and the newly added claims 22 – 29 have been fully considered. Applicant argues the amended claim 1 is not disclosed by the prior art cited Lilak. Examiner respectfully disagrees. The current interpretation of Lilak references discloses all of the currently claimed elements, in particular “wherein the first surface is in direct contact with a bottom surface of at least one of the gate structure.” Please see rejection of claims 1 – 6 and 29 below.
Response to Amendment
Applicant’s amendments to the drawings, filed on 11/26/2025 have been fully considered and resolve the informalities. The objection to the drawing has been withdrawn.
Applicant’s cancellation of claim 18, filed on 11/26/2025 has been fully considered and resolve the informalities of the claim objection. The claim objection has been withdrawn.
Applicant’s amendments to the claims 1 - 5, 7, 9, 10, and 12, filed on 11/26/2025 have been fully considered and examined.
Applicant’s newly added claims 22 – 29, filed on 11/26/2025 has been fully considered and examined.
Applicant’s cancellation of claims 11 and 15-21, filed on 11/26/2025 has been acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 28 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lilak et al. (US20200294998A1; hereinafter Lilak).
Regarding Amended Claim 1, Lilak discloses an integrated circuit (IC) device [0010], comprising
a gate-all-around transistor (transistors in device region 104, 108) comprising a gate structure (gate structure includes gate electrode 120A and gate dielectrics 122A) between a source (124A, 124B) and a drain (124A, 124B), [0008], [0013], FIG. 1A reproduced below;
a gate contact (frontside contact region 105 contacting the gate electrode 120), a source contact, and a drain contact (frontside contacts 125 of the source or drain) on top surfaces of the gate structure, the source, and the drain, respectively, FIG. 1A, [0013];
a probe point structure (929) consisting of a first surface and a plurality of second surfaces, wherein the first surface is in direct contact with a bottom surface of at least one of the gate structure (gate structure includes gate electrode 120A and gate dielectrics 122A), FIG. 9C reproduced below,
Lilak (FIG. 9C, [0061]) discloses the interconnect 929 is connected to the bottom surface of the gate structure (gate electrode 120A and gate dielectrics 122A) and consists of a plurality of second surfaces including etch material 140, 136 and spacers 126, indicating 929 functions as a probe point structure.
one or more dielectric materials, wherein the one dielectric material (126) is in direct contact with the second surfaces (side surfaces of 929), FIG. 9C, [0061].
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Lilak: FIG. 1A
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Lilak: FIG. 9C
Regarding Claim 29, Lilak discloses the integrated circuit (IC) device of claim 1.
Lilak discloses: further comprising: a power supply (battery) coupled to the gate-all-around transistor, [0063]. Lilak discloses an example computing system 1000 implemented with IC structure including gate-all-around transistor, wherein the computing system includes components such as a battery.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 - 6 are rejected under 35 U.S.C. 103 as being unpatentable over Lilak in view of Suthar (US20040232414A1; hereinafter Suthar).
Regarding Amended Claim 2, Lilak discloses the IC device of claim 1, further comprising:
a second probe point structure in contact with a bottom surface of a second gate-all-around transistor; a third probe point structure in contact with a bottom surface of a third gate-all-around transistor; Lilak (FIG. 1A, [0013]) discloses multiple gate-all-around transistors in the upper device region 108 and lower device region 104; and [0061] discloses a probe point structure 929, indicating a second probe point structure is in contact with a bottom surface of a second gate-all-around transistor; a third probe point structure in contact with a bottom surface of a third gate-all-around transistor.
Lilak does not disclose “a wire in direct contact with the second probe point structure and the third probe point structure.”
In a similar device, Suthar discloses: an integrated circuit with a wire (241) in direct contact with the second probe point structure (202) and the third probe point structure (204), FIG. 4 reproduced below, [0018]. Suthar (FIG. 3, [0017]) discloses vias 215, 219 are formed through the connection targets 202, 204 to the signal lines 217 and 221, indicating 202 and 204 function as probe structures. Suthar [0018] discloses a conductor 241 is coupled to 202 and 204, indicating the wire 241 is in direct contact with the second probe point structure and the third probe point structure.
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Suthar: FIG. 4
Suthar discloses that a device as taught enables easier verification of design engineering change orders [0001]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Lilak’s device, in order to provide a device that enables easier verification of design engineering change orders [0001] as taught by Suthar.
Regarding Amended Claim 3, The combination of Lilak and Suthar disclose the IC device of claim 2.
Lilak discloses: further comprising:
a front side metallization layer over the gate contact, the source contact, and the drain contact (a frontside contact region 105 can be applied to the frontside 101 of the structure, which may include local contacts and/or interconnects, along with one or more interconnect or metallization layers e.g., metal layers M1-MN, shown in dashed lines in FIGS. 1A,1B, [0013]); and
a back side metallization layer under the bottom surfaces of the gate, the source, and the drain ( [0058], FIGS. 9A-D collectively illustrate the formation of interconnects 968A and 968B e.g., vias and metal lines, thus forming backside contact region 103);
wherein the probe point structure is electrically isolated from the front and back side metallization layers. Lilak [0061] discloses that 929 is conductive and includes liners or barriers to prevent electromigration of the conductive material into the neighboring dielectric materials indicating the probe point structure is electrically isolated from the front and back side metallization layers.
Regarding Amended Claim 4, The combination of Lilak and Suthar disclose the IC device of claim 3.
Lilak further discloses: the back side metallization layer comprises a second metal composition FIG. 9C, [0061]. Lilak discloses copper, aluminum, silver, gold, tungsten, and tantalum nitride as a part of backside metallization 103.
Lilak does not disclose: “wherein the wire comprises a first metal composition.”
Suthar further discloses: wherein the wire (241) comprises a first metal composition (any metal, including metals having tungsten, platinum, or other organo-metallics, such as gold, copper, or silver-based compounds, [0018]).
Suthar discloses that a device as taught improves process throughput and reliability [0022]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Lilak’s device, in order to provide a device with improved process throughput and reliability [0022] as taught by Suthar.
Regarding Amended Claim 5, The combination of Lilak and Suthar discloses the IC device of claim 3.
Lilak discloses: wherein an entirety of the back side metallization layer (103) is under the probe point structure (929), FIG. 9C, [0061].
Regarding Claim 6, The combination of Lilak and Suthar disclose the IC device of claim 5.
Lilak discloses: wherein the front side metallization layer (105) is coupled to the back side metallization layer (103) by a via (968A,968B), [0059].
Allowable Subject Matter
Claims 7 and 23 are allowed. The following is a statement of reasons for the indication of allowable subject matter:
Regarding Amended Claim 7, the prior art does not disclose “exposing a back side surface of at least one of the gate structure, the source, or the drain; exposing, by removing a portion of the device layer, a metallization feature of the front side metallization layer” in combination with the remaining claimed features.
Regarding New Claim 23, the prior art does not disclose “wherein a first die comprises the IC structure and the first die is mounted to a second die; exposing a back side surface of at least one of the gate structure, the source, or the drain by removing a portion of the second die to expose the first die and removing a portion of the back side metallization layer to expose the back side surface of at least one of the gate structure, the source, or the drain” in combination with the remaining claimed features.
Claims 8 - 10, 12 - 14, 22, and 24 - 28 are allowed due to the virtue of their dependency on the allowed based claims.
Conclusion
Applicant’s amendment necessitated the new grounds of rejection presented in
this Office Action. Accordingly, THIS ACTION IS MADE FINAL. Applicant is reminded
of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE
MONTHS from the mailing date of this action. In the event a first reply is filed within
TWO MONTHS of the mailing date of this final action and the advisory action is not
mailed until after the end of the THREE-MONTH shortened statutory period, then the
shortened statutory period will expire on the date the advisory action is mailed, and any
nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be
calculated from the mailing date of the advisory action. In no event, however, will the
statutory period for reply expire later than SIX MONTHS from the mailing date of this
final action.
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to Krishna J Palaniswamy whose telephone number
is (571)272-6239. The examiner can normally be reached Monday - Friday 8:30AM -
5PM EST.
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conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s
supervisor, Brent Fairbanks can be reached on 408-918-7532. The fax phone number
for the organization where this application or proceeding is assigned is 571-483-7639.
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/Krishna J Palaniswamy/
Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899