Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendments filed 3/2/2026 have been entered and considered. The amendments to claims 1, 7, 16, and 18 are acknowledged.
The examiner agrees the amendments to claims 7 and 18 overcome the rejections under 35 U.S.C. 112, such that the rejections are withdrawn.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 7-9, and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Baba US 6369443 B1 (hereinafter referred to as Baba), in view of Baks et al. US 20180159203 A1 (hereinafter referred to as Baks).
Regarding claim 1, Baba teaches
A substrate (“BGA substrate 1” col 3 lines 25-26 FIG. 2) comprising:
a first metallization stack (first group of traces in “BGA substrate 1” as shown in annotated FIG. 2. The examiner understands that the “stacked vias 10” terminate at traces shown as the black lines in “BGA substrate 1”.);
a second metallization stack (second group of traces in “BGA substrate 1” as shown in annotated FIG. 2);
a hardware interface (interface between “semiconductor chip 2” and the second stack where “bumps 3” are disposed, col 3 lines 26-28) at a side of the second metallization stack;
a first interconnect comprising a first via portion (first “stacked via 10” as shown in annotated FIG. 2, col 3 line 38) and a first trace portion (trace to which first “stacked via 10” connects), wherein the first trace portion extends from the first via portion in a first routing layer of the first metallization stack (the trace extends along a layer in the first stack portion of “BGA substrate 1”), and the first via portion extends from the hardware interface, through the second metallization stack, to the first routing layer (first “stacked via 10” extends from under the “bumps 3” to the trace through the second stack of “BGA substrate 1”); and
a second interconnect adjacent to the first interconnect and a first trace portion (second “stacked via 10” and second trace to which second “stacked via 10” connects as shown in annotated FIG. 2 adjacent to the first “stacked via 10” and first trace), the second interconnect comprising a second via portion (second “stacked via 10”) and a second trace portion (second trace), wherein the second trace portion extends from the second via portion in the first routing layer (second trace is shown to extend along the layer in the first stack portion of “BGA substrate 1” where the first trace extends), and the second via portion extends from the hardware interface, through the second metallization stack, to the first routing layer (second “stacked via 10” extends from under the “bumps 3” to the trace through the second stack of “BGA substrate 1”).
However, Baba fails to teach a core structure between the first metallization stack and the second metallization stack; the first via portion extends from the hardware interface, through both the second metallization stack and the core structure, to the first routing layer; the second via portion extends from the hardware interface, through both the second metallization stack and the core structure, to the first routing layer.
Nevertheless, Baks teaches
a core structure (“central core layer 120”, para. 0014 FIG. 1) between the first metallization stack (“interface layer 130” para. 0014) and the second metallization stack (“antenna layer 140” para. 0017).
Baba and Baks teach substrates comprising metallization stacks. The “package substrate 110” comprises “interface layer 130” and “antenna layer 140” aa metallization stacks on opposite sides of the “central core structure 120”. The “central core structure 120” includes a “substrate layer 122” made of material that provides structural support (para. 0017). Furthermore, Baks teaches “antenna feed lines 112 and 114” that extend through the second metallization stack “antenna layer 140”, through the “central core layer 120”, to the first metallization stack “interface layer 130” (para. 0021). These “antenna feed lines 112 and 114” are analogous to the “stacked vias 10” in Baba. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that including “central core layer 120” between the first and second metallization stacks may improve the structural stability of the substrate. “Stacked vias 10” can be made to extend through the “central core layer 120” such as portions of “antenna feed lines 112 and 114” do.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate in Baba with the core structure in Baks. The core structure improves the mechanical stability of the substrate.
Regarding claim 2, Baba, modified by Baks, teaches the substrate of claim 1, wherein the first metallization stack forms a first multi-layer insulator structure (MLIS) (first stack in “BGA substrate 1” comprises stacked organic insulation layers, col 3 lines 39-40. The layers formed above the traces can be considered the first MLIS) which adjoins respective first sides of the first trace portion and the second trace portion (since the first and second trace are understood to be formed at a same level, it is understood an organic insulation layer formed over both traces contacts both upper surfaces of the traces).
Regarding claim 3, Baba, modified by Baks, teaches the substrate of claim 2, wherein the first metallization stack further forms a second MLIS (first stack in “BGA substrate 1” comprises stacked organic insulation layers. The layers formed below the traces can be considered the second MLIS) which adjoins respective second sides of the first trace portion and the second trace portion (since the first and second trace are understood to be formed at a same level, it is understood they are disposed above an organic insulation layer in contact both lower surfaces of the traces).
Regarding claim 7, Baba, modified by Baks, teaches the substrate of claim 1, wherein a third interconnect comprises a third via portion (a third “stacked via 10” in the second stack as shown in annotated FIG. 2) and a third trace portion (trace portion connected to the third “stacked via 10”), wherein the third trace portion extends from the third via portion in a second routing layer of the second metallization stack (the trace connected to the third “stacked via 10” extends along a layer in the second stack of “BGA substrate 1”), and the third via portion extends from the hardware interface to the second routing layer (third “stacked via 10” extends from “bump 3 to the trace in the “BGA substrate 1” layer);
wherein a fourth interconnect of the substrate comprises both a fourth via portion (a fourth “stacked via 10” in the second stack as shown in annotated FIG. 2) and a fourth trace portion (trace portion connected to the fourth “stacked via 10”), wherein the fourth trace portion extends from the fourth via portion in the second routing layer (the trace connected to the third “stacked via 10” extends along a layer in the second stack of “BGA substrate 1”), and the fourth via portion extends from the hardware interface to the second routing layer (fourth “stacked via 10” extends from “bump 3 to the trace in the “BGA substrate 1” layer); and
wherein the second metallization stack forms a second MLIS (second stack in “BGA substrate 1” comprises stacked organic insulation layers, col 3 lines 39-40. The layers formed above the traces can be considered the second MLIS) which adjoins respective second sides of the third trace portion and the fourth trace portion (since the third and fourth trace are understood to be formed at a same level, it is understood an organic insulation layer formed over both traces contacts both upper surfaces of the traces).
Regarding claim 8, Baba, modified by Baks, teaches the substrate of claim 7, wherein the second metallization stack further forms a third MLIS (second stack in “BGA substrate 1” comprises stacked organic insulation layers. The layers formed below the traces can be considered the third MLIS) which adjoins respective third sides of the third trace portion and the fourth trace portion (since the third and fourth trace are understood to be formed at a same level, it is understood they are disposed above an organic insulation layer in contact both lower surfaces of the traces).
Regarding claim 9, Baba, modified by Baks, teaches the substrate of claim 7 but fails to expressly teach wherein a length of the third trace portion in the second routing layer is greater than a length of the first trace portion in the first routing layer.
Nevertheless, the examiner notes there are three possible alternatives regarding the lengths of the first and third trace portions: the first trace portion is longer, the third trace portion is longer, or they are both the same length. The length of a trace portion will depend on the routing of a signal across both sides of the “BGA substrate 1”; the vertical offset between a “bump 3” and a “solder ball 9” that are interconnected can be different based on the desired routing path. Though no lengths are given for the traces, FIG. 2 does show examples of traces with different lengths. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that there was a finite number of possible arrangements regarding the lengths of the traces. The third trace can have a greater length than the first trace based on a desired routing of the signals.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that there was a finite number of possible solutions for the relationship between the lengths of the first and third trace portions. Whether the first trace portion of the third trace portion is longer is a matter of design choice. As stated in MPEP 2143 Section E, “"a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense”.
Regarding claim 14, Baba, modified by Baks, teaches the substrate of claim 1, wherein the first via portion and the second via portion each extend to the first routing layer in a direction substantially orthogonal to the side (“stacked vias 10” pass through “BGA substrate 1” layers in what appears to be a substantially vertical direction, orthogonal to the top surface).
Regarding claim 15, Baba, modified by Baks, teaches the substrate of claim 1, wherein the first trace portion includes an angle measuring other than 45 degrees (the trace connected to the first “stacked via 10” extends in a substantially horizontal direction along the layer in “BGA substrate 1”. The angle between the “stacked via 10” and the trace is understood to be around 90 degrees).
Regarding claim 13, Baba, modified by Baks, teaches the substrate of claim 1, wherein:
the hardware interface is a first hardware interface (interface with “bumps 3” can be considered a first hardware interface);
the substrate further comprises a second hardware interface at another side of the first metallization stack (lower side of “BGA substrate 1” with “solder balls 9” can be considered a second hardware interface);
However, Baba, modified by Baks, fails to expressly teach the first interconnect further comprises a third via portion which extends to the second hardware interface; and the second interconnect further comprises a fourth via portion which extends to the second hardware interface.
Nevertheless, other “stacked vias 10” in Baba connect to traces in “BGA substrate 1” that are also connected to what appear to be vias. The vias extend down to and are understood to connect with “solder balls 9”. Similarly, the “first and second antenna feed lines 112 and 114” in Baks include stacked vias connected to traces “horizontal stripline structure 112-1” and “horizontal microstrip structure 114-1” in the “antenna layer 140” and stacked vias “vertical portions 112-3 and 114-3” extending down to the lower surface of “interface layer 130 (para. 0026-0031). As seen in Baba, and Baks, at least some interconnects route signals from the upper end of the second metallization stack with the first hardware interface to the lower surface of the first metallization stack with the second hardware interface. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that third and fourth via portions can extend from the first and second traces in “BGA substrate 1” to route signals from “semiconductor chip 2” to corresponding “solder balls 9”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the substrate taught between Baba and Baks. Signals from the first hardware interface can be sent to the second hardware interface through the first interconnect and second interconnect by use of a third via connected to the first trace and a fourth via connected to the second trace.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Baba, modified by Baks, as applied to claim 1 above, in view of Sundaram et al. US 20130119555 A1 (hereinafter referred to as Sundaram).
Baba, modified by Baks, teaches the substrate of claim 1 but fails to teach wherein the core structure comprises a glass material.
Nevertheless, Sundaram teaches
wherein the core structure ("interposer 108" para. 0045 FIG. 1) comprises a glass material ("interposer 108" comprises glass, para. 0045).
Baba, modified by Baks, and Sundaram teach core materials between stacks of metallization patterns. The material of “substrate layer 122” in “central core layer 120” can be RF4 material or any other material that provides rigidity and support (Baba para. 0017). Sundaram teaches the use of glass due to its dimensional and thermal stability, electrical properties, and is relatively available in large panel sizes (Sundaram para. 0041 and Table 1). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that glass is a material suitable for use as a core layer of a substrate for its thermal, electrical, and structural properties.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate taught between Baba and Baks with the glass core structure in Sundaram. Glass is a strong insulator with good thermal and physical stability.
Claims 5-6 and 10 are rejected under 35 U.S.C. 103 as being unpatentable Baba, modified by Baks, as applied to claim 1 above, in view of Kim et al. US 20200375024 A1 (hereinafter referred to as Kim).
Regarding claim 5, Baba, modified by Baks, teaches the substrate of claim 1, wherein the hardware interface is to couple the substrate to an integrated circuit (IC) die (“bumps 3” bond “BGA substrate 1” to “semiconductor chip 2”, col 3 lines 27-28).
However, Baba, modified by Baks, fails to teach wherein the first interconnect and the second interconnect are to communicate with the IC die different respective signals of a differential signal pair.
Nevertheless, Kim teaches differential pairs comprising pad portions, via portions and trace portions in a PCB (para. 0035 and 0039 FIG. 3-4). “Differential pair vias 301” extend through “PCB” and connect to “first signal trace 401” (para. 0039 FIG. 4). The upper pads on “differential pair vias 301” are coupled to a connected integrated chip (para. 0039). Differential pair signaling is used for high-speed data transmission with reduced crosstalk and electromagnetic interference, as evidenced in Chandra et al. US 20190239339 A1 para. 0003. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the adjacent “stacked vias 10” in Baba can act as differential pairs to transmit high speed signals between the “semiconductor chip 2” and “BGA substrate 1”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate taught between Baba and Baks with the differential signal pair in Kim. Adjacent vias and traces can be a differential pair to send data at high speed with minimized crosstalk and electromagnetic interference.
Regarding claim 6, Baba, modified by Baks, teaches the substrate of claim 5, wherein the IC die comprises at least one of serializer circuitry or deserializer circuitry.
Nevertheless, Asl teaches that serializer/deserializer devices are typically implemented as an IC chip that is mounted on a PCB (para. 0025). Serializer/deserializer devices are high speed communications devices that convert data between serial data and parallel interfaces in each direction that provide data transmission over a single line or a differential pair in order to minimize the number of I/O pins and interconnects needed to communicate between computing devices that are spaced apart from one another (para. 0025). The “semiconductor chip 2” in Baba is unspecified. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the “semiconductor chip 2” can be a serializer/deserializer device that converts data for transmission through a differential pair.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate taught between Baba and Baks with the IC die in Asl. A serializer/deserializer chip processes the signals sent through the differential signal pair.
Regarding claim 10, Baba, modified by Baks, teaches the substrate of claim 7, wherein the hardware interface is to couple the substrate to an integrated circuit (IC) die (“bumps 3” bond “BGA substrate 1” to “semiconductor chip 2”, col 3 lines 27-28).
However, Baba, modified by Baks, fails to teach wherein the third interconnect and the fourth interconnect are to communicate with the IC die different respective signals of a differential signal pair.
Nevertheless, Kim teaches differential pairs comprising pad portions, via portions and trace portions in a PCB (para. 0035 and 0039 FIG. 3-4). “Differential pair vias 301” extend through “PCB” and connect to “first signal trace 401” (para. 0039 FIG. 4). The upper pads on “differential pair vias 301” are coupled to a connected integrated chip (para. 0039). Differential pair signaling is used for high-speed data transmission with reduced crosstalk and electromagnetic interference, as evidenced in Chandra et al. US 20190239339 A1 para. 0003. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the adjacent third and fourth “stacked vias 10” and corresponding traces in Baba can act as differential pairs to transmit high speed signals between the “semiconductor chip 2” and “BGA substrate 1”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate taught between Baba and Baks with the differential signal pair in Kim. Adjacent vias and traces can be a differential pair to send data at high speed with minimized crosstalk and electromagnetic interference.
Claims 16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Baba, in view of Baks.
Regarding claim 16, Baba teaches
An IC device (semiconductor device according to a embodiment 1” col 3 lines 23-24 FIG. 2), comprising:
a substrate (“BGA substrate 1” col 3 lines 25-26 FIG. 2) comprising:
a first metallization stack (first group of traces in “BGA substrate 1” as shown in annotated FIG. 2. The examiner understands that the “stacked vias 10” terminate at traces shown as the black lines in “BGA substrate 1”.) and a second metallization stack (second group of traces in “BGA substrate 1” as shown in annotated FIG. 2), wherein each of the first metallization stack and second metallization stack comprise a plurality of routing layers separated by a plurality of dielectric layers (“BGA substrate 1” comprises stacked organic insulation layers, col 3 lines 39-40. The examiner understands that the traces are shown as the black lines between each dielectric layer of “BGA substrate 1”.);
a hardware interface at a side of the second metallization stack (interface between “semiconductor chip 2” and the second stack where “bumps 3” are disposed, col 3 lines 26-28);
a first interconnect comprising a first via portion (first “stacked via 10” as shown in annotated FIG. 2, col 3 line 38), and a first trace portion (trace to which first “stacked via 10” connects) which extends from the first via portion in a first routing layer of the first metallization stack (the trace extends along a layer in the first stack portion of “BGA substrate 1”), wherein the first via portion extends from the hardware interface, through the second metallization stack, to the first routing layer (first “stacked via 10” extends from under the “bumps 3” to the trace through the second stack of “BGA substrate 1”);
a second interconnect comprising a second via portion (second “stacked via 10” as shown in annotated FIG. 2 adjacent to the first “stacked via 10), and a second trace portion (second trace to which second “stacked via 10” connects) which extends from the second via portion in the first routing layer (second trace is shown to extend along the layer in the first stack portion of “BGA substrate 1” where the first trace extends), wherein the second via portion extends from the hardware interface, through both the second metallization stack and the core structure, to the first routing layer (second “stacked via 10” extends from under the “bumps 3” to the trace through the second stack of “BGA substrate 1”); and
an integrated circuit (IC) die (“semiconductor chip 2”) coupled with the hardware interface.
However, Baba fails to teach a core structure between the first metallization stack and the second metallization stack; the first via portion extends from the hardware interface, through both the second metallization stack and the core structure, to the first routing layer; the second via portion extends from the hardware interface, through both the second metallization stack and the core structure, to the first routing layer.
Nevertheless, Baks teaches
a core structure (“central core layer 120”, para. 0014 FIG. 1) between the first metallization stack (“interface layer 130” para. 0014) and the second metallization stack (“antenna layer 140” para. 0017).
Baba and Baks teach substrates comprising metallization stacks. The “package substrate 110” comprises “interface layer 130” and “antenna layer 140” aa metallization stacks on opposite sides of the “central core structure 120”. The “central core structure 120” includes a “substrate layer 122” made of material that provides structural support (para. 0017). Furthermore, Baks teaches “antenna feed lines 112 and 114” that extend through the second metallization stack “antenna layer 140”, through the “central core layer 120”, to the first metallization stack “interface layer 130” (para. 0021). These “antenna feed lines 112 and 114” are analogous to the “stacked vias 10” in Baba. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that including “central core layer 120” between the first and second metallization stacks may improve the structural stability of the substrate. “Stacked vias 10” can be made to extend through the “central core layer 120” such as portions of “antenna feed lines 112 and 114” do.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate in Baba with the core structure in Baks. The core structure improves the mechanical stability of the substrate.
Regarding claim 18, Baba, modified by Baks, teaches the IC device of claim 16, wherein the substrate further comprises:
a third interconnect comprising a third via portion (a third “stacked via 10” in the second stack as shown in annotated FIG. 2) and a third trace portion (trace portion connected to the third “stacked via 10”), wherein the third trace portion extends from the third via portion in a second routing layer of the second metallization stack (the trace connected to the third “stacked via 10” extends along a layer in the second stack of “BGA substrate 1”), and the third via portion extends from the hardware interface to the second routing layer (third “stacked via 10” extends from “bump 3 to the trace in the “BGA substrate 1” layer);
a fourth interconnect comprising a fourth via portion (a fourth “stacked via 10” in the second stack as shown in annotated FIG. 2) and a fourth trace portion (trace portion connected to the fourth “stacked via 10”), wherein the fourth trace portion extends from the fourth via portion in the second routing layer, (the trace connected to the third “stacked via 10” extends along a layer in the second stack of “BGA substrate 1”), and the fourth via portion extends from the hardware interface to the second routing layer (fourth “stacked via 10” extends from “bump 3 to the trace in the “BGA substrate 1” layer); and
wherein the second metallization stack forms a second MLIS (second stack in “BGA substrate 1” comprises stacked organic insulation layers, col 3 lines 39-40. The layers formed above the traces can be considered the second MLIS) which adjoins respective second sides of the third trace portion and the fourth trace portion (since the third and fourth trace are understood to be formed at a same level, it is understood an organic insulation layer formed over both traces contacts both upper surfaces of the traces).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Baba, modified by Baks, as applied to claim 16 above, in view of Sundaram et al. US 20130119555 A1 (hereinafter referred to as Sundaram).
Baba, modified by Baks, teaches the substrate of claim 1 but fails to teach wherein the core structure comprises a glass material.
Nevertheless, Sundaram teaches
wherein the core structure ("interposer 108" para. 0045 FIG. 1) comprises a glass material ("interposer 108" comprises glass, para. 0045).
Baba, modified by Baks, and Sundaram teach core materials between stacks of metallization patterns. The material of “substrate layer 122” in “central core layer 120” can be RF4 material or any other material that provides rigidity and support (Baba para. 0017). Sundaram teaches the use of glass due to its dimensional and thermal stability, electrical properties, and is relatively available in large panel sizes (Sundaram para. 0041 and Table 1). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that glass is a material suitable for use as a core layer of a substrate for its thermal, electrical, and structural properties.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate taught between Baba and Baks with the glass core structure in Sundaram. Glass is a strong insulator with good thermal and physical stability.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kusano et al. US 20210249344 A1 (hereinafter referred to as Kusano), in view of Baba, in view of Baks.
Regarding claim 19, Kusano teaches
A system (“circuit module 80” para. 0048 FIG. 9) comprising:
a system board (“system board 30” para. 0048) and a power supply (“power supply chip module 10”, para. 0048) coupled with the system board;
an integrated circuit device (“load semiconductor chip 22” in “load chip module 20”, para. 0031 and 0048, FIG. 4-5) coupled with the system board and to receive power from the power supply (“load chip module 20” receives power from “power supply chip module 10”, para. 0048); and
a substrate coupled with the IC device (as shown in FIG 4-5, “load chip module 20” comprises at least one “load semiconductor chip 22” on a “load chip module board 21”
However, Kusano fails to teach the substrate comprising: a core structure between a first metallization stack and a second metallization stack; a hardware interface at a side of the second metallization stack; a first interconnect comprising a first via portion, and a first trace portion which extends from the first via portion in a first routing layer of the first metallization stack, wherein the first via portion extends from the hardware interface, through both the second metallization stack and the core structure, to the first routing layer; and a second interconnect comprising a second via portion, and a second trace portion which extends from the second via portion in the first routing layer, wherein the second via portion extends from the hardware interface, through both the second metallization stack and the core structure, to the first routing layer.
Nevertheless, Baba teaches
the substrate (“BGA substrate 1” col 3 lines 25-26 FIG. 2) comprising:
a first metallization stack (first group of traces in “BGA substrate 1” as shown in annotated FIG. 2. The examiner understands that the “stacked vias 10” terminate at traces shown as the black lines in “BGA substrate 1”.) and a second metallization stack (second group of traces in “BGA substrate 1” as shown in annotated FIG. 2);
a hardware interface at a side of the second metallization stack (interface between “semiconductor chip 2” and the second stack where “bumps 3” are disposed, col 3 lines 26-28);
a first interconnect comprising a first via portion (first “stacked via 10” as shown in annotated FIG. 2, col 3 line 38), and a first trace portion (trace to which first “stacked via 10” connects) which extends from the first via portion in a first routing layer of the first metallization stack the trace extends along a layer in the first stack portion of “BGA substrate 1”), wherein the first via portion extends from the hardware interface, through the second metallization stack, to the first routing layer (first “stacked via 10” extends from under the “bumps 3” to the trace through the second stack of “BGA substrate 1”); and
a second interconnect comprising a second via portion (second “stacked via 10” as shown in annotated FIG. 2 adjacent to the first “stacked via 10), and a second trace portion (second trace to which second “stacked via 10” connects) which extends from the second via portion in the first routing layer (second trace is shown to extend along the layer in the first stack portion of “BGA substrate 1” where the first trace extends), wherein the second via portion extends from the hardware interface, through both the second metallization stack and the core structure, to the first routing layer (second “stacked via 10” extends from under the “bumps 3” to the trace through the second stack of “BGA substrate 1”).
Kusano and Baba teach packages comprising IC chips on substrates. The “BGA substrate 1” has high packaging reliability and maintains high power/ground plane characteristics and can be embodied inexpensively even when the device has a large number of terminals (col 2 lines 13-15). Reliability of the “solder balls 9” can be ensured by using an organic dielectric material of the “BGA substrate 1” with a coefficient of thermal expansion similar to that of a “system board” bonded to the “solder balls 9” (col 3 lines 39-41). The array arrangement of the “stacked vias10” enables “bumps 3” to be reliably arranged (col 3 lines 62-67 to col 4 lines 1-4). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the “BGA substrate 1” is a reliable structure with which signals between the IC chip and the system board can be routed.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system taught in Kusano with the substrate taught in Baba. The substrate has reliable hardware interfaces for routing signals between the IC chip and the system board.
However, Kusano, modified by Baba, fails to teach a core structure between the first metallization stack and the second metallization stack; the first via portion extends from the hardware interface, through both the second metallization stack and the core structure, to the first routing layer; the second via portion extends from the hardware interface, through both the second metallization stack and the core structure, to the first routing layer.
Nevertheless, Baks teaches
a core structure (“central core layer 120”, para. 0014 FIG. 1) between the first metallization stack (“interface layer 130” para. 0014) and the second metallization stack (“antenna layer 140” para. 0017).
Kusano, modified by Baba, and Baks teach substrates comprising metallization stacks. The “package substrate 110” comprises “interface layer 130” and “antenna layer 140” aa metallization stacks on opposite sides of the “central core structure 120”. The “central core structure 120” includes a “substrate layer 122” made of material that provides structural support (para. 0017). Furthermore, Baks teaches “antenna feed lines 112 and 114” that extend through the second metallization stack “antenna layer 140”, through the “central core layer 120”, to the first metallization stack “interface layer 130” (para. 0021). These “antenna feed lines 112 and 114” are analogous to the “stacked vias 10” in Baba. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that including “central core layer 120” between the first and second metallization stacks may improve the structural stability of the substrate. “Stacked vias 10” can be made to extend through the “central core layer 120” such as portions of “antenna feed lines 112 and 114” do.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate between Kusano and Baba with the core structure in Baks. The core structure improves the mechanical stability of the substrate.
Regarding claim 20, Kusano, modified by Baba and Baks, teaches the system of claim 19, wherein the first metallization stack forms a first multi-layer insulator structure (MLIS) (first stack in “BGA substrate 1” comprises stacked organic insulation layers, col 3 lines 39-40. The layers formed above the traces can be considered the first MLIS) which adjoins respective first sides of the first trace portion and the second trace portion (since the first and second trace are understood to be formed at a same level, it is understood an organic insulation layer formed over both traces contacts both upper surfaces of the traces) and a second MLIS (first stack in “BGA substrate 1” comprises stacked organic insulation layers. The layers formed below the traces can be considered the second MLIS) which adjoins respective second sides of the first trace portion and the second trace portion (since the first and second trace are understood to be formed at a same level, it is understood they are disposed above an organic insulation layer in contact both lower surfaces of the traces), and wherein the hardware interface is to couple the substrate to the IC die (“bumps 3” bond “BGA substrate 1” to “semiconductor chip 2”, col 3 lines 27-28), and wherein the first interconnect and the second interconnect are to communicate with the IC die different respective single-ended signals (the examiner understands that each “stacked via 10” and corresponding trace carry respective signals to the “semiconductor chip 2” that may be different).
Conclusion
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/ERIC MANUEL MULERO FLORES/ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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