DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicants' arguments involve discussing why the previously cited prior art documents fail to disclose the amended limitations. Examiner finds this argument persuasive and has brought in an additional reference to address the amended claim limitations. The applicability of the reference to the amended elements is discussed in the claim rejections below.
Regarding the objections to the specification, the amendments are sufficient and the objection of 1/27/2026 to the specification is hereby withdrawn.
Regarding the objections to the drawings, the replacement sheet is sufficient and the drawing objection of 1/27/2026 is hereby withdrawn.
Status of the Claims
Claims 1, 3-7, 9-12, and 23-34 are pending in the application and are currently being examined. Claims 1, 3-7, and 9-12 have been amended. Claims 2, 8, and 13-22 have been canceled. New claims 23-34 have been added.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/7/2026 is being considered by the examiner.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 3-5, 7, 10, 24-27, and 24-31 is/are rejected under 35 U.S.C. 103 as being anticipated by Gardner et al. (US 2023/0114024 A1, hereafter Gardner) in view of Thomas et al. (US 2021/0408257 A1, hereafter Thomas).
Regarding claim 1, Fig. 1B of Gardner teaches an apparatus, comprising:
a plurality of vertically aligned semiconductor structures (transistors 100A and 100B, [0041]. Note, Gardner teaches in [0042] that while not shown explicitly, that any number of transistors 100A and 100B can be repeated, making a stack of at least two transistors 100B on top of at least two transistors 100A, separated by the dielectric 105 as shown between each subsequent transistor);
a gate dielectric layer (high k dielectric 140, [0039]) on and surrounding a channel region (115, [0038]) of each of the semiconductor structures (100A and 100B);
an independent gate electrode (145, 146, [0041]) on each of the gate dielectric layers (140) and surrounding each of the channel regions (115), the independent gate electrodes (145, 146) vertically aligned and separated by isolation layers (portion of 105 see annotated Fig. 1B, [0045]), each isolation layer (105) on neighboring ones of the gate electrodes (145, 146);
an independent source or drain structure (215A, 215B, 220A, 220B, [0039]) coupled to each of the channel regions (115) of the semiconductor structures (100A and 100B) the independent gate sources or drains (215A, 215B, 220A, 220B) vertically aligned and separated by second isolation layers (portion of 105 see annotated Fig. 1B, [0045]), each second isolation layer on neighboring ones of the independent sources or drains (215A, 215B, 220A, 220B).
Gardner fails to teach a conductor vertically between a first and a second of the semiconductor structures and vertically between a first and a second of source or drain structures, the first and second of the source or drain structures on the first and second of the semiconductor structures, respectively, the conductor separated from the gate electrodes and the source or drain structures by isolation material, and the conductor coupled to one or more of a plurality of second vertically aligned semiconductor structures.
However, Thomas teaches a similar device in Fig. 1A in which a conductor (shared gate electrode, see annotated Fig. 1A) vertically between a first and a second of the semiconductor structures (110_1 and 110_2, [0020]) and vertically between a first and a second of source or drain structures (112 in respective semiconductor structures, [0020]), the first and second of the source or drain structures on the first and second of the semiconductor structures (there is a source or drain 112 for each transistor, 110_1 and 110_2), respectively, the conductor separated from the gate electrodes (116_1 and 116_2, [0023]) and the source or drain structures (112) by isolation material (115, [0022]), and the conductor coupled to one or more of a plurality of second vertically aligned semiconductor structures (as the conductor is physically in contact with both the semiconductor structures, it is coupled to the vertically aligned semiconductor structures). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Gardner to include a shared gate as taught by Thomas to have the gate control of the two semiconductor devices coupled together, as taught by Thomas in [0025].
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Regarding claim 3, Gardner in view of Thomas teach the apparatus of claim 1. Fig. 1B of Gardner further teaches, wherein a first of the semiconductor structures comprises a p-type semiconductor material (100B, [0041]) and a second of the semiconductor structures comprises an n-type semiconductor material (100A, [0041]).
Regarding claim 4, Gardner in view of Thomas teach the apparatus of claim 3. Fig. 1B of Gardner further teaches, wherein a first independent gate electrode (146, [0041]) coupled to the first of the semiconductor structures (transistor 100B, [0041]) comprises a first metal composition and a second independent gate electrode (145, [0041]) coupled to the second of the semiconductor structures (transistor 100A, [0041]) comprises a second metal composition ([0041] states that 145 and 146 can comprise different materials).
Regarding claim 5, Gardner in view of Thomas teach the apparatus of claim 4. Fig. 1B of Gardner further teaches, wherein a third of the semiconductor structures (repeated 100B, [0042]) adjacent to the first semiconductor structure (100B, [0041]) comprises the p-type semiconductor material or a second p-type semiconductor material (as stated in the Note of claim 1, the layers are repeated, making the structure comprise the p-type semiconductor material), and a fourth of the semiconductor structures (repeated 100A, [0042]) adjacent to the second semiconductor structure (100A, [0041]) comprises the n-type semiconductor material or a second n-type semiconductor material (as stated in the Note of claim 1, the layers are repeated, making the structure comprise the n-type semiconductor material).
Regarding claim 7, Gardner in view of Thomas teach the apparatus of claim 1. Fig. 1B of Gardner further teaches, wherein the first source or drain structure (215B, [0042]) comprises a first material, and the second source or drain structure (215A, [0041]) comprises a second material. Gardner states in [0096] that 215A and 215B can be materially different from one another.
Regarding claim 9, Gardner in view of Thomas teach the apparatus of claim 1. Thomas further teaches the conductor (shared gate electrode, see annotated Fig. 1A) comprises one of copper, aluminum, ruthenium, palladium, platinum, cobalt ([0024]), nickel, hafnium, zirconium, tungsten, or tantalum.
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Regarding claim 10, Gardner in view of Thomas teach the apparatus of claim 1. Fig. 1B of Gardner further teaches, wherein the semiconductor structures (100A and 100B, [0041]) comprise a plurality of nanoribbons, a plurality of nanosheets (115, [0038]), or a plurality of fins.
Regarding claim 24, Gardner teaches apparatus, comprising:
a plurality of vertically aligned semiconductor structures a plurality of vertically aligned semiconductor structures (transistors 100A and 100B, [0041] comprising upper semiconductor structures of a first conductivity type (100B, p-type, [0041]) and lower semiconductor structures of a second conductivity type (100A, n-type, [0041]). Note, Gardner teaches in [0042] that while not shown explicitly, that any number of transistors 100A and 100B can be repeated, making a stack of at least two transistors 100B on top of at least two transistors 100A, separated by the dielectric 105 as shown between each subsequent transistor);
a gate dielectric layer (high k dielectric 140, [0039]) on and surrounding a first region (115, [0038]) of each of the semiconductor structures (100A and 100B);
an independent gate electrode on each of the gate dielectric layers and surrounding each of the first regions, the independent gate electrodes vertically aligned and separated by isolation layers;
an independent source or drain structure coupled to a second region of each of the semiconductor structures, the independent source or drain structures vertically aligned and separated by second isolation layers; and
Gardner fails to teach a conductor extending laterally, the conductor located vertically between a lowermost of the upper semiconductor structures and an uppermost of the lower semiconductor structures and located vertically between a first source or drain structure and a second source or drain structures, the first source or drain structure on the lowermost of the upper semiconductor structures, the second source or drain structure on the uppermost of the lower semiconductor structures, the conductor separated from the gate electrodes and the source or drain structures by isolation material, and the conductor coupled to one or more of a plurality of second vertically aligned semiconductor structures.
a conductor (shared gate electrode, see annotated Fig. 1A) extending laterally, the conductor located vertically between a lowermost of the upper semiconductor structures (110_2) and an uppermost of the lower semiconductor structures (110_1) and located vertically between a first source or drain structure and a second source or drain structures (112 in respective semiconductor structures, [0020]), the first source or drain structure (112) on the lowermost of the upper semiconductor structures (110_1), the second source or drain structure (112) on the uppermost of the lower semiconductor structures (110_2), the conductor separated from the gate electrodes (116_1 and 116_2, [0023]) and the source or drain structures (112) by isolation material (115, [0022]), and the conductor coupled to one or more of a plurality of second vertically aligned semiconductor structures (as the conductor is physically in contact with both the semiconductor structures, it is coupled to the vertically aligned semiconductor structures). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Gardner to include a shared gate as taught by Thomas to have the gate control of the two semiconductor devices coupled together, as taught by Thomas in [0025].
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Regarding claim 25, Gardner in view of Thomas teach the apparatus of claim 24. Fig. 1B of Gardner further teaches, wherein the upper semiconductor structures (100B, [0041]) comprises a p-type semiconductor material ([0041]) and the lower semiconductor structures (100A, [0041]) comprises an n-type semiconductor material ([0041]).
Regarding claim 26, Gardner in view of Thomas teach the apparatus of claim 25. Fig. 1B of Gardner further teaches, wherein a first independent gate electrode (146, [0041]) coupled to the lowermost of the upper semiconductor structures (transistor 100B, [0041]) comprises a first metal composition and a second independent gate electrode (145, [0041]) coupled to the uppermost of the lower semiconductor structures (transistor 100A, [0041]) comprises a second metal composition ([0041] states that 145 and 146 can comprise different materials).
Regarding claim 27, Gardner in view of Thomas teach the apparatus of claim 26. Fig. 1B of Gardner further teaches, wherein a third of the semiconductor structures adjacent to the lowermost of the upper semiconductor structures (repeated 100B, [0042]) comprises the p-type semiconductor material or a second p-type semiconductor material (as stated in the Note of claim 1, the layers are repeated, making the structure comprise the p-type semiconductor material), and a fourth of the semiconductor structures adjacent to the uppermost of the lower semiconductor structures (repeated 100A, [0042]) comprises the n-type semiconductor material or a second n-type semiconductor material (as stated in the Note of claim 1, the layers are repeated, making the structure comprise the n-type semiconductor material).
Regarding claim 29, Gardner in view of Thomas teach the apparatus of claim 24. Fig. 1B of Gardner further teaches, wherein the first source or drain structure (215B, [0042]) comprises a first material, and the second source or drain structure (215A, [0041]) comprises a second material. Gardner states in [0096] that 215A and 215B can be materially different from one another.
Regarding claim 30, Gardner in view of Thomas teach the apparatus of claim 24. Thomas further teaches the conductor (shared gate electrode, see annotated Fig. 1A) comprises one of copper, aluminum, ruthenium, palladium, platinum, cobalt ([0024]), nickel, hafnium, zirconium, tungsten, or tantalum.
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Regarding claim 31, Gardner in view of Thomas teach the apparatus of claim 24. Fig. 1B of Gardner further teaches, wherein the semiconductor structures (100A and 100B, [0041]) comprise a plurality of nanoribbons, a plurality of nanosheets (115, [0038]), or a plurality of fins.
Claim(s) 6 and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gardner in view of Thomas in further view of Noh et al. (US 2022/0085161 A1, hereafter Noh).
Regarding claim 6, Gardner in view of Thomas teach the apparatus of claim 5. Fig. 1B of Gardner further teaches, wherein a third independent gate electrode (repeated 146, [0042]) is coupled to the third semiconductor structure (repeated 100B, [0042]), and a fourth independent gate electrode (repeated 145, [0042]) is coupled to the fourth semiconductor structure (repeated 100A, [0042]), and wherein the first and third gate electrodes (repeated 145 and 146) are separated by a first isolation layer having a first composition and the second and fourth gate electrodes are separated by a second isolation layer. Gardner in view of Thomas is silent on the second isolation material having a second composition.
However, Noh teaches a similar nanosheet semiconductor device in which spacers (1131/1132/1133; 1151) and gate caps (1141/1142/1143) made of various materials ([0061]; [0065] and [0070]) are used to cap and separate the stacks of transistors. While not explicitly being used to isolate individual transistors, these are known insulating layers, and thus function the same. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Gardner in view of Thomas to include the various materials used in Noh for the isolation layers for the expected result of different properties in the isolation layer such as etch resistant differences or differences in RC-time constants between the individual transistors.
Regarding claim 28, Gardner in view of Thomas teach the apparatus of claim 27. Fig. 1B of Gardner further teaches, wherein a third independent gate electrode (repeated 146, [0042]) is coupled to the third semiconductor structure (repeated 100B, [0042]), and a fourth independent gate electrode (repeated 145, [0042]) is coupled to the fourth semiconductor structure (repeated 100A, [0042]), and wherein the first and third gate electrodes (repeated 145 and 146) are separated by a first isolation layer having a first composition and the second and fourth gate electrodes are separated by a second isolation layer. Gardner in view of Thomas is silent on the second isolation material having a second composition.
However, Noh teaches a similar nanosheet semiconductor device in which spacers (1131/1132/1133; 1151) and gate caps (1141/1142/1143) made of various materials ([0061]; [0065] and [0070]) are used to cap and separate the stacks of transistors. While not explicitly being used to isolate individual transistors, these are known insulating layers, and thus function the same. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Gardner in view of Thomas to include the various materials used in Noh for the isolation layers for the expected result of different properties in the isolation layer such as etch resistant differences or differences in RC-time constants between the individual transistors.
Claim(s) 11 and 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gardner in view of Thomas in view of Lee et al. (US 2021/0296445 A1, hereafter Lee).
Regarding claim 11, Gardner in view of Thomas teach the apparatus of claim 1. Gardner in view of Thomas is silent on a first of the semiconductor structures has a thickness in the vertical direction of not more than 2 nm. However, one of ordinary skill in the art would know to use a known thickness of nanosheets in the art.
Lee teaches a similar nanosheet transistor in which the channel thickness is between 0 and 3nm [0026], which is necessary according to the present application. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the channel thickness of the channels of Gardner in view of Thomas to be within the thickness range of Lee in order to get the expected result of a functional device.
Regarding claim 32, Gardner in view of Thomas teach the apparatus of claim 24. Gardner in view of Thomas is silent on a first of the semiconductor structures has a thickness in the vertical direction of not more than 2 nm. However, one of ordinary skill in the art would know to use a known thickness of nanosheets in the art.
Lee teaches a similar nanosheet transistor in which the channel thickness is between 0 and 3nm [0026], which is necessary according to the present application. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the channel thickness of the channels of Gardner in view of Thomas to be within the thickness range of Lee in order to get the expected result of a functional device.
Claim(s) 12 and 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gardner in view of Thomas in view of Lee and in view of Porter et al. (US 5,028,988, hereafter Porter).
Regarding claim 12, Gardner in view of Thomas in view of Lee teaches the device of claim 11. Gardner in view of Thomas in view of Lee fail to teach a cooling structure operable to remove heat from an IC die comprising the semiconductor structures to achieve an operating temperature at or below -25°C.
However, in Fig. 5 Porter teaches an integrated circuit similar to Gardner which is coupled to a cooling apparatus to get the chip to an operating temperature of -20 degrees Fahrenheit (column 6 line 53). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Gardner in view of Thomas in view of Lee to include the cooling apparatus of Porter in order to increase the performance of the IC chip (column 6 lines 53-56 of Porter.)
Regarding claim 33, Gardner in view of Thomas in view of Lee teaches the device of claim 32. Gardner in view of Thomas in view of Lee fail to teach a cooling structure operable to remove heat from an IC die comprising the semiconductor structures to achieve an operating temperature at or below -25°C.
However, in Fig. 5 Porter teaches an integrated circuit similar to Gardner which is coupled to a cooling apparatus to get the chip to an operating temperature of -20 degrees Fahrenheit (column 6 line 53). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Gardner in view of Thomas in view of Lee to include the cooling apparatus of Porter in order to increase the performance of the IC chip (column 6 lines 53-56 of Porter.)
Claim(s) 23 and 34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gardner in view of Thomas in view of Sharangpani et al. (US 2022/0130853 A1, hereafter Sharangpani).
Regarding claim 23, Gardner in view of Thomas teach the apparatus of claim 1, further comprising:
an integrated circuit (IC) die comprising the semiconductor structures (transistors 100A and 100B of Gardner, [0041]), the gate dielectric layers (high k dielectric 140 of Gardner, [0039]), the independent gate electrodes (145 and 146 of Gardner, [0041]), the independent source or drain structures (215A, 215B, 220A, and 220B of Gardner, [0039]), and the conductor (shared gate electrode of Thomas, see annotated Fig. 1A);
Gardner in view of Thomas fails to teach a power supply coupled to the IC die. However, Sharangpani teaches a device similar that is coupled to a peripheral circuitry with a power supply in order to supply power to the die [0118]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Gardner in view of Thomas to include the peripheral circuitry of Sharangpani in order to get the expected result of a device with power.
Regarding claim 34, Gardner in view of Thomas teach the apparatus of claim 24, further comprising:
an integrated circuit (IC) die comprising the semiconductor structures (transistors 100A and 100B of Gardner, [0041]), the gate dielectric layers (high k dielectric 140 of Gardner, [0039]), the independent gate electrodes (145 and 146 of Gardner, [0041]), the independent source or drain structures (215A, 215B, 220A, and 220B of Gardner, [0039]), and the conductor (shared gate electrode of Thomas, see annotated Fig. 1A);
Gardner in view of Thomas fails to teach a power supply coupled to the IC die. However, Sharangpani teaches a device similar that is coupled to a peripheral circuitry with a power supply in order to supply power to the die [0118]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Gardner in view of Thomas to include the peripheral circuitry of Sharangpani in order to get the expected result of a device with power.
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Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMMANTHA K SALAZ whose telephone number is (571)272-2484. The examiner can normally be reached Monday - Friday 8:00am-5:00pm.
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/SAMMANTHA K SALAZ/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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