DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-22 are pending in the application and are currently being examined. Claims 2, 13, and 21 have been amended. No claims have been canceled. Claims 17-22 have been withdrawn per the 10/17/2025 restriction election (see below). No new claims have been added.
Election/Restrictions
Claims 17-22 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention and species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10/17/2025.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/27/2025 is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities: Lines 16-18 of page 14 do not read clearly, lines 19-20 of page 16 second instance of 700 should be 600. This is not an exhaustive list due to the length of the specification.
Appropriate correction is required.
The use of the terms Wi-Fi, GPS, LTE, etc., each of which is a trade name or a mark used in commerce, has been noted in this application. The terms should be accompanied by the generic terminology; furthermore the terms should be capitalized wherever it appears or, where appropriate, include a proper symbol indicating use in commerce such as ™, SM , or ® following the term. These are not the only instances in the written specification, it is advised that a thorough read be done. It appears that the improper use of trade names starts on page 31 and continues through page 33.
Although the use of trade names and marks used in commerce (i.e., trademarks, service marks, certification marks, and collective marks) are permissible in patent applications, the proprietary nature of the marks should be respected and every effort made to prevent their use in any manner which might adversely affect their validity as commercial marks.
Drawings
The drawings are objected to because Fig. 17 appears to be missing a label and has an inconsistent pattern for layers 601. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5, 7, and 10 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Gardner et al. (US 2023/0114024 A1, hereafter Gardner).
Regarding claim 1, Fig. 1B of Gardner teaches a device, comprising:
a plurality of vertically aligned semiconductor structures (transistors 100A and 100B, [0041]. Note, Gardner teaches in [0042] that while not shown explicitly, that any number of transistors 100A and 100B can be repeated, making a stack of at least two transistors 100B on top of at least two transistors 100A, separated by the dielectric 105 as shown between each subsequent transistor);
a gate dielectric layer (high k dielectric 140, [0039]) on and surrounding a channel region (115, [0038]) of each of the semiconductor structures (100A and 100B); and
an independent gate electrode (145, 146, [0041]) on each of the gate dielectric layers (140) and surrounding each of the channel regions (115), the independent gate electrodes (145, 146) vertically aligned and separated by isolation layers (portion of 105 see annotated Fig. 1B, [0045]), each isolation layer (105) on neighboring ones of the gate electrodes (145, 146).
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Regarding claim 2, Fig. 1B of Gardner teaches the device of claim 1, further comprising:
an independent source or drain (215A, 215B, 220A, 220B, [0039]) coupled to each of the channel regions (115, [0038]) of the semiconductor structures (transistors 100A and 100B, [0041]), the independent gate sources or drains (215A, 215B, 220A, 220B) vertically aligned and separated by second isolation layers (portion of 105 see annotated Fig. 1B, [0045]), each second isolation layer on neighboring ones of the independent sources or drains (215A, 215B, 220A, 220B).
Regarding claim 3, Fig. 1B of Gardner teaches the device of claim 1, wherein a first of the semiconductor structures comprises a p-type semiconductor material (100B, [0041]) and a second of the semiconductor structures comprises an n-type semiconductor material (100A, [0041]).
Regarding claim 4, Fig. 1B of Gardner teaches the device of claim 3, wherein a first independent gate electrode (146, [0041]) coupled to the first semiconductor structure (transistor 100B, [0041]) comprises a first metal composition and a second independent gate electrode (145, [0041]) coupled to the second semiconductor structure (transistor 100A, [0041]) comprises a second metal composition ([0041] states that 145 and 146 can comprise different materials).
Regarding claim 5, Fig. 1B of Gardner teaches the device of claim 4, wherein a third of the semiconductor structures (repeated 100B, [0042]) adjacent to the first semiconductor structure (100B, [0041]) comprises the p-type semiconductor material or a second p-type semiconductor material (as stated in the Note of claim 1, the layers are repeated, making the structure comprise the p-type semiconductor material), and a fourth of the semiconductor structures (repeated 100A, [0042]) adjacent to the second semiconductor structure (100A, [0041]) comprises the n-type semiconductor material or a second n-type semiconductor material (as stated in the Note of claim 1, the layers are repeated, making the structure comprise the n-type semiconductor material).
Regarding claim 7, Fig. 1B of Gardner teaches the device of claim 3, further comprising:
a first source or drain (215B, [0042]) comprising a first material coupled to the first semiconductor structure (100B, [0041]); and
a second source or drain (215A, [0041]) comprising a second material coupled to the second semiconductor structure (100A, [0041]). Gardner states in [0096] that 215A and 215B can be materially different from one another.
Regarding claim 10, Fig. 1B of Gardner teaches the device of claim 1, wherein the semiconductor structures (100A and 100B, [0041]) comprise a plurality of nanoribbons, a plurality of nanosheets (115, [0038]), or a plurality of fins.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gardner in view of Noh et al. (US 2022/0085161 A1, hereafter Noh).
Regarding claim 6, Fig. 1B of Gardner teaches the device of claim 5, wherein a third independent gate electrode (repeated 146, [0042]) is coupled to the third semiconductor structure (repeated 100B, [0042]), and a fourth independent gate electrode (repeated 145, [0042]) is coupled to the fourth semiconductor structure (repeated 100A, [0042]), and wherein the first and third gate electrodes (repeated 145 and 146) are separated by a first isolation layer having a first composition and the second and fourth gate electrodes are separated by a second isolation layer. Gardner is silent on the second isolation material having a second composition.
However, Noh teaches a similar nanosheet semiconductor device in which spacers (1131/1132/1133; 1151) and gate caps (1141/1142/1143) made of various materials ([0061]; [0065] and [0070]) are used to cap and separate the stacks of transistors. While not explicitly being used to isolate individual transistors, these are known insulating layers, and thus function the same. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Gardner to include the various materials used in Noh for the isolation layers for the expected result of different properties in the isolation layer such as etch resistant differences or differences in RC-time constants between the individual transistors.
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gardner in view of Yang (US 2022/0093593 A1).
Regarding claim 8, Fig. 1B of Gardner teaches the device of claim 1. Gardner fails to disclose a conductor between a first and second of the semiconductor structures, the conductor separated from the gate electrodes by isolation material, and the conductor coupled to one or more of a plurality of second vertically aligned semiconductor structures.
However, in Fig. 12 of Yang, there are conductors adjacent to sidewalls of the transistors (sources/drains 44, [0025]). When added to Gardner, these conductors are separated from the gate electrodes by isolation material (105 of Gardner, [0045]) Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Gardner to add the conductors of Yang (as shown in annotated Fig. 1B of Gardner) in order to get the expected result of creating a set of parallel devices.
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Regarding claim 9, Gardner in view of Yang teaches the device of claim 8. Gardner in view of Yang further teach in annotated Fig. 1B, the conductor (sources/drains of Yang 44, [0025]) extends between first and second independent sources or drains (215A, 215B, 220A, 220B, of Gardner, [0039]) coupled to channel regions (115 of Gardner, [0038]) of the first and second semiconductor structures (transistors 100A and 100B of Gardner, [0041]). While not physically between the independent first and second sources and drains, the conductor is in a layer between the bounds of the independent first and second sources and drains.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gardner in view of Lee et al. (US 2021/0296445 A1, hereafter Lee).
Regarding claim 11, Fig. 1B of Gardner teaches the device of claim 1. Gardner is silent on a first of the semiconductor structures has a thickness in the vertical direction of not more than 2 nm. However, one of ordinary skill in the art would know to use a known thickness of nanosheets in the art.
Lee teaches a similar nanosheet transistor in which the channel thickness is between 0 and 3nm [0026], which is necessary according to the present application. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the channel thickness of the channels of Gardner to be within the thickness range of Lee in order to get the expected result of a functional device.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gardner in view of Lee and in view of Porter et al. (US 5,028,988, hereafter Porter).
Regarding claim 12, Gardner in view of Lee teaches the device of claim 11. Gardner in view of Lee fail to teach a cooling structure operable to remove heat from an IC die comprising the semiconductor structures to achieve an operating temperature at or below -25°C.
However, in Fig. 5 Porter teaches an integrated circuit similar to Gardner which is coupled to a cooling apparatus to get the chip to an operating temperature of -20 degrees Fahrenheit (column 6 line 53). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Gardner in view of Lee to include the cooling apparatus of Porter in order to increase the performance of the IC chip (column 6 lines 53-56 of Porter.)
Claim(s) 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gardner in view of Sharangpani et al. (US 2022/0130853 A1, hereafter Sharangpani).
Regarding claim 13, Fig. 1B of Gardner teaches a system, comprising:
an integrated circuit (IC) die comprising a multi-transistor structure, comprising:
a plurality of vertically aligned semiconductor structures (transistors 100A and 100B, [0041]. Note, Gardner teaches in [0042] that while not shown explicitly, that any number of transistors 100A and 100B can be repeated, making a stack of at least two transistors 100B on top of at least two transistors 100A, separated by the dielectric 105 as shown between each subsequent transistor);
an independent gate electrode (145, 146, [0041]) surrounding a channel region (115, [0038]) of each of the semiconductor structures (100A and 100B), the independent gate electrodes vertically aligned and separated by isolation layers, each isolation layer on neighboring ones of the gate electrodes; and
an independent source or drain coupled to each of the channel regions of the semiconductor structures, the independent gate sources or drains vertically aligned and separated by second isolation layers, each second isolation layer on neighboring ones of the independent sources or drains; and
Gardner fails to teach a power supply coupled to the IC die. However, Sharangpani teaches a device similar that is coupled to a peripheral circuitry with a power supply in order to supply power to the die [0118]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Gardner to include the peripheral circuitry of Sharangpani in order to get the expected result of a device with power.
Regarding claim 14, Gardner in view of Sharangpani teaches the system of claim 13, wherein a first of the semiconductor structures comprises a p-type semiconductor material (100B of Gardner, [0041]) and a second of the semiconductor structures comprises an n-type semiconductor material (100A of Gardner, [0041]).
Regarding claim 15, Gardner in view of Sharangpani teaches the system of claim 14, wherein a first independent gate electrode (146, [0041]) coupled to the first semiconductor structure (transistor 100B, [0041]) comprises a first metal composition and a second independent gate electrode (145, [0041]) coupled to the second semiconductor structure (transistor 100A, [0041]) comprises a second metal composition ([0041] states that 145 and 146 can comprise different materials).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gardner in view of Sharangpani and further in view of Yang.
Regarding claim 16, Gardner in view of Sharangpani teaches the system of claim 13. Gardner in view of Sharangpani fails to disclose a conductor between a first and second of the semiconductor structures, the conductor separated from the gate electrodes by isolation material, and the conductor coupled to one or more of a plurality of second vertically aligned semiconductor structures.
However, in Fig. 12 of Yang, there are conductors adjacent to sidewalls of the transistors (sources/drains 44, [0025]). When added to Gardner in view of Sharangpani, these conductors are separated from the gate electrodes by isolation material (105 of Gardner, [0045]) Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Gardner in view of Sharangpani to add the conductors of Yang (as shown in annotated Fig. 1B of Gardner) in order to get the expected result of creating a set of parallel devices.
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMMANTHA K SALAZ whose telephone number is (571)272-2484. The examiner can normally be reached Monday - Friday 8:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SAMMANTHA K SALAZ/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892