DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to Amendment filed on February 24, 2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 6-8 are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Lee (US 2021/0257366).
Regarding claim 1, Lee discloses for a memory device, comprising that
an access transistor (transistor TR, Fig. 12) comprising a channel (channel region CH of the active region ACT, Fig. 3B) between a source (first source/drain region SD1, Fig. 3B, 12) and a drain (second source/drain region SD2, Fig. 3B, 12);
a plurality of first capacitors (a plurality of capacitors CAP1, Fig. 7, 12) comprising a first shared plate (storage node SN of CAP1, Fig. 7, 12) and a plurality of first separate plates (plate node PN of CAP1, Fig. 7, 12), the first shared plate (SN of CAP1, Fig. 7, 12) coupled to and above the source or the drain (above source/drain regions of the active region ACT1, Fig. 7, 12), because Applicants do not specifically claim what orientation the claimed access transistor has and/or how the capacitors and source/drain are arranged, when the memory device by Lee is oriented along the direction D2 as a vertical direction, as shown in the attached and annotated Fig. 7 and 12 below, the first capacitors CAP1 is positioned above the first active regions CAP1 having the source/drain regions SD1/SD2 (see Fig. 7, 12 below),
wherein individual ones of the first capacitors (CAP1, Fig. 7, 12) comprise one of the first separate plates (PN of CAP1, Fig. 12), a portion of the first shared plate (a portion of SN of CAP1, Fig. 12), and a first insulator therebetween (dielectric layer DE of CAP1, Fig. 12);
a plurality of second capacitors (a plurality of capacitors CAP2, Fig. 7, 12) comprising a second shared plate (storage node SN of CAP2, Fig. 7, 12) and a plurality of second separate plates (plate node PN of CAP2, Fig. 7, 12), the second shared plate (SN of CAP2, Fig. 7, 12) coupled to and below the source or the drain (below source/drain regions of the active region ACT2, see attached Fig. 7, 12 below),
wherein individual ones of the second capacitors (CAP2, Fig. 7, 12) comprise one of the second separate plates (PN of CAP2, Fig. 7, 12), a portion of the second shared plate (a portion of SN of CAP2, Fig. 7, 12), and a second insulator therebetween (dielectric layer DE of CAP2, Fig. 7, 12); and
a plurality of platelines (a plurality of plate lines PL, Fig. 7, 12), individual ones of the platelines (PL, Fig. 7, 12) electrically connected to corresponding ones of the first and second separate plates (PN of CAP1 and CAP2, Fig. 7, 12).
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Regarding claim 6, Lee further discloses for the memory device of claim 1 that the first and second capacitors (CAP1 and CAP2, Fig. 7, 12 above) are vertically aligned, because Applicants do not specifically claim what orientation the claimed access transistor has and/or how the capacitors and source/drain are arranged, when the memory device by Lee is oriented along the direction D2 as a vertical direction as shown in the attached and annotated Fig. 7 and 12 above, the first capacitor CAP1 and the second capacitor CAP2 are vertically aligned along the direction D2 disclosed by Lee.
Regarding claim 7, Lee further discloses for the memory device of claim 1 that the first capacitors (CAP1, Fig. 7, 12) are on a front side of an integrated circuit (IC) die, and the second capacitors (CAP2, Fig. 7, 12) are on a back side of the IC die, because Applicants do not specifically claim what orientation the claimed access transistor has and/or how the capacitors and source/drain are arranged, when the memory device by Lee is oriented along the direction D2 as a vertical direction as shown in the attached and annotated Fig. 7 and 12 above, the first capacitors CAP1 in Lee are on the front side of the memory device 700, which corresponds to the IC die in the claimed invention, and the second capacitors CAP2 are on the back side of the memory device 700 (Fig. 7, 12).
Regarding claim 8, Lee further discloses for the memory device of claim 1 that the first and second shared plates (SN of CAP1 and CAP2, Fig. 7, 12) comprise first and second vertical regions (vertical regions of SN in CAP1 and CAP2, respectively, see attached Fig. 12 below), respectively, and individual ones of the first and second separate plates (PN of CAP1 and CAP2, Fig. 7, 12) encircle the first and second shared plates (SN of CAP1 and CAP2, see attached Fig. 5, 12 below) in horizontal planes (the direction D1 in the attached Fig. 12 below) spaced at heights along the first and second vertical regions (vertical regions of SN in CAP1 and CAP2, Fig. 12 below), because the plate node PN surrounds the storage node SN, therefore, the PN horizontally encircles the SN, and the vertical regions of SN of CAP1 and CAP2 are vertically spaced apart from each other along the direction D2 (see Fig. 12 below).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-5 are rejected under 35 U.S.C. 103 as being unpatentable over by Lee (US 2021/0257366) in view of Gomes et al. (US 2021/0159229, Filed: Nov. 21, 2019; hereinafter Gomes).
Regarding claim 2, Lee does not explicitly disclose that individual ones of the first and second insulators comprise a ferroelectric material.
However, Gomes discloses for a three-dimensional nanoribbon-based dynamic random access memory (DRAM) that the capacitor 320 (Fig. 3) includes the electrode 328 at the end of the nanoribbon channel 304, which corresponds to the first capacitor plate in the claimed invention, and the electrode 326, which corresponds to the second capacitor plate in the claimed invention, and the capacitor dielectric 330 is formed therebetween (Fig. 3), and the capacitor dielectric 330 by Gomes includes “a layer of a ferroelectric material (i.e., in some embodiments, a ferroelectric material may be provided between the two electrodes of the capacitor 320 or 220). Such a ferroelectric material may include one or more materials with exhibit sufficient ferroelectric behavior even at thin dimensions” ([0060]), therefore, one of ordinary skill in the semiconductor memory device would readily recognize that the dielectric layer DE of Lee between capacitor electrodes can be replaced with the ferroelectric material disclosed by Gomes, in order to improve memory retention and polarization switching properties of the memory device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a capacitor of the memory device may include a ferroelectric material layer between capacitor electrodes, as disclosed by Gomes, in order to improve memory retention and polarization switching properties of the memory device.
Regarding claim 3, Gomes further discloses that the ferroelectric material comprises oxygen and one or more of hafnium, zirconium, strontium, niobium, lanthanum, lead, and titanium, because the ferroelectric material by Gomes includes that “Some examples of such materials known at the moment include hafnium zirconium oxide (HfZrO, also referred to as HZO)…” (emphasis added, [0060]).
Regarding claim 4, Gomes does not explicitly disclose that the ferroelectric material has a capacitance of at least 1 fF and not more than 30 fF.
However, one of ordinary skill in the art would acknowledge that a capacitance depends on the material’s dielectric constant (k), the geometry or dimensions such as thickness and area, and the electrode configuration (Formula: Capacitance (C) = vacuum permittivity • relative dielectric constant • electrode area / dielectric thickness), and since Applicants do not specifically claim the dimensions of the ferroelectric material or electrode area and/or the capacitance measurement parameters such as frequency or voltage, the capacitance is a result-effective variable to be optimized or adjusted by the known parameters (e.g., thickness, area, dielectric constant) of a known ferroelectric material (for example, HfZrO disclosed by Gomes, [0060]) to obtain a desired capacitance range.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to adjust or optimize the thickness and/or electrode area of the known ferroelectric material disclosed by Gomes (i.e., hafnium zirconium oxide, HfZrO) to obtain a capacitance within the range of 1fF to 30 fF, since capacitance is a result-effective variable that depends on well-known geometric and material parameters of the capacitor structure.
Regarding claim 5, Gomes further discloses that the ferroelectric material has a thickness of at least 2 nm and not more than 20 nm, because “The ferroelectric material included in the capacitor 220/320 may have a thickness that may, in some embodiments, be between about 0.5 nanometers and 10 nanometers” (emphasis added, [0060]), therefore, the claimed range “not more than 7 nm” is overlapped with the range disclosed by Gomes.
Allowable Subject Matter
Claims 9-12 and 23-25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The cited prior arts in this Office Action do not teach the claim limitation recited in lines 4-15 of claim 23 and claim 24. Claim 25 depends on claim 24.
Response to Arguments
Applicant's arguments filed in February 24, 2026 have been fully considered but they are not persuasive due to the following reasons: Applicants do not specifically claim which elements or structures share “the first shared plate”. As illustrated below in the annotated Fig. 5 of Lee with a bird-eye view of the capacitor CAP disclosed by Lee, the capacitor CAP includes the plate node PN having an internal node N2 and external nodes N21, N22, N23 and N24. The internal node N2 is disposed within the interior of the storage node SN. In this configuration, the storage node SN surrounds and interfaces with the internal node N2 along its four sides – top, bottom, left, and right sides, thereby forming multiple capacitive couplings along each side of the internal node N2. Because the storage node SN in Lee is shared by each side of the internal node N2 of the plate node PN, the structure constitutes a plate that is shared across multiple interfaces, consistent with the claimed “first shared plate”. (see attached Fig. 5 of Lee below). Also, because the capacitor CAP2 by Lee, which corresponds to the second shared plate in the claimed invention, exhibits the same internal shape and configuration as the capacitor CAP1, the storage node SN of CAP2 is consistent with the claimed “second shared plate”. Therefore, the rejection of claim 1 under 35 USC 102 is proper.
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Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WOO K LEE whose telephone number is (571)270-5816. The examiner can normally be reached Monday - Friday, 8:30 am - 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WOO K LEE/Examiner, Art Unit 2815
/MONICA D HARRISON/Primary Examiner, Art Unit 2815
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