Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Species B (Fig. 2) in the reply filed on 1/26/2026 is acknowledged.
Claims 1-14 and 16-22 are elected for examination and claim 15 is withdrawn from consideration.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-3, 5-6, 9-11 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Giterman et al. (US Pub. No. 2024/0062811 A1), hereafter referred to as Giterman, in view of Bennett (US Pub. No. 2020/0342932 A1).
As to claim 1, Giterman discloses a memory device (fig 2A and fig 10; [0016]), comprising:
an array of bit cells (fig 10, array 300 of cells 100), wherein individual ones of the bit cells (fig 2A, cells 100) comprise:
a first transistor (transistor 20) comprising a first channel region (region of fin 25 covered with SN Gate) coupled to a first gate (SN Gate), wherein the first channel region extends in a first direction (vertical direction); and
a second transistor (transistor 10) comprising a second channel region (region of fin 15 covered by WWL gate) substantially parallel to the first channel region (vertical direction), wherein a first end of the second channel region is coupled to the first gate (SN contact couples fin 15 to SN Gate); and
a read bitline (fig 8, RBL1-4) and a write bitline (WBL1-4), the first channel regions of the first and second bit cells are within a first channel structure coupled to the read bitline (fig 10 shows the first channel structure 25 of adjacent first and second bit cells coupled to read bitline through RBL active contact), and the second channel regions of the second and third bit cells are within a second channel structure coupled to the write bitline (fig 10 shows the second channel regions of second and third bit cells coupled to write bitline through WBL active contact).
Giterman further discloses a simplified schematic of the read and write bitlines wherein the read and write bitlines are parallel and extend in a second direction (vertical direction), wherein a first bit cell and a second bit cell are on opposite sides of the read bitline (2T Gain-Cells on opposite sides of RBL), the second bit cell and a third bit cell are on opposite sides of the write bitline (2TGain-Cells on opposite sides of WBL).
However, Giterman does not explicitly show the physical layout of the read and write bitlines.
Nonetheless, Bennett discloses wherein read and write bitlines extend parallel in a second direction (fig 15B, 1520 and 1522).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the read and write bitlines of Giterman in a parallel second direction as taught by Bennett since this will provide good electrical interconnection to the cells along the memory device.
As to claim 2, Giterman in view of Bennett disclose the memory device of claim 1 (paragraphs above).
Bennett further discloses wherein the second direction is substantially orthogonal to the first direction (fig 15B, read and write lines 1520/1522 are orthogonal to extending direction of the fins).
As to claim 3, Giterman in view of Bennett disclose the memory device of claim 1 (paragraphs above).
Giterman further discloses wherein the first transistors on opposing sides of the read bitline or the second transistors on opposing sides of the write bitline share a substantially vertical fin, and the substantially vertical fin comprises corresponding ones of the first or second channel regions (fig 10, vertical fins 15 and 25 are shared between the cells 100).
As to claim 5, Giterman in view of Bennett disclose the memory device of claim 1 (paragraphs above).
Giterman further discloses wherein, for an individual one of the bit cells (fig 2A, 100):
a first end of the first channel region is electrically connected to a read wordline (fig 2A-B, end of first channel connected to RWL);
a second end of the first channel region is electrically connected to the read bitline (second end of first channel 25 connected to RBL); the second end of the second channel region is electrically connected to the first gate (second end of channel 15 connected to SN Gate); an outer end of the second channel region is electrically connected to the write bitline (end of 15 connected to WBL); and
the second transistor comprises a second gate (WWL gate), wherein the second channel region is coupled to the second gate (15 connected to WWL gate), and the second gate is electrically connected to a write wordline (WWL gate contact).
As to claim 6, Giterman in view of Bennett disclose the memory device of claim 1 (paragraphs above).
Giterman further discloses wherein the first or second transistors are p- type transistors, and the second or first transistors are n-type transistors ([0033]).
As to claim 9, Giterman discloses an integrated circuit system ([0036]), comprising:
an array of bit cells (fig 10, array 300 of cells 100), wherein individual ones of the bit cells (fig 2A, cells 100) comprise:
a first transistor (transistor 20) comprising a first channel region (region of fin 25 covered with SN Gate) coupled to a first gate (SN Gate), wherein the first channel region extends in a first direction (vertical direction); and
a second transistor (transistor 10) comprising a second channel region (region of fin 15 covered by WWL gate) substantially parallel to the first channel region (vertical direction), wherein a first end of the second channel region is coupled to the first gate (SN contact couples fin 15 to SN Gate); and
a read bitline (fig 8, RBL1-4) and a write bitline (WBL1-4), the first channel regions of the first and second bit cells are within a first channel structure coupled to the read bitline (fig 10 shows the first channel structure 25 of adjacent first and second bit cells coupled to read bitline through RBL active contact), and the second channel regions of the second and third bit cells are within a second channel structure coupled to the write bitline (fig 10 shows the second channel regions of second and third bit cells coupled to write bitline through WBL active contact).
Giterman further discloses a simplified schematic of the read and write bitlines wherein the read and write bitlines are parallel and extend in a second direction (vertical direction), wherein a first bit cell and a second bit cell are on opposite sides of the read bitline (2T Gain-Cells on opposite sides of RBL), the second bit cell and a third bit cell are on opposite sides of the write bitline (2TGain-Cells on opposite sides of WBL).
However, Giterman does not explicitly show the physical layout of the read and write bitlines.
Nonetheless, Bennett discloses wherein read and write bitlines extend parallel in a second direction (fig 15B, 1520 and 1522).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the read and write bitlines of Giterman in a parallel second direction as taught by Bennett since this will provide good electrical interconnection to the cells along the memory device.
Bennett further discloses a power supply coupled to an IC die ([0059]-[0061]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include a power supply coupled to the IC die of Giterman as taught by Bennett since this will provide functional operation of the memory device.
As to claim 10, Giterman in view of Bennett disclose the IC system of claim 9 (paragraphs above).
Bennett further discloses wherein the second direction is substantially orthogonal to the first direction (fig 15B, read and write lines 1520/1522 are orthogonal to extending direction of the fins).
As to claim 11, Giterman in view of Bennett disclose the IC system of claim 9 (paragraphs above).
Giterman further discloses wherein the first or second channel regions are comprised within substantially vertical fins (fig 10, vertical fins 15 and 25 are shared between the cells 100).
As to claim 18, Giterman discloses a method ([0036]), comprising:
receiving a base substrate with a first set of channel structures (fig 2A, finFET channels 15 and 25), the first set of channel structures collinear and extending in a first direction (vertical direction);
forming a second set of channel structures (fig 10, finFET channels 15 and 25 of adjacent column of cells 100), wherein the second set of channel structures are collinear (linear in vertical direction), the second set of channel structures parallel to and offset in the first direction from the first set of channel structures (adjacent cells 100 with fins 15/25 offset in vertical direction); and
wherein the first bitlines couple to the first set of channel structures and the second bitlines couple to the second set of channel structures (fig 8 bitlines RBL and WBL coupled to channels of fins 15/25 through WBL active contact and RBL active contact).
Giterman forming conductive structures comprising first bitlines and second bitlines, the first and second bitlines parallel and extending in a second direction, the second direction substantially orthogonal to the first direction.
Nonetheless, Bennett discloses wherein read and write bitlines extend parallel in a second direction (fig 15B, 1520 and 1522).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the read and write bitlines of Giterman in a parallel second direction as taught by Bennett since this will provide good electrical interconnection to the cells along the memory device.
Claim(s) 4 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Giterman in view of Bennett and further in view of Uchida et al. (US Pub. No. 2023/0352070 A1).
As to claim 4, Giterman in view of Bennett disclose the memory device of claim 1 (paragraphs above).
Giterman in view of Bennett do not disclose wherein the first transistors on opposing sides of the read bitline or the second transistors on opposing sides of the write bitline share a nanowire or nanosheet, and the nanowire or nanosheet comprises corresponding ones of the first or second channel regions.
Nonetheless, Uchida discloses wherein the channel structure in a field effect transistor may be a nanowire/nanosheet ([0102]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the finFET channels of Giterman in view of Bennett as a nanowire/nanosheet channel structure as taught by Uchida since allows for improved electrical mobility of the semiconductor device.
As to claim 12, Giterman in view of Bennett disclose the IC system of claim 9 (paragraphs above).
Giterman in view of Bennett do not disclose wherein the first or second channel regions are comprised within nanowires or nanosheets.
Nonetheless, Uchida discloses wherein the channel structure in a field effect transistor may be a nanowire/nanosheet ([0102]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the finFET channels of Giterman in view of Bennett as a nanowire/nanosheet channel structure as taught by Uchida since allows for improved electrical mobility of the semiconductor device.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Giterman in view of Bennett and further in view of Farias Moguel et al. (US Pub. No. 2022/0117114 A1), hereafter referred to as Farias Moguel.
As to claim 16, Giterman in view of Bennett disclose the IC system of claim 9 (paragraphs above).
Giterman in view of Bennett wherein the IC system comprises or is thermally coupled to a cooling structure, the cooling structure operable to remove heat from the IC die to achieve an operating temperature at or below 0°C.
Nonetheless, Farias Moguel discloses wherein an IC system comprises or is thermally coupled to a cooling structure, the cooling structure operable to remove heat from the IC die to achieve an operating temperature at or below 0°C ([0014]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to couple the IC system of Giterman in view of Bennett to a cooling structure as taught by Farias Moguel since this will improve the performance of the semiconductor device.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Giterman in view of Bennett and Farias Moguel and further in view of Lin et al. (US Pub. No. 2023/0402521 A1), hereafter referred to as Lin.
As to claim 17, Giterman in view of Bennett and Farias Moguel disclose the IC system of claim 16 (paragraphs above).
Giterman in view of Bennett do not disclose wherein an individual one of the first or second channel regions has a thickness of not more than 2 nm.
Nonetheless, Lin discloses an individual one of channel regions has a thickness of not more than 2nm ([0014]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the channel thickness of Giterman not more than 2nm as taught by Lin since the thickness of the channel is chosen based on device performance considerations.
Allowable Subject Matter
Claims 7-8, 13-14, 19-22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach or suggest wherein the first and second channel regions are in vertically adjacent layers of an integrated circuit (IC) die, as recited in claims 7 and 13; or wherein the first set of channel structures and the second set of channel structures are in vertically adjacent layers of the base substrate, as recited in claim 19. Claims 8, 14 and 20-22 are objected to as allowable because of their dependence from a claim with allowable subject matter.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub. No. 2021/0166751A1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
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/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 2/17/2026