Detailed Office Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restriction
Applicant’s election without traverse of claims 1-7, 21-27, and 34-39 in the reply filed on 11 October 2025 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5, 21-27, 34-36, and 39
Claims 1-5, 21-27, 34-36, and 39 are rejected under 35 U.S.C. 103 as being unpatentable over Liff et al. (2002/0286871; “Liff”) in view of Chen et al. (2020/0365544; “Chen”).
Regarding claim 1, Liff discloses in figure 4D, and related figures and text, for example, Liff – Selected Text, embodiments of semiconductor packages in which dies 130-1, 130-2, and 130-3 are disposed above and connected to die 108, for example, by redistribution layers; and Liff discloses in 4D that dies 130-1, 130-2, and 130-3 are separated by pillars (shown but not labeled). Liff, figure 4D, and related figures and text, for example, Liff – Selected Text.
Liff – Figure 4D
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[0022] Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a first die comprising a first face and a second face; and a second die, the second die comprising a first face and a second face, wherein the second die further comprises a plurality of first conductive contacts at the first face and a plurality of second conductive contacts at the second face, and the second die is between first-level interconnect contacts of the microelectronic assembly and the first die. In some embodiments, a microelectronic assembly may include a backside illuminated image sensor comprising a pixel array layer and a logic layer; and a double-sided die coupled to the logic layer by interconnects, wherein the logic layer is between the double-sided die and the pixel array layer. In still some embodiments, a microelectronic assembly may include a photonic receiver; and a die coupled to the photonic receiver by interconnects, wherein the die comprises a device layer between a first interconnect layer of the die and a second interconnect layer of the die. In still some embodiments, a microelectronic assembly may include a photonic transmitter; and a die coupled to the photonic transmitter by interconnects, wherein the die comprises a device layer between a first interconnect layer of the die and a second interconnect layer of the die.
[0030] The microelectronic assembly 100 may include a double-sided die 130-1 coupled to a die 102 at a first face 104 of the die 102 and at a first face 132-1 of the double-sided die 130-1 by die-to-die (DTD) interconnects 140-1. In particular, the first face 104 of die 102 may include a set of conductive contacts 118-1 and the first face 132-1 of the double-sided die 130-1 may include a set of conductive contacts 136-1. The conductive contacts 118-1 at the first face 104 of die 102 may be electrically and mechanically coupled to the conductive contacts 136-1 at the first face 132-1 of the double-sided die 130-1 by DTD interconnects 140-1. The first face 104 of die 102 may also include conductive contacts 116 to electrically couple the die 102 to one or more interconnect structures 114 of a routing layer, such as a redistribution layer (RDL) 112 shown in the embodiment of FIG. 1. The double-sided die 130-1 may also include conductive contacts 138-1 at a second face 134-1 of the double-sided die 130-1. The conductive contacts 138-1 at the second face 134-1 of the die 130-1 may electrically couple the die double-sided 130-1 to one or more interconnect structures 114 of the redistribution layer 112. In some embodiments, die 102 may also be a double-sided die.
[0071] Any suitable techniques may be used to manufacture the microelectronic assemblies disclosed herein. For example, FIGS. 4A-4E are side, cross-sectional views of various stages in an example process for manufacturing the microelectronic assembly of FIG. 1, in accordance with various embodiments. Although the operations discussed below with regard to FIGS. 4A-4E (and others of the accompanying drawings representing manufacturing processes) are illustrated in a particular order, these operations may be performed in any suitable order. Additionally, although particular assemblies are illustrated in FIGS. 4A-4E (and others of the accompanying drawings representing manufacturing processes), the operations discussed below with reference to FIGS. 4A-4E may be used to form any suitable assemblies. In some embodiments, microelectronic assemblies manufactured in accordance with the process of FIGS. 4A-4E may have DTD interconnects 140 that may be non-solder interconnects (e.g., metal-to-metal interconnects or anisotropic conductive material interconnects). In the embodiment of FIGS. 4A-4E dies 102/130 may first be assembled into a “composite die,” and then the composite die may be coupled to the package substrate 160. In general, a composite die may refer to a semiconductor structure in which multiple dies may be coupled together and assembled such that the assembly can be treated as a single die. In particular, the assembly may have a planar surface with conductive contacts for first-level interconnects. This approach may allow for tighter tolerances in the formation of DTD interconnects 140, and may be particularly desirable for integrating relatively small dies into a composite die assembly.
[0091] In another example, the die 102 in a microelectronic assembly 100 may be a processing device (e.g., a central processing unit, a graphics processing unit, a FPGA, a modem, an applications processor, etc.), and the die 130-1 may include high bandwidth memory, transceiver circuitry, and/or input/output circuitry (e.g., Double Data Rate transfer circuitry, Peripheral Component Interconnect Express circuitry, etc.). In another example, the die 102 in a microelectronic assembly 100 may be a cache memory (e.g., a third level cache memory), and one or more dies 130 may be processing devices (e.g., a central processing unit, a graphics processing unit, a FPGA, a modem, an applications processor, etc.) that share the cache memory of the die 102.
Further regarding claim 1, Chen discloses in figure 2A, and related figures and text, for example, Chen – Selected Text, embodiments of optical semiconductor packages to which are attached optical fibers 207, via die 200 which in turn is stacked above and connect to die 100; and Chen discloses stacked and overlaid conductive pillars, for example, 103. Chen, figure 2A, and related figures and text, for example, Chen – Selected Text
Chen – Figure 2A
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[0020] Referring to FIG. 1, the semiconductor package structure 10A may include a first semiconductor die 100 and a second semiconductor die 200. The first semiconductor die 100 has an active surface 100A and a passive surface 100P opposite to the active surface 100A. The active surface 100A of the first semiconductor die 100 is the surface formed with the active devices (not shown) of the first semiconductor die 100. Conductive bumps 1001 are in proximity to, adjacent to, or embedded in and exposed at active surface 100A, serving as a medium for signal input/output, wherein each conductive bumps 1001 electrically and mechanically connects a bonding pad (not shown) of the first semiconductor die 100 and the redistribution layer (RDL) 102R. Thereby, the signals from the first semiconductor die 100 can be transmitted to the second semiconductor die 200 via the conductive bumps 1001 and the RDL 102R.
[0021] As illustrated in FIG. 1A, a plurality of conductive elements 103 are disposed beside, or leveled with, the first semiconductor die 100. By leveling with the first semiconductor die 100, a bottom of each of the conductive elements may be coplanar with a bottom of the first semiconductor die 100. In some embodiments, a bottom of each of the conductive elements and a bottom of the first semiconductor die 100 are both disposed on a top surface of the RDL 101R. In some embodiments, molding compound 105 encapsulates the first semiconductor die 100 and the conductive elements 103. In some embodiments, the conductive element 103 can be a copper pillar or a through package via (TPV). RDL 102R over the first semiconductor die 100 is disposed to be closer to the active surface 100A than the passive surface 100P. RDL 101R under the first semiconductor die 100 is disposed to be closer to the passive surface 100P than the active surface 100A. Substrate 300 is disposed to be closer to the passive surface 100P than the active surface 100A. Conductive traces 1021R and 1022R in the RDL 102R can be configured in a fan-out structure with respect to the first semiconductor die 100, in which a projection area of the conductive trances 1021R and 1022R in the RDL 102R may be greater than a projection area of the first semiconductor die 100. Conductive traces 1011R in the RDL 101R may be connected to the passive surface 100P of the first semiconductor die 100. Conductive traces 1012R in the RDL 101R may be connected to the bottom of the conductive elements 103 encapsulated in the molding compound 105.
[0022] By having the electrical connection exemplified in FIG. 1A, the signals from the conductive terminals 301 can be transmitted to the RDL 101R via signal line 1011S in the substrate 300 and the conductive terminal 1011. The signals may be further transmitted from the RDL 101R to the first semiconductor die 100 via conductive element 103, RDL 102R, and conductive bump 1001 at the active surface 100A of the first semiconductor die 100. Similarly, the signal may be further transmitted from the first semiconductor die 100 to the second semiconductor die 200 via the RDL 102R, as previously discussed.
[0038] Referring to FIG. 2A, FIG. 2A illustrates a cross-sectional view of a semiconductor package structure 20A according to some embodiments of the present disclosure. The second semiconductor die 200 in the semiconductor package structure 20A can be a PIC having a waveguide layer 203, for example, disposed in proximity to the active surface 200A. The semiconductor package structure 20A further includes an optical fiber 207 optically coupled to the waveguide layer 203 through, for example, a pair of reflectors 209A, 209B, and a coupler 205. As shown in FIG. 2A, the optical fiber 207 is disposed over a passive surface 200P of the second semiconductor die 200. Reflector 209A can be machined in the body of the second semiconductor die 200 by a MEMS procedure so as to alter the optical path from a horizontal direction to a vertical direction, for example. The optical path is then altered again at the reflector 209B machined in the coupler 205 from a vertical direction to a horizontal direction, and subsequently propagating into the optical fiber 207. To reduce optical loss, boundaries between the passive surface 200P of the second semiconductor die 200 and the coupler 205 may father include a layer of anti-reflective coating (ARC) (not shown).
[0039] Referring to FIG. 2B, FIG. 2B illustrates a cross-sectional view of a semiconductor package structure 20B according to some embodiments of the present disclosure. Semiconductor package structure 20B may be substantially similar to the semiconductor package structure 20A except that the optical fiber 207 optically couples to the waveguide 203 from a lateral direction through an overhang portion 200H of the second semiconductor die 200. The overhang portion 200H of the second semiconductor die 200 can be an edge portion hanging over a sidewall of the first package 1071. Since the coupler 205 may be leveled with the waveguide layer 203, a kink 200K is machined at the active surface 200A of the second semiconductor die 200, or the PIC, in order to accommodate the coupler 205 which attached to the optical fiber 207. Fabrication of the second semiconductor die 200 may include dicing a PIC wafer into individual PIC units with sufficient width and subsequently aligning PIC unit with the first package 1071 to form the overhang portion 200H.
Consequently, in light of Chen’s disclosures of optical semiconductor packages, it would have been obvious to one of ordinary skill in the art to modify Liff’s embodiments to disclose: an optical device, comprising: a processing component; a first electronic component disposed over and electrically connected to the processing component; a second electronic component disposed over the processing component and electrically connected to the first electronic component; a first pillar disposed between the first electronic component and the second electronic component and electrically connected to the processing component; and an encapsulant disposed over the processing component, wherein the encapsulant encapsulates the first electronic component, the second electronic component, and the first pillar; Liff, figure 4D, and related figures and text, for example, Liff – Selected Text; Chen, figure 2A, and related figures and text, for example, Chen – Selected Text; because the resultant configuration would facilitate enhancing the efficiencies of electronic devices; Ziff, paragraph [0023]; for example, that provide high-speed signal transmission. Chen, paragraph [0018].
Regarding claims 2-5, 21-27, 34-36, and 39, as dependent upon claim 1, it would have been obvious to one of ordinary skill in the art to modify Ziff in view of Chen, as applied in the rejection of claim 1, to disclose:
2. The optical device as claimed in claim 1, further comprising a second pillar disposed around the processing component and electrically connected to the first pillar. Liff, figure 4D, and related figures and text, for example, Liff – Selected Text; Chen, figure 2A, and related figures and text, for example, Chen – Selected Text.
3. The optical device as claimed in claim 2, further comprising a first redistribution layer (RDL), disposed between the processing component and the first electronic component, and electrically connected to the first pillar and the second pillar. Liff, figure 4D, and related figures and text, for example, Liff – Selected Text; Chen, figure 2A, and related figures and text, for example, Chen – Selected Text.
4. The optical device as claimed in claim 3, further comprising a third pillar disposed over and electrically connected to the first RDL, wherein a projection of the third pillar at least partially overlaps a projection of the second pillar from a top view perspective. Liff, figure 4D, and related figures and text, for example, Liff – Selected Text; Chen, figure 2A, and related figures and text, for example, Chen – Selected Text.
5. The optical device as claimed in claim 3, wherein the processing component is electrically connected to the first electronic component through the first RDL. Liff, figure 4D, and related figures and text, for example, Liff – Selected Text; Chen, figure 2A, and related figures and text, for example, Chen – Selected Text.
21. The optical device as claimed in claim 1, wherein the first electronic component, the second electronic component, and the first pillar are located within a projection of the processing component from a top view perspective. Liff, figure 4D, and related figures and text, for example, Liff – Selected Text; Chen, figure 2A, and related figures and text, for example, Chen – Selected Text.
22. The optical device as claimed in claim 21, wherein the first electronic component comprises at least a digital signal processing unit electrically connected to the second electronic component, and the second electronic component comprises at least one transimpedance amplifier (TIA) unit, and at least one driver (DRV) unit, or a combination thereof. Liff, figure 4D, and related figures and text, for example, Liff – Selected Text; Chen, figure 2A, and related figures and text, for example, Chen – Selected Text.
23. The optical device as claimed in claim 1, further comprising a photonic component disposed over the first electronic component, wherein the first electronic component, the second electronic component, and the processing component are located within a projection of the photonic component from a top view perspective. Liff, figure 4D, and related figures and text, for example, Liff – Selected Text; Chen, figure 2A, and related figures and text, for example, Chen – Selected Text.
24. The optical device as claimed in claim 2, wherein the second pillar is configured to transmit a power to the processing component and the first electronic component. Liff, figure 4D, and related figures and text, for example, Liff – Selected Text; Chen, figure 2A, and related figures and text, for example, Chen – Selected Text.
25. The optical device as claimed in claim 24, further comprising: a first RDL disposed under the processing component and electrically connected to the first pillar; and a second RDL disposed over the first electronic component and electrically connected to the first RDL, wherein the second pillar is configured to transmit the power from the first RDL to the second RDL. Liff, figure 4D, and related figures and text, for example, Liff – Selected Text; Chen, figure 2A, and related figures and text, for example, Chen – Selected Text.
26. The optical device as claimed in claim 25, wherein the first pillar is disposed around the first electronic component and electrically connected to the second pillar and the second RDL, wherein the first pillar is configured to transmit the power from the first pillar to the second RDL. Liff, figure 4D, and related figures and text, for example, Liff – Selected Text; Chen, figure 2A, and related figures and text, for example, Chen – Selected Text.
27. The optical device as claimed in claim 3,further comprising a first RDL disposed between the processing component and the first electronic component, wherein a first part of the first RDL is configured to transmit power to the processing component or the first electronic component, a second part of the first RDL is configured to transmit an electrical signal between the processing component and the first electronic component, and the first part of the first RDL is electrically insulated from the second part of the first RDL. Liff, figure 4D, and related figures and text, for example, Liff – Selected Text; Chen, figure 2A, and related figures and text, for example, Chen – Selected Text.
34. The optical device as claimed in claim 4, further comprising a fourth pillar disposed between and electrically connected to the processing component and the first electronic component, wherein the second pillar is configured to transmit a power to the processing component and the first electronic component, wherein the fourth pillar is configured to transmit an electrical signal between the processing component and the first electronic component. Liff, figure 4D, and related figures and text, for example, Liff – Selected Text; Chen, figure 2A, and related figures and text, for example, Chen – Selected Text.
35. The optical device as claimed in claim 34, further comprising a second encapsulant disposed under the first electronic component, wherein the second encapsulant encapsulates the processing component, the second pillar, and the fourth pillar. Liff, figure 4D, and related figures and text, for example, Liff – Selected Text; Chen, figure 2A, and related figures and text, for example, Chen – Selected Text.
36. The optical device as claimed in claim 35, wherein the first encapsulant encapsulates the third pillar, wherein the first encapsulant is spaced apart from the second encapsulant by the first RDL. Liff, figure 4D, and related figures and text, for example, Liff – Selected Text; Chen, figure 2A, and related figures and text, for example, Chen – Selected Text.
39. The optical device as claimed in claim 4, wherein the third pillar is laterally separated from the first pillar by the first encapsulant, and wherein a diameter of the third pillar is less than a diameter of the first pillar. Liff, figure 4D, and related figures and text, for example, Liff – Selected Text; Chen, figure 2A, and related figures and text, for example, Chen – Selected Text.
because the resultant configurations would facilitate enhancing the efficiencies of electronic devices; Ziff, paragraph [0023]; for example, that provide high-speed signal transmission. Chen, paragraph [0018].
Claims 6 and 7
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Liff et al. (2002/0286871; “Liff”) in view of Chen et al. (2020/0365544; “Chen”), as applied in the rejection of claims 1-5, 21-27, 34-36, and 39, and further in view of Zarbock et al. (2014/0029639; “Zarbock”).
Regarding claims 6 and 7, Zarbock discloses in figures 5, and related figures and text, embodiments of optical devices comprising heat sinks. Zarbock, figure 5 and paragraph [0046] (“The heat sink 132 (FIG. 5) may be made of any suitable material such as copper for example, which facilitates drawing heat energy from the dies 102 and 150 and radiating that heat energy away from the package 102. As shown in FIG. 5 and FIG. 6d, a cross-sectional view as viewed along the line 6d-6d of FIG. 5, a top surface 250 of the heat sink 132 may extend over substantially all of the backside 114 of the die 102 to facilitate radiating heat drawn from the dies 102 and 150. A bottom surface 252 (FIG. 5) of the heat sink 132 with the exception of the heat sink cavity 130 which receives the optical coupler 120, extends over and is in thermal contact with most of the backside 114 of the die 102 to facilitate drawing heat energy from the dies 102 and 150. In the illustrated embodiment, the heat sink bottom surface 252 covers those areas of the die 102 (and indirectly the die 150) which generate most of the heat energy.”).
Consequently, it would have been obvious to one of ordinary skill in the art to modify Ziff in view of Chen, as applied in the rejection of claims 1-5, 21-27, 34-35, and 39, to disclose:
6. The optical device as claimed in claim 1, further comprising: a photonic component disposed over the first electronic component; and a heat dissipation structure disposed on the photonic component, wherein the photonic component dissipates heat along a first direction towards the heat dissipation structure in a first rate, and dissipates heat along a second direction opposite to the first direction in a second rate less than the first rate. Liff, figure 4D, and related figures and text, for example, Liff – Selected Text; Chen, figure 2A, and related figures and text, for example, Chen – Selected Text; Zarbock, figure 5 and paragraph [0046].
7. The optical device as claimed in claim 6, wherein the heat dissipation structure is configured to reduce a heat accumulation in the processing component. Liff, figure 4D, and related figures and text, for example, Liff – Selected Text; Chen, figure 2A, and related figures and text, for example, Chen – Selected Text; Zarbock, figure 5 and paragraph [0046].
because the resultant configurations would facilitate managing thermal loads; Zarbock, figure 5 and paragraph [0046]; while enhancing the efficiencies of electronic devices; Ziff, paragraph [0023]; for example, that provide high-speed signal transmission. Chen, paragraph [0018].
Claims 37 and 38
Claims 37 and 38, as dependent upon claim 6, are rejected under 35 U.S.C. 103 as being unpatentable over Liff et al. (2002/0286871; “Liff”) in view of Chen et al. (2020/0365544; “Chen”), as applied in the rejection of claims 1-5, 21-27, 34-36, and 39, and further in view of Zarbock et al. (2014/0029639; “Zarbock”), as applied in the rejection of claims 6 and 7, and further in view of Islam et al. (2021/0225824; “Islam”)
Regarding claims 37 and 38, Islam discloses in figure 2B embodiment of optical semiconductor configurations comprising, “[A] plurality of optical lens 302 may be attached to plurality of second semiconductor dies 108. For example, as illustrated in FIG. 2C, which is a top view of the structure shown FIG. 2B, optical lens 302 are attached along the side surfaces 108SD of the second semiconductor dies 108 to form a lens array. For example, a plurality of optical lens 302 are attached to the side surface 108SD of each second semiconductor die 108 to form the lens array. Referring back to FIG. 2B, a plurality of optical fibers 304 may be attached to the side surfaces 108SD of each of the second semiconductor dies 108 through the plurality of optical lens 302. In some embodiments, light transmitted in the optical fibers 304 is projected onto the optical lens 302, and/or the light emitted out of the optical lens 302 is received by the optical fibers 304.” Islam, paragraph [0034].
37. The optical device as claimed in claim 6, further comprising an optical fiber array component coupled to the photonic component, wherein the optical fiber array component is located outside of a projection of the processing component from a top view perspective. Islam, figure 2B and paragraph [0034]; Liff, figure 4D, and related figures and text, for example, Liff – Selected Text; Chen, figure 2A, and related figures and text, for example, Chen – Selected Text; Zarbock, figure 5 and paragraph [0046].
38. The optical device as claimed in claim 37, wherein the optical fiber array component non-overlaps the processing component laterally from a cross-sectional view, and wherein the optical fiber array component includes a plurality of fiber array units (FAUs) and a waveguide. Islam, figure 2B and paragraph [0034]; Liff, figure 4D, and related figures and text, for example, Liff – Selected Text; Chen, figure 2A, and related figures and text, for example, Chen – Selected Text; Zarbock, figure 5 and paragraph [0046].
because the resultant configurations would facilitate managing thermal loads; Zarbock, figure 5 and paragraph [0046]; while enhancing the efficiencies of electronic devices; Ziff, paragraph [0023]; for example, that provide high-speed signal transmission. Chen, paragraph [0018] and Islam, paragraph [0056].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER RADKOWSKI whose telephone number is (571)270-1613. The examiner can normally be reached on M-Th 9-5. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas Hollweg, can be reached on (571) 270-1739. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/PETER RADKOWSKI/Primary Examiner, Art Unit 2874