Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
1. Applicant’s arguments, filed January 12th, 2026, with respect to the rejections of the independent claims under 35 U.S.C. 102 have been fully considered and are persuasive in light of the claim amendments. Therefore, the rejections have been withdrawn. However, upon further consideration, new grounds of rejection are made in view of Roussel et al (US 2014/0189311).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 1-13 and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Corbal et al (US 2016/0179522, herein Corbal, cited in the IDS dated January 11th, 2024) in view of Roussel et al (US 2014/0189311, herein Roussel).
Regarding claim 1, Corbal teaches an apparatus comprising:
decoder circuitry to decode an instance of a single instruction, the single instruction to include one or more fields for an opcode, a destination operand identifier, a first source operand identifier, a second source operand identifier, and an immediate, (Fig 21, [0095], [0173-0176], [0186], [0188], decoder, instructions, source registers including vectors to be operated on, immediate values), wherein the opcode is to indicate execution circuitry is to interleave data elements from the identified first and second source operands according to an encoding of the immediate wherein the encoding of the immediate to include multiple controls with each control dictating what is to be written into a particular data element position of the identified destination operand ([0175-0186], vector instruction to interleave elements from source operands based on values of the immediate, different immediate bits control different element operations);
execution circuitry to execute the decoded instruction according to the opcode ([0173], execution logic).
Corbal fails to teach wherein a first set of two bits of the immediate is to indicate what data element position of the first source operand or the second source operand is to be stored in a first data element position of the destination operand, a second set of two bits of the immediate is to indicate what data element position of the first source operand or the second source operand is to be stored in a second data element position of the destination operand, a third set of two bits of the immediate is to indicate what data element position of the first source operand or the second source operand is to be stored in a third data element position of the destination operand, and a fourth set of two bits of the immediate is to indicate what data element position of the first source operand or the second source operand is to be stored in a fourth data element position of the destination operand.
Roussel teaches an apparatus comprising decoder circuitry to decode an instruction including an immediate wherein a first set of two bits of the immediate is to indicate what data element position of the first source operand or the second source operand is to be stored in a first data element position of the destination operand, a second set of two bits of the immediate is to indicate what data element position of the first source operand or the second source operand is to be stored in a second data element position of the destination operand, a third set of two bits of the immediate is to indicate what data element position of the first source operand or the second source operand is to be stored in a third data element position of the destination operand, and a fourth set of two bits of the immediate is to indicate what data element position of the first source operand or the second source operand is to be stored in a fourth data element position of the destination operand ([0034-0035], 8-bit immediate value, each set of two bits controls which data element of an operand are shuffled into the destination register).
Regarding claim 2, the combination of Corbal and Roussel teaches the apparatus of claim 1, wherein the field for the identifier of the first source operand is to identify a vector register (Corbal [0157], [0165], source vector registers).
Regarding claim 3, the combination of Corbal and Roussel teaches the apparatus of claim 1, wherein the field for the identifier of the first source operand is to identify a memory location (Corbal [0188], source as memory location).
Regarding claim 4, the combination of Corbal and Roussel teaches the apparatus of claim 1, wherein two bits of the immediate are to be used as element selectors for a 4:1 multiplexer (Corbal [0175], multiplexers to perform element selection).
Regarding claim 5, the combination of Corbal and Roussel teaches the apparatus of claim 1, wherein the data elements to interleave of the identified first and second source operands are 32-bit in size (Corbal [0082], 32-bit data elements).
Regarding claim 6, the combination of Corbal and Roussel teaches the apparatus of claim 1, wherein the data elements to interleave of the identified first and second source operands are 64-bit in size (Corbal [0082], 64-bit data elements).
Regarding claim 7, the combination of Corbal and Roussel teaches the apparatus of claim 1, wherein the apparatus is a digital signal processing core (Corbal [0125], [0137], DSP).
Claims 8-13 refer to a method embodiment of the apparatus embodiment of claims 1-7. Therefore, the above rejections for claims 1-6 are applicable to claims 8-13.
Claims 15-20 refer to a system embodiment of the apparatus embodiment of claims 1-6. Therefore, the above rejections for claims 1-6 are applicable to claims 15-20.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ould-Ahmed-Vall (US 2018/0074822) discloses a processor wherein an index value of an immediate has a number of bits sufficient to identify a data element to be permuted into a destination register.
Ould-Ahmed-Vall (US 2017/0235516) discloses a processor including shuffle logic to copy elements into a position of a destination register according to one, two, or four bits of an immediate value.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MICHAEL J METZGER/ Primary Examiner, Art Unit 2183