Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I and Species A in the reply filed on 5/7/2025 is acknowledged.
Claim 12 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention and/or species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 5/7/2025. Claims 1-11, 13-14, and 21-26 are examined in this office action.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: "Nonvolatile memory structure incorporating capacitor, RRAM, PCRAM, or FERAM".
Claim Objections
Claim 5 is objected to because of the following informalities: the phrase "a first etch stop layer between the first electrode and the first dielectric layer and surround. Appropriate correction is required.
Claim 21 is objected to because of the following informalities: Claim 21 recites "an electrode; a first conductive via; and an insulating layer between the electrode and the f The claim language is unclear when considered in view of the disclosure. The Applicant Arguments/Remarks filed on 5/7/2025 state that for Claim 21, “supporting grounds can be found in at least FIG. 1G of the present application as filed”. However, in Fig. 1G it is unclear which of the structures (112, 134) on either side of the insulating layer (132) serves as an electrode and which serves as a first conductive via. Throughout the specification, both structures 112 and 134 are established to be electrodes and subsequently only referred to as electrodes. This leaves at least two interpretations of Claim 21 in view of Fig. 1G, an issue that further complicates the interpretation of claims dependent on Claim 21. For the purpose of this action, structure 112 of Fig. 1G has been interpreted as the electrode of Claim 21. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 24 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 24, line 4 recites the limitation "a fourth dielectric layer extending in the first region and the second region to surround the second conductive line and the third conductive line". The Applicant Arguments/Remarks filed on 5/7/2025 state that for Claim 24, “supporting grounds can be found in at least FIG. 1G of the present application as filed”. However, FIG. 1G as submitted does not teach the fourth dielectric layer described in the claim. Further, neither the claims nor the specification as submitted on the application filing date make mention of a fourth dielectric layer.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4-7, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by EP 1 020 905 A1 (Sung).
Regarding Claim 1, Sung teaches a semiconductor device (Fig. 1, 20), comprising:
a first electrode (44);
a first dielectric layer (42) on the first electrode;
a second electrode (49) in the first dielectric layer; and
an insulating layer (46) in the first dielectric layer and between the second electrode and the first electrode and between the second electrode and the first dielectric layer (46 between 49 and 42), wherein the first electrode and the second electrode are electrically isolated by the insulating layer (46 between 42 and 49).
Regarding Claim 4, Sung teaches the semiconductor device of claim 1 (as stated above), wherein the insulating layer surrounds a sidewall of the second electrode (Fig. 1, 46 surrounds sidewalls of upper electrode 49).
Regarding Claim 5, Sung teaches the semiconductor device of claim 1 (as stated above), further comprising a first etch stop layer (Fig. 1, 40) between the first electrode (44) and the first dielectric layer (42) and surrounds a portion of the insulating layer between the first electrode and the second electrode (40 surrounds a portion of 46).
Regarding Claim 6, Sung teaches the semiconductor device of claim 1 (as stated above), wherein a surface of the second electrode (Fig. 1, 49) is substantially coplanar with surfaces of the insulating layer (46) and the first dielectric layer (42).
Regarding Claim 7, Sung teaches the semiconductor device of claim 1 (as stated above), wherein the insulating layer (Fig. 1, 46) is in direct contact with the first electrode (44) and the second electrode (49).
Regarding Claim 21, Sung teaches a semiconductor device, comprising:
a MIM structure in a first region (24), comprising
an electrode (49);
a first conductive via (34); and
an insulating layer (46) between the electrode and the first conductive (46 between 49 and 34) via along a first direction;
a first interconnect structure (22) in a second region, comprising:
a first conductive line (27); and
a second conductive via (36) on the first conductive line along the first direction;
a first dielectric layer (42) extending in the first region and the second region to surround the electrode and the first conductive line; and
a second dielectric layer (32) extending in the first region and the second region to surround the first conductive via and the second conductive via (32 surrounds 34 and 36).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over EP 1 020 905 A1 (Sung) in view of US 2020/0136038 A1 (Manfrini) and further in view of US 6,281,535 B1 (Ma).
Regarding Claim 2: The semiconductor device of claim 1, wherein the insulating layer comprises a resistance variable material, a phase change material or a ferroelectric material.
Sung teaches the semiconductor device of claim 1 (as stated above).
Sung does not teach wherein the insulating layer comprises a resistance variable material, a phase change material or a ferroelectric material.
However, Sung teaches “In ICs such as dynamic random access memory (DRAM), capacitors are used for storage in the memory cells.” ([0003])
Also, Manfrini teaches an intercalated metal/dielectric structure for nonvolatile memory devices (title) and a memory element (Fig. 9, 504) serving as a nonvolatile memory device such as an RRAM device, which can also take other forms such as a phase-change memory (PCRAM) element, or a MIM capacitor ([0047]).
Further, Ma teaches a ferroelectric capacitor structure for nonvolatile random access memory cell (title) and that preferably “. . . the capacitor dielectric is a ferrous-electric material . . .” (abstract).
While attempting to create a nonvolatile memory device, one skilled in the art could refer to Sung while designing a structure including the two electrodes and insulating layer. Then, motivated by Sung’s description of capacitors as storage in memory cells (or otherwise obtaining this information which is common in the art), one could reference and incorporate Manfrini – using a resistance variable material to form an RRAM device, or a phase-change material to form a PCRAM element.
Alternatively, motivated to improve the RAM memory cell structure inspired by Sung, one could incorporate Ma and use a ferroelectric material as the capacitor dielectric layer.
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to arrive at the claimed invention having combined the teachings of Sung, Manfrini, and Ma and/or as a matter of routine experimentation per MPEP 2144.05.
Regarding Claim 3: The semiconductor device of claim 1, wherein the first electrode, the second electrode and the insulating layer form a capacitor, a RRAM, a PCRAM or a FERAM.
Sung teaches the semiconductor device of claim 1 (as stated above), wherein the first electrode (44), the second electrode (49) and the insulating layer form a capacitor (Fig. 1, 24).
Sung does not teach . . . a RRAM, a PCRAM, or a FERAM.
However, Sung teaches “In ICs such as dynamic random access memory (DRAM), capacitors are used for storage in the memory cells.” ([0003])
Also, Manfrini teaches a memory element (Fig. 9, 504) serving as a nonvolatile memory device such as an RRAM device, which can also take other forms such as a phase-change memory (PCRAM) element, or a MIM capacitor ([0047]).
Further, Ma teaches a ferroelectric capacitor structure for nonvolatile random access memory cell (title) and that “Preferably . . . the capacitor dielectric is a ferrous-electric material . . .” (abstract).
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to arrive at the claimed invention having combined the teachings of Sung, Manfrini, and Ma motivated by the reason stated above and/or as a matter of routine experimentation per MPEP 2144.05.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over EP 1 020 905 A1 (Sung) in view of US 2019/0115394 A1 (Liu).
Regarding Claim 8: The semiconductor device of claim 1, wherein the insulating layer is in direct contact with the first dielectric layer.
Sung teaches the semiconductor device of claim 1 (as stated above).
Sung does not teach wherein the insulating layer is in direct contact with the first dielectric layer.
However, Liu teaches a semiconductor structure including a RRAM (abstract) wherein the insulating layer (Fig. 7, 142) is in direct contact with the first dielectric layer (120).
While attempting to create a nonvolatile memory device, one skilled in the art could refer to Sung while designing a structure including the second electrode, insulating layer, and first dielectric layer. Then, motivated by Sung’s description of capacitors as storage in memory cells (or otherwise obtaining this information which is common in the art), one could reference and incorporate Liu’s method for forming a random access memory device.
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to arrive at the claimed invention having combined the teachings of Sung and Liu and/or as a matter of routine experimentation per MPEP 2144.05.
Claims 9-11, 13-14, 23, 25, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over EP 1 020 905 A1 (Sung).
Regarding Claim 9: a semiconductor device, comprising:
a memory cell, comprising:
a first electrode in a first dielectric layer; and
a second electrode in a second dielectric layer on the first dielectric layer; and
a data storage layer disposed in the second dielectric layer and surrounding the second electrode;
a first conductive line in the first dielectric layer;
a first conductive via on the first conductive line in the second dielectric layer, wherein surfaces of the second electrode and the data storage layer are substantially coplanar with a surface of the first conductive via.
Sung teaches a semiconductor device (Fig. 1, 20), comprising:
a memory cell (24), comprising:
a first electrode (44) in a first dielectric layer (38); and
a second electrode (49) in a second dielectric layer (42) on the first dielectric layer; and
a data storage layer (46) disposed in the second dielectric layer and surrounding the second electrode;
a first conductive line (27) in the first dielectric layer;
a first conductive via (26) on the first conductive line.
Sung does not teach the first conductive line being in the first dielectric layer; or
the first conductive via being in the second dielectric layer, wherein surfaces of the second electrode and the data storage layer are substantially coplanar with a surface of the first conductive via.
However, Sung teaches “The skilled artisan would appreciate that a plurality of interconnect levels and vias will be present throughout the device and at multiple levels within the device. A via is an opening formed in an interlevel dielectric layer to expose a certain portion of an underlying metal line to allow electrical contact to be made to the line. A conductive contact is then formed in the via to connect the underlying metal line with a subsequently formed overlying metal line” ([0021]) which is also knowledge common in the art.
Sung also teaches the formation of the first conductive via and the first conductive line by the deposition of a conductive metal layer (Fig. 5, 54) which is subsequently planarized (Fig. 8) along with the capacitor structure (24), leaving surfaces of interconnect structure (22) and the second electrode (49) substantially coplanar with a surface of the surrounding dielectric layer (32).
While attempting to create a nonvolatile memory device, one skilled in the art could refer to Sung while designing a structure including a memory cell and interconnect structure. Then, motivated by Sung’s description of interconnect levels and vias being present throughout the device and at multiple levels within the device, one could incorporate an interconnect design including a conductive via in the second dielectric layer on a conductive line in the first dielectric layer. Following Sung’s method of forming the interconnect structure and capacitor, then planarizing both along with the second dielectric layer, the resultant structure would include surfaces of the second electrode and the data storage layer substantially coplanar with a surface of the first conductive via.
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to arrive at the claimed invention having referenced Sung, incorporated knowledge common in the art, and/or as a matter of routine experimentation per MPEP 2144.05.
Regarding Claim 10: The semiconductor device of claim 9, wherein a surface of the second dielectric layer is substantially coplanar with the surfaces of the second electrode, the data storage layer and the first conductive via.
Sung teaches the semiconductor device of claim 9 (as stated above), wherein a surface of the second dielectric layer (Fig. 1, 42) is substantially coplanar with the surfaces of the second electrode (49), the data storage layer (46).
Sung does not teach and the first conductive via.
However, motivated by the reason above and following the process described above, one skilled in the art could arrive at a structure wherein surfaces of the second dielectric layer, second electrode, data storage layer, and first conductive via are substantially coplanar.
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to arrive at the claimed invention having referenced Sung, incorporated knowledge common in the art, and/or as a matter of routine experimentation per MPEP 2144.05.
Regarding Claim 11: The semiconductor device of claim 9, further comprising a first conductive pattern in a third dielectric layer being in direct contact with the second electrode, and a second conductive pattern in the third dielectric layer being in direct contact with the first conductive via.
Sung teaches the semiconductor device of claim 9 (as stated above) further comprising a first conductive pattern (Fig. 1, 34) and a second conductive pattern (36) in a third dielectric layer (32).
Sung does not teach the first conductive pattern in direct contact with the second electrode, or the second conductive pattern in direct contact with the first conductive via.
However, Sung teaches “a plurality of interconnect levels and vias will be present throughout the device and at multiple levels within the device.” ([0021]) which is also a practice common in the art.
While attempting to create a nonvolatile memory device, one skilled in the art could refer to Sung while designing a structure including a memory cell and interconnect structure. Then, motivated by Sung’s description of interconnect levels and vias being present throughout the device and at multiple levels within the device, one could incorporate a multilevel interconnect design including a third dielectric layer with first and second conductive patterns. Using conductive patterns in one dielectric layer as direct contacts for interconnect structures and capacitors in a second dielectric layer is a practice common in the art.
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to arrive at the claimed invention having referenced Sung, incorporated knowledge common in the art, and/or as a matter of routine experimentation per MPEP 2144.05.
Regarding Claim 13: The semiconductor device of claim 11, wherein first surfaces of the first conductive pattern, the second conductive pattern and the third dielectric layer are substantially coplanar, and second surfaces opposite to the first surfaces of the first conductive pattern, the second conductive pattern and the third dielectric layer are substantially coplanar.
Sung teaches the semiconductor device of claim 11 (as stated above).
Sung does not teach wherein first surfaces of the first conductive pattern, the second conductive pattern and the third dielectric layer are substantially coplanar, and second surfaces opposite to the first surfaces of the first conductive pattern, the second conductive pattern and the third dielectric layer are substantially coplanar.
However, Sung teaches the formation of the first conductive via and the first conductive line by the deposition of a conductive metal layer (Fig. 5, 54) which is subsequently planarized (Fig. 8) along with the capacitor structure (24), leaving surfaces of interconnect structure (22) and the second electrode (49) substantially coplanar with a surface of the surrounding dielectric layer (32).
While attempting to create a nonvolatile memory device, one skilled in the art could refer to Sung while designing a structure including a memory cell and interconnect structure. Motivated by the reason above and following the process described above, one could arrive at a structure including a third dielectric layer with first and second conductive patterns. Finally, following Sung’s method of forming an interconnect structure in a dielectric layer and subsequently planarizing both, the resultant structure would include surfaces of the first and second conductive patterns substantially coplanar with surfaces of the third dielectric layer.
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to arrive at the claimed invention having referenced Sung, incorporated knowledge common in the art, and/or as a matter of routine experimentation per MPEP 2144.05.
Regarding Claim 14: The semiconductor device of claim 9, wherein the data storage layer is in direct contact with a sidewall and a surface of the second electrode, and the surface of the second electrode faces the first electrode.
Sung teaches the semiconductor device of claim 9 (as stated above), wherein the data storage layer (Fig. 1, 46) is in direct contact with a sidewall and a surface of the second electrode (49), and the surface of the second electrode faces the first electrode (surface of 49 faces 44)
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to arrive at the claimed invention having referenced Sung, incorporated knowledge common in the art, and/or as a matter of routine experimentation per MPEP 2144.05.
Regarding Claim 23: The semiconductor device of claim 21, further comprising:
a third conductive via on the first conductive via;
a fourth conductive via on the second conductive via; and
a third dielectric layer extending in the first region and the second region to surround the third conductive via and the fourth conductive via.
Sung teaches the semiconductor device of claim 21 (as stated above).
Sung does not teach further comprising:
a third conductive via on the first conductive via;
a fourth conductive via on the second conductive via; and
a third dielectric layer extending in the first region and the second region to surround the third conductive via and the fourth conductive via.
However, Sung teaches “a plurality of interconnect levels and vias will be present throughout the device and at multiple levels within the device.” ([0021]) which is also a practice common in the art.
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to arrive at the claimed invention having referenced Sung, incorporated knowledge common in the art, and/or as a matter of routine experimentation per MPEP 2144.05.
Regarding Claim 25: The semiconductor device of claim 23, wherein the first conductive via has a first width along a second direction substantially perpendicular to the first direction, and the third conductive via has a second width smaller than the first width along the second direction.
Sung teaches the semiconductor device of claim 23 (as stated above).
Sung does not teach wherein the first conductive via has a first width along a second direction substantially perpendicular to the first direction, and the third conductive via has a second width smaller than the first width along the second direction.
However, “stacked vias” with differing widths is a design common in the art.
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to arrive at the claimed invention having referenced Sung, incorporated knowledge common in the art, and/or as a matter of routine experimentation per MPEP 2144.05.
Regarding Claim 26: The semiconductor device of claim 23, wherein an interface between the first conductive via and the third conductive via is substantially coplanar with an interface between the second conductive via and the fourth conductive via and a surface of the third dielectric layer.
Sung teaches the semiconductor device of claim 23 (as stated above).
Sung does not teach wherein an interface between the first conductive via and the third conductive via is substantially coplanar with an interface between the second conductive via and the fourth conductive via and a surface of the third dielectric layer.
However, Sung teaches the formation of the first conductive via and the first conductive line by the deposition of a conductive metal layer (Fig. 5, 54) which is subsequently planarized (Fig. 8) along with the capacitor structure (24), leaving surfaces of interconnect structure (22) and the second electrode (49) substantially coplanar with a surface of the surrounding dielectric layer (32).
Sung also teaches “a plurality of interconnect levels and vias will be present throughout the device and at multiple levels within the device.” ([0021]) which is also a practice common in the art.
While attempting to create a nonvolatile memory device, one skilled in the art could refer to Sung while designing a structure including second dielectric layer with first and second vias. Then, using Sung’s description of depositing multiple conductive features and subsequently planarizing, one could arrive at a structure wherein subsequently layered material over the conductive structures results in coplanar interfaces.
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to arrive at the claimed invention having referenced Sung, incorporated knowledge common in the art, and/or as a matter of routine experimentation per MPEP 2144.05.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over EP 1 020 905 A1 (Sung) in view of US 6,180,976 (Roy).
Regarding Claim 22: the semiconductor device of claim 21, wherein an interface between the electrode and the insulating layer is substantially coplanar with an interface between the first conductive line and the second conductive via.
Sung teaches the semiconductor device of claim 21 (as stated above).
Sung does not teach wherein an interface between the electrode and the insulating layer is substantially coplanar with an interface between the first conductive line and the second conductive via.
However, Roy teaches wherein an interface between the electrode (Fig. 1, 12) and the insulating layer (14) is substantially coplanar with an interface between the first conductive line (36) and the second conductive via (22).
While attempting to create a nonvolatile memory device, one skilled in the art could refer to Sung while designing a MIM structure in one region and an interconnect structure in a second region. Then, motivated by Sung’s description of capacitors as storage in memory cells (or otherwise obtaining this information which is common in the art), one could reference and incorporate Roy’s method for forming thin-film capacitors. Alternatively, one could reference Sung and incorporate a process common in the art: forming recesses in a dielectric layer, depositing conductive material over the entirety of the dielectric layer, and planarizing the material (as in Roy, Fig.’s 2-4) to form disparate, conductive structures with coplanar faces. Subsequently layering any material over the conductive structures results in coplanar interfaces.
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to arrive at the claimed invention having referenced Sung, incorporated Roy and/or as a matter of routine experimentation per MPEP 2144.05.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hsue (US 6,492,226 B1) teaches a method for forming a semiconductor device with a capacitor in a first region and an interconnect structure in a second region.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jesse Goss whose telephone number is (571) 272-5170. The examiner can normally be reached M-F 830-600.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JESSE M. GOSS/Examiner, Art Unit 2897
/JACOB Y CHOI/Primary Examiner, Art Unit 2897
Prosecution Insights