Prosecution Insights
Last updated: October 02, 2026
Application No. 17/857,049

SEMICONDUCTOR DEVICE INCLUDING EMBEDDED CAPACITOR OR MEMEORY CELL

Final Rejection §102
Filed
Jul 04, 2022
Examiner
ALAM, MOHAMMED R
Art Unit
2800
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
2 (Final)
90%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
519 granted / 580 resolved
+21.5% vs TC avg
Moderate +6% lift
Without
With
+6.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
23 currently pending
Career history
594
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
47.8%
+7.8% vs TC avg
§102
29.1%
-10.9% vs TC avg
§112
16.1%
-23.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 580 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Response to Arguments Applicant’s arguments, filed on 9/26/2025 with respect to amended claim independent claim(s) 1 and 21 have been fully considered and persuasive. Thereby, after conducting an updated search none of the prior arts of record, alone or in combination, discloses the claimed invention of independent claim(s) 1 and 21. Claims 1-3, 5-8, 21-24, and 26-29 are allowed. Applicant’s arguments with respect to amended independent claim(s) 9 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kunishima et al. (US publication 2015/0357335 A1), hereinafter referred to as Kunishima and response to the arguments have been fully incorporated into the claim rejection set forth below in this office action. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claim 9, 11, and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kunishima et al. (US publication 2015/0357335 A1), hereinafter referred to as Kunishima. Regarding claim 9, Kunishima teaches a semiconductor device (fig. 1 and related text), comprising: a substrate (SUB, [0031], fig. 1); a memory cell (fig. 1), comprising: a first electrode (LE, [0043]) in a first dielectric layer (DL2, [0034]), the first electrode having a first surface (bottom surface) facing the substrate and a second surface (side surface) opposite to the first surface; and a second electrode (UE, [0043]) in a second dielectric layer (ILD, [0035]) on the first dielectric layer (fig. 1), wherein the second dielectric layer covers the second surface of the first electrode (fig. 1); and a data storage layer (CDL, [0043]) disposed in the second dielectric layer and surrounding the second electrode (fig. 1); a first conductive line (CT2, [0034]) in the first dielectric layer; and a first conductive via (WR, [0037]) on the first conductive line in the second dielectric layer (fig. 1). Regarding claim 11, Kunishima teaches further comprising a first conductive pattern (CF) in a third dielectric layer ((ILD) being in direct contact with the second electrode, and a second conductive pattern (LWR, [0037]) in the third dielectric layer being in direct contact with the first conductive via (fig. 1). Regarding claim 14, Kunishima teaches wherein the data storage layer is in direct contact with a sidewall and a surface of the second electrode, and the surface of the second electrode faces the first electrode (fig. 1). Allowable Subject Matter Claims 1-3, 5-8, 21-24, and 26-29 are allowed. Claims 10 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The claims contain limitations that none of the prior art of record discloses, teaches or fairly suggests, alone or in combinations when taken in combination with all other limitations of the base claim and any intervening claims. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mohammed R Alam whose telephone number is 469-295-9205 and can normally be reached between 8:00am-6:00pm (M-F) or by e-mail via Mohammed.Alam1@uspto.gov. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached on 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOHAMMED R ALAM/Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Jul 04, 2022
Application Filed
Jun 18, 2025
Non-Final Rejection mailed — §102
Sep 26, 2025
Response Filed
Aug 13, 2026
Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12745417
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
3y 5m to grant Granted Sep 22, 2026
Patent 12727201
THIN FILM TRANSISTOR, THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THIN FILM TRANSISTOR
3y 4m to grant Granted Sep 01, 2026
Patent 12727141
VERTICAL GATE-ALL-AROUND (GAA) MEMORY CELL AND METHOD FOR FORMING THE SAME
2y 7m to grant Granted Sep 01, 2026
Patent 12718983
CAPACITOR, ELECTRONIC DEVICE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME
4y 5m to grant Granted Aug 25, 2026
Patent 12713738
LED STRUCTURE AND GAN-BASED SUBSTRATE THEREOF, AND METHOD FOR MANUFACTURING GAN-BASED SUBSTRATE
3y 5m to grant Granted Aug 18, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
90%
Grant Probability
96%
With Interview (+6.0%)
2y 2m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 580 resolved cases by this examiner. Grant probability derived from career allowance rate.

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