DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species C in the reply filed on 12/29/2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 9 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang et al. (US 20230005941 A1) hereinafter “Zhang”.
Regarding Claim 1, Figures 1-2C of Zhang teach: A semiconductor device (100; Figure 1A), including: a lower structure (114; Figure 1B) including a substrate (111; Figure 1B) and a peripheral circuit (113; Figure 1B) on the substrate; and an upper structure (112; Figure 1B) on the lower structure, wherein: the upper structure includes a stack structure (125; Figure 1B) including interlayer insulating layers (128 Figure 1B) and gate layers (126; Figure 1B), a vertical memory structure (124/184-2; Figure 1B) penetrating through the stack structure, a bit line (115; Figure 1B) electrically connected to the vertical memory structure and below the stack structure, a conductive pattern (130/178-2; Paragraph 0037; Figure 1B/2C) electrically connected to the vertical memory structure and on the stack structure, an upper insulating layer (132; Figure 1B) covering the conductive pattern, and a capping insulating layer (142; Figure 1B) on the upper insulating layer, the vertical memory structure includes an insulating core region (Core; See annotated Figure 2C of Zhang below; Paragraph 0038), a first pad pattern (195-2; Figure 2C) electrically connected to the conductive pattern and on the insulating core region, a dielectric structure (DS; See annotated Figure 2C of Zhang below; Paragraph 0038) on a side surface (left/right horizontally of “Core”) of the insulating core region and a side surface (bottom-side of “195-2”) of the first pad pattern, and a channel layer (194-2; Figure 2C) between the insulating core region and the dielectric structure and between the insulating core region and the first pad pattern (Figure 2C), and the channel layer includes a first portion (left/right horizontal sides of “194-2”; Figure 2C) contacting the dielectric structure, and a second portion (top vertical side of “194-2”; Figure 2C) extending from the first portion and between a lower surface (bottom vertically of “195-2”) of the first pad pattern and an upper surface (top vertically of “Core”; Figure 2C) of the insulating core region. [Examiner notes: The use of the claim language “on” does not require direct contact. Further, the claim language “a side surface” does not limit which side surface, therefore a bottom-side satisfies the claim language.]
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Annotated Figure 2C of Zhang
Regarding Claim 2, Figures 1-2C of Zhang teach: the channel layer (194-2; Paragraph 0058 where items 194-1 and 194-2 are equal to item 124) includes a silicon layer (Paragraph 0038 where the semiconductor channel of item 124 is silicon) contacting the lower surface of the first pad pattern (195-2; Figure 2C) and the upper surface of the insulating core region (top vertically of “Core”; See annotated Figure 2C above).
Regarding Claim 3, Figures 1-2C of Zhang teach: the dielectric structure (DS; See annotated Figure 2C of Zhang above) includes a first dielectric layer (Tunneling layer; Paragraph 0038), a second dielectric layer (Blocking layer; Paragraph 0038), and a data storage layer (Storage layer; Paragraph 0038) between the first dielectric layer and the second dielectric layer, and the dielectric structure contacts the side surface (bottom-side of “195-2”) of the first pad pattern (195-2).
Regarding Claim 5, Figures 1-2C of Zhang teach: the channel layer (194-2) includes an undoped region (Paragraph 0039), and a first doped region (Paragraph 0088; Where an implantation process is performed to dope the top portion of semiconductor channel (item 334). Figure 3E) contacting the first pad pattern (195-2) on the undoped region (Paragraph 0088; Where the remaining channel is undoped.), the first doped region and the first pad pattern have the same conductivity type (Paragraph 0088, N-type), the gate layers (126) include a plurality of lower gate electrodes (See annotated Figure 2C of Zhang below; Lower), a plurality of upper gate electrodes (See annotated Figure 2C of Zhang below; Upper, and a plurality of intermediate gate electrodes (See annotated Figure 2C of Zhang below; Intermediate) between the plurality of lower gate electrodes and the plurality of upper gate electrodes, the first doped region faces at least a portion of at least one of the plurality of upper gate electrodes (Paragraph 0088), and the undoped region faces the plurality of intermediate gate electrodes (Paragraph 0088).
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Annotated Figure 2C of Zhang
Regarding Claim 9, Figures 1-2C of Zhang teach: the first pad pattern (195-2; Figure 2C) extends into the conductive pattern (130/178-2; Paragraph 0037; Figure 1B/2C), and the conductive pattern covers an upper surface (top vertically of 195-2) of the first pad pattern and at least a portion (left/right horizontally of 195-2) of the side surface of the first pad pattern.
Regarding Claim 13, Figures 1-2C of Zhang teach: the vertical memory structure (124/184-2) penetrates the stack structure (125) and extends upwardly, and the first pad pattern (195-2) is on a level higher than a level of the stack structure (Figure 2C).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 20230005941 A1) hereinafter “Zhang” in view of Du et al. (US 20230367488 A1) hereinafter “Du”.
Regarding Claim 11, Figures 1-2C of Zhang teach: the gate layers (126) include a plurality of lower gate electrodes (See annotated Figure 2C of Zhang below; Lower), a plurality of upper gate electrodes (See annotated Figure 2C of Zhang below; Upper, and a plurality of intermediate gate electrodes (See annotated Figure 2C of Zhang below; Intermediate) between the plurality of lower gate electrodes and the plurality of upper gate electrodes, the plurality of intermediate gate electrodes include word lines (Paragraph 0036)
Zhang does not teach: a side surface of the vertical memory structure has a bent portion between the plurality of upper gate electrodes and the plurality of intermediate gate electrodes.
Figure 4A of Du teaches: a memory device (300; Figure 3) with a vertical memory structure (308) formed in a memory stack (404); wherein the vertical memory structure has a bent portion (Figure 4A)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a side surface of the vertical memory structure has a bent portion between the plurality of upper gate electrodes and the plurality of intermediate gate electrodes because Du teaches a memory structure can include a plurality of memory cells coupled in series and stacked vertically (Du Paragraph 0048).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 20230005941 A1) hereinafter “Zhang” in view of Du et al. (US 20230367488 A1) hereinafter “Du” and Lee “US 20220077182 A1” hereinafter “Lee.”
Regarding Claim 12, the combination of Zhang and Du teaches all of the limitations of the claimed invention as stated above.
Zhang does not teach: the vertical memory structure has an inclined side surface, such that a width thereof decreases upwardly on a level higher than a level of the bent portion.
Figure 3A of Lee teaches: a semiconductor memory device (Paragraph 0008) comprising a gate stack (G1) with vertical memory structures (CL) formed through the memory stack, w herein the vertical memory structure has an inclined side surface (Paragraph 0048), such that a width thereof decreases upwardly (Figure 3A; Paragraph 0048).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the vertical memory structure has an inclined side surface, such that a width thereof decreases upwardly on a level higher than a level of the bent portion because Lee teaches this tapered shape increases margin space toward the top of the gate stack (Lee Paragraph 0048).
Allowable Subject Matter
Claims 4, 6-8, 10 and 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 4, none of the prior art explicitly teaches, suggests, or motivates one having ordinary skill in the art to have the data storage layer has a bent portion on a level higher than a level of an uppermost gate layer among the gate layers along with the limitations of Claims 3 and 1.
Regarding Claim 6, none of the prior art explicitly teaches, suggests, or motivates one having ordinary skill in the art to have the channel layer further includes a second doped region below the undoped region, and the second doped region faces at least a portion of at least one of the plurality of lower gate electrodes along with the limitations of Claim 5 and 1.
Regarding Claim 10, none of the prior art explicitly teaches, suggests, or motivates one having ordinary skill in the art to have a buffer layer between an uppermost interlayer insulating layer among the interlayer insulating layers and the conductive pattern, wherein: the buffer layer covers at least a portion of the side surface of the first pad pattern, and the dielectric structure includes a portion extending to a region between the buffer layer and the first pad pattern along with the limitations of Claim 1.
Regarding Claim 14, none of the prior art explicitly teaches, suggests, or motivates one having ordinary skill in the art to have the first pad pattern has a first side surface inclined such that a width of the first pad pattern increases upwardly, and a second side surface on a level higher than a level of the first side surface, extending from the first side surface, and inclined such that a width of the first pad pattern decreases upwardly along with the limitations of Claims 13 and 1.
Regarding Claim 15, none of the prior art explicitly teaches, suggests, or motivates one having ordinary skill in the art to have the dielectric structure further includes a portion interposed between the first pad pattern and the stack structure along with the limitations of Claims 13 and 1.
Claims 16-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding Claim 16, none of the prior art explicitly teaches, suggests, or motivates one having ordinary skill in the art to have a second pad pattern contacting the channel layer and below the insulating core region along with the other limitations of Claim 16. Claims 17-18 are also allowable as they depend from and include all of the limitations of Claim 16.
Regarding Claim 19, none of the prior art explicitly teaches, suggests, or motivates one having ordinary skill in the art to have a second pad pattern below the insulating core region, the dielectric structure includes a first dielectric layer, a second dielectric layer, and a data storage layer between the first dielectric layer and the second dielectric layer, and the second dielectric layer includes a portion contacting the channel layer and a portion contacting the first pad pattern, and is spaced apart from the second pad pattern along with the other limitations of Claim 19. Claim 20 is also allowable as it depends from and includes all of the limitations of Claim 19.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Halee Cramer whose telephone number is (571)270-1641. The examiner can normally be reached Monday - Friday 7:30am - 4:30pm.
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/HALEE CRAMER/Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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