DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites “the direction” in lines 18 and 24 and recites multiple directions including a first direction, a second direction and a direction perpendicular to the plane in the previous lines of the claim 8 and therefore it is unclear which direction is being referred to. Further clarification and appropriate correction is required.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 2, 8, 10, 11, 14, 16, 19, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Griebenow (US 20110291269 A1) in view of McKinnell (US 20040145049 A1) in view of Xu (US 20200119250 A1) in view of Yoshida (JPH03064050A, provided with Machine Translation).
Regarding claims 1, 2, 8, and 16, Griebenow discloses a method of manufacturing an integrated circuit (IC) structure, the method comprising:
forming active regions including p-type (128) and n-type regions (130) (see Fig. 1a-1k) in a substrate (121-part of 120 which can be provided as a wafer-- wafer is single crystal structure which has the same structure as an epitaxial semiconductor) and further discloses that the p-type and n-type regions may be formed by an implantation process providing the required dopant concentration in the substrate (121 ([0040]-- “In other illustrative embodiments (not shown), a portion of the substrate itself may be used as one type of semiconductor material, wherein an appropriate doping concentration may be incorporated by ion implantation, for instance on the basis of a non-masked implantation process prior to forming any openings in the substrate 121.”).
However, Griebenow does not explicitly disclose wherein the thermoelectric device comprises first portions of the bulk portion of the substrate doped with n-type dopants alternating with second portions of the bulk portion of the substrate doped with p-type dopants.
McKinnell discloses a technique similar to that described by Griebenow wherein the thermoelectric device comprises first portions of the bulk portion (120) of the substrate doped by implanting n-type silicon dopants alternating with second portions of the bulk portion of the substrate doped with p-type silicon dopants ([0024]).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the method of forming the n-type and p-type silicon thermoelectric elements of Griebenow by using the method as disclosed by McKinnell which includes implanting n-type and p-type dopants because it is a method used to form n-type and p-type thermoelectric elements and because Griebenow discloses it is appropriate to do so.
Griebenow further discloses forming a first via (any one of filled vias 135C, see Fig. 1j and 1k) over the p-type region (128) and a second via (any other filled vias 135C, see Fig. 1j and 1k) over the n-type region (130);
forming a wire (See horizontal wiring portion of 135, Fig. 1j) on each of the first via (any one of filled vias 135C, see Fig. 1j and 1k) and the second via (any other filled vias 135C, see Fig. 1j and 1k);
Griebenow does not disclose that after forming the active regions, the forming the first and second vias, and the forming the wire; forming a third via extending in the direction and thermally coupled to the p-type region (128) and a fourth via extending in the direction and thermally coupled to the n-type region (130).
Xu discloses after forming the active regions (see Fig. 6C and 6D), the forming the first and second vias (multiple vias shown which comprise bottom most 340a), and the forming the wire (horizontal portion of bottom most 340a ); forming a third via extending (see Fig. 6E) in the direction and thermally coupled to the p-type region ([0038] 308) and a fourth via (see Fig. 6E) extending in the direction and thermally coupled to the n-type region ([0038] 310) [0120] and that an external device can be coupled to this structure (See Fig. 6G 320)
It would have been obvious to one of ordinary skill in the art at the time of the invention to replace the interconnecting structure and power rails/structures of Griebenow by depositing a layer and forming third and fourth conductive vias in the layer with horizontal portions electrically coupled to p an n-type thermoelectric regions as disclosed by Xu because Xu discloses it is an appropriate structure to contact an external device.
Modified Griebenow discloses that an energy device (110) is coupled to a first and second power structure/rails (horizontal portions of interconnects) on the back side of the substrate (see Fig. 1p).
Griebenow discloses a plurality of heat sources (123D, circuit elements [0046]) positioned on a front side of a substrate (see Fig. 1n analogous structure is present in Fig. 1k, substrate is where structure 140 is placed).
Griebenow does not disclose that the heat source and the p-type region and n-type region are aligned in the same plane wherein the plane is defined by the front side of the substrate and wherein the heat source is between the p-type and n-type region in the same plane.
Griebenow discloses that the heat sources can be repositioned into substrate (121) (the device level 123 may represent a crystalline portion of the substrate 121 [0030], and also can be resized [0046]).
Yoshida discloses that a heat source (5 and 6) and a p-type region (4) and an n-type region (3) are aligned in the same plane wherein the plane is defined by the front side of the substrate(2) and wherein the heat source is between and adjacent to the p-type and n-type region in the same plane and thermally connected to the doped regions and also electrically isolated ([0011]).
Yoshida further discloses that having circuit heat sources arranged in this manner relative to the Peltier elements helps with reducing the size of the package of the semiconductor device and miniaturizing the electronic circuit.
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the position of any of the heat sources of Griebenow so that the heat sources and the p-type region and n-type region are aligned in the same plane wherein the plane is defined by the front side of the substrate and wherein any of the heat sources are between the p-type and n-type regions as disclosed by Yoshida because Griebenow discloses heat sources can be rearranged and Yoshida discloses that the heat sources can be in the same substrate where the thermoelectric regions are formed and this helps with reducing the size of the package of the semiconductor device and miniaturizing the electronic circuit.
Modified Griebenow discloses wherein the forming the active regions, the forming the first and second vias, and the forming the wire result in an array of thermoelectric structures including:
the p-type region and then-type region aligned with the heat source across a plane corresponding to the front side of the substrate; and
the wire overlying the heat source on the front side of the substrate and configured to electrically couple the p-type region to the n-type region; region through the first and second vias extending in a direction perpendicular to the plane.
Regarding claims 11 and 19, modified Griebenow discloses all of the claim limitations as set forth above.
In addition, Griebenow discloses the energy device comprises an energy source configured to apply a voltage to the first and second back-side power rails ([0056]).
Regarding claims 14 and 21, modified Griebenow discloses all of the claim limitations as set forth above.
In addition, Griebenow discloses a heat sink can be added to the stacked configuration to remove additional heat ([0026]).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the substrate (151) of Griebenow by adding an external heat sink as disclosed by Griebenow because Griebenow discloses it is appropriate to do so and it will remove additional heat.
Regarding claim 10, modified Griebenow discloses all of the claim limitations as set forth above.
However, Griebenow does not disclose forming respective first and second back-side vias on the first and second back-side power rails and respective first and second pads on the first and second back-side vias, and the electrically coupling the energy device to the first and second back-side power rails.
Xu discloses forming respective first and second back-side vias (see Fig. 6G vias are portions in which 316 are formed) formed in a solder resist layer on the first and second back-side power rails and respective first and second pads (316) on the first and second back-side vias, and the electrically coupling an electrical device to the first and second back-side power rails through the pads ([0121][0084]).
It would be obvious to one of ordinary skill in the art at the time of the filing to modify the power structures/rail of Griebenow by having a solder resist layer with vias and conductive pads to couple an electrical device as disclosed by Xu because it is a known interconnect structure to connect an electrical device to a power structure.
Furthermore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify the energy device of Griebenow by coupling it directly to the conductive pads as disclosed by Xu because it will reduce the amount of wiring necessary and also result in a more compact structure.
Claim(s) 17 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Griebenow (US 20110291269 A1) in view of McKinnell (US 20040145049 A1) in view of Xu (US 20200119250 A1) in view of Yoshida (JPH03064050A, provided with Machine Translation) as applied to claims 1, 2, 8, 10, 11, 14, 16, 19, and 21 above and in further view of Kim (US 2013/0139524 A).
Regarding claim 17, modified Griebenow discloses all of the claim limitations as set forth above.
However, Griebenow does not disclose any particular arrangement for the thermoelectric structures and in particular does not disclose array of thermoelectric structures arranged as a plurality of rows of thermoelectric structures, and the electrically coupling the energy device comprises electrically coupling the energy device to each row of the plurality of rows of thermoelectric structures arranged in parallel.
In addition, Kim discloses that the array of thermoelectric structures contain multiple rows of thermoelectric structures (See Fig. 4A and 4C and Fig. 2B (claim 17 power structures will be portions with attached leads that go through substrate)).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the particular arrangement for the thermoelectric structures of modified Griebenow so that the array of thermoelectric structures contain multiple rows of thermoelectric structures as disclosed by Kim because doing so will allow for efficient cooling of a semiconductor device.
Regarding claims 18, modified Griebenow discloses all of the claim limitations as set forth above.
However, Griebenow does not disclose any particular arrangement for the thermoelectric structures and in particular does not disclose thermoelectric structures arranged as a series of thermoelectric structures, and the electrically coupling the energy device comprises electrically coupling the energy device to the first thermoelectric structure being the first thermoelectric structure of the series of thermoelectric structures and the second thermoelectric structure being a last thermoelectric structure of the series of thermoelectric structures.
Kim also discloses the first thermoelectric structure (see Fig. 2A, power structures will be portions with attached leads that go through substrate) being the first structure of the series and the second structure being a last structure of the series of thermoelectric structures and the interconnecting wire to the powering circuit being on the first and last structure.
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the particular arrangement for the thermoelectric structures of modified Griebenow so that the array of thermoelectric structures are arranged as disclosed by Kim including interconnecting wiring to the powering circuit on the first and last structure because doing so will allow for efficient cooling of a semiconductor device.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Griebenow (US 20110291269 A1) in view of McKinnell (US 20040145049 A1) in view of Xu (US 20200119250 A1) in view of Yoshida (JPH03064050A, provided with Machine Translation) as applied to claims 1, 2, 8, 10, 11, 14, 16, 19, and 21 above and in further view of Fisher (US 6674128 B1).
Regarding claim 9, Griebenow discloses all of the claim limitations as set forth above.
However, Griebenow does not disclose a thinning operation of the substrate prior to forming the first and second power rails.
Fisher discloses that a substrate (16, See Fig. 15) for a thermoelectric device (70) can be thinned before the thermoelectric is constructed on there to improve the heat transfer so that the ability to remove heat is enhanced (C3/L24-57).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the semiconductor substrate of Griebenow by thinning the substrate in the portions where the thermoelectric elements are provided as disclosed by Fisher because it will improve heat removal properties.
Claim(s) 12 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Griebenow (US 20110291269 A1) in view of McKinnell (US 20040145049 A1) in view of Xu (US 20200119250 A1) in view of Yoshida (JPH03064050A, provided with Machine Translation) as applied to claims 1, 2, 8, 10, 11, 14, 16, 19, and 21 above and in further view of Smythe (US 2012/0174956 A1).
Regarding claims 12 and 20, modified Griebenow discloses all of the claim limitations as set forth above.
However, Griebenow does not disclose that the thermoelectric module is connected to an energy device which comprises an energy storage device
Smythe discloses that thermoelectric module can function to cool or generate energy and if it generates energy the thermoelectric module can be connected to an energy storage device ([0006][0045]).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the circuit of Griebenow by replacing the energy device with an energy storage device so that a voltage can be received and stored by the energy device as disclosed by Smythe because it is an alternative method of using a thermoelectric module and results in a method to generate energy.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Griebenow (US 20110291269 A1) in view of McKinnell (US 20040145049 A1) in view of Xu (US 20200119250 A1) in view of Yoshida (JPH03064050A, provided with Machine Translation) in view of Smythe (US 2012/0174956 A1) as applied to claims 1, 2, 8, 10, 11, 14, 16, 19, and 21 above and in further view of Stark (US 2006/0151021 A1).
Regarding claim 13, modified Griebenow discloses all of the claim limitations as set forth above.
In addition, Griebenow discloses a battery (see modification above with Smythe), however does not disclose that the energy storage device is a capacitive device.
Stark discloses a battery or a capacitive device can be used store energy generated from a thermoelectric device ([0099]).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the energy storage device of modified Griebenow by replacing the battery with a capacitive device as disclosed by Stark because both a battery and a capacitive device are able to store energy from a thermoelectric module.
With regards to where the energy device is placed relative to the substrate namely the energy storage device being on the front or back of the substrate, it would have been obvious to one of ordinary skill in the art at the time of filing to modify the placement of the energy storage device relative to the substrate to have the claimed placement because the mere rearrangement of parts, without any new or unexpected results, is within the ambit of a person of ordinary skill in the art. See In re Japikse, 86 USPQ 70 (CCPA 1950) (see MPEP § 2144.04).
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEVINA PILLAY whose telephone number is (571)270-1180. The examiner can normally be reached Monday-Friday 9:30-6:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeffrey T Barton can be reached at 517-272-1307. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
DEVINA PILLAY
Primary Examiner
Art Unit 1726
/DEVINA PILLAY/ Primary Examiner, Art Unit 1726
Prosecution Insights