DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1, including claims 1-2, 4-14, 18-19, 22-23 and 25-26, in the reply filed on 10/15/2025 is acknowledged.
Claim 3 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species of the device, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10/15/2025.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/05/2022, 08/01/2025 and 12/04/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-5, 7-12, 14, 18 and 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20170162542 A1, hereafter, “Chen”.
Regarding claim 1, Chen anticipates a semiconductor package (Fig. 4A) comprising:
a package substrate 52 [0018];
an interposer 18 [0017] (see Fig. 1A for labeling) mounted on the package substrate 52 (Fig. 4A);
a first semiconductor chip 10 [0020] mounted on the interposer 18;
a plurality of second semiconductor chips 12 [0020] mounted on the interposer 18 to surround at least a portion of the first semiconductor chip 10 (see Fig. 4G);
a heat radiation member 72 [0031] (where Fig. 4A may comprise 72 [0033]) arranged on the first semiconductor chip 10 and the plurality of second semiconductor chips 12 (Fig. 4A); and
a heat blocking member 66c [0033] extending from a portion of the heat radiation member 72 and arranged in at least one space (see 66c in Fig. 4A [0033]) among a first space (corresponding to space in which 66c is formed; Fig. 4A) between the first semiconductor chip 10 and at least one of the plurality of second semiconductor chips 12 (see Fig. 4A; where “between” does not necessarily mean “directly between”) and a second space (see Fig. 4G; where 66b is the same thermal barrier with different chosen materials [0035]) between at least two of the plurality of second semiconductor chips 12 (where top two chips on are both 12).
Regarding claim 2, Chen anticipates the semiconductor package of claim 1, wherein a material of the heat blocking member 66c has a thermal conductivity that is lower than a thermal conductivity of a material of the heat radiation member 72 (see [0033] and [0027], where 66c is a low Tk material (air) and 72 is a high Tk material).
Regarding claim 4, Chen anticipates the semiconductor package of claim 1, wherein the heat blocking member 66c comprises a heat blocking wall (one of the walls of 66c making up the pattern; Fig. 4G) 66c extending from a portion of the heat radiation member 72 in a vertical direction (see Figs. 3 & 4A) and arranged in the first space between the first semiconductor chip 10 and the at least one of the plurality of second semiconductor chips 12 (see Fig. 4G).
Regarding claim 5, Chen anticipates the semiconductor package of claim 1, wherein the heat blocking member 66c comprises a heat blocking wall 66c extending from a portion of the heat radiation member 72 in a vertical direction and arranged in the second space (see Fig. 4G) between the at least two of the plurality of second semiconductor chips 12 (Fig. 4G).
Regarding claim 7, Chen anticipates the semiconductor package of claim 1, wherein the heat blocking member comprises:
a first heat blocking wall 66c (Figs. 4A & 4G) extending from a first portion of the heat radiation member 72 (see Fig. 3) in a vertical direction and arranged in the first space between the first semiconductor chip 10 and the at least one of the plurality of second semiconductor chips 12 (Figs. 4A and 4G; where the center chip is 10); and
a second heat blocking wall 66c (Figs. 4A & 4G) extending from a second portion of the heat radiation member 72 in a vertical direction and arranged in the second space between the at least two of the plurality of second semiconductor chips 12 (Fig. 4G).
Regarding claim 8, Chen anticipates the semiconductor package of claim 1, wherein the heat blocking member comprises:
a first heat blocking wall 66c (Figs. 4A & 4G) extending from a first portion of the heat radiation member 72 (see Fig. 3) in a vertical direction and arranged in the first space between the first semiconductor chip 10 and the at least one of the plurality of second semiconductor chips 12 (Figs. 4A and 4G; where the center chip is 10); and
a second heat blocking wall 66c (Figs. 4A & 4G) extending from a second portion of the heat radiation member 72 in a vertical direction and arranged in the second space between the at least two of the plurality of second semiconductor chips 12 (Fig. 4G); and
a third heat blocking wall 16 (molding compound, surrounding the sides of each first and second semiconductor chip; [0015]; see Fig. 1A for labeling) arranged outside the plurality of second semiconductor chips 12, surrounding the first semiconductor chip 10 and the plurality of second semiconductor chips 12 (Fig. 4A), and
connecting the first heat blocking wall 66c to the second heat blocking wall 66c (Figs. 4A; thermally connected).
Regarding claim 9, Chen anticipates the semiconductor package of claim 1, wherein, when the semiconductor package is seen in a planar view, the heat blocking member 66c has a quadrangular shape (Fig. 4G) that surrounds a side portion of the first semiconductor chip 10 (see rectangle around center first semiconductor chip 10; Fig. 4G).
Regarding claim 10, Chen anticipates the semiconductor package of claim 1, wherein the heat blocking member comprises:
a plurality of first protrusions 66c protruding in a direction toward the first semiconductor chip 10 (where the protrusion direction is relative to the top surface of 66); and
a plurality of second protrusions 66c protruding in a direction toward at least one of the plurality of second semiconductor chips 12 (where the protrusion direction is relative to the top surface of 66).
Regarding claim 11, Chen anticipates the semiconductor package of claim 1, wherein a lower surface of the heat blocking member 66c is spaced apart from an upper surface of the interposer 18 (see Fig. 1A for labeling) in a vertical direction (see Fig. 4A).
Regarding claim 12, Chen anticipates the semiconductor package of claim 1, a lower surface of the heat blocking member 66c is in contact with an upper surface of the interposer 18 (through molding compound 16 [0015], see Fig. 1A; not necessarily in “direct” contact).
Regarding claim 14, Chen anticipates a semiconductor package (Fig. 4A) comprising:
a package substrate 52 [0018];
an interposer 18 [0017] (see Fig. 1A for labeling) mounted on the package substrate 52 (Fig. 4A);
a first semiconductor chip 10 [0020] mounted on the interposer 18;
a plurality of semiconductor stack structures 12 [0020] mounted on the interposer 18 to surround at least a portion of the first semiconductor chip 10 (Figs. 4A & 4G), and comprising a plurality of semiconductor chips stacked in a vertical direction (see Fig. 4A; [0016]);
a heat radiation member 72/66a [0031] (where 66a and 72 are thermally conductive and move heat away from the chips [0031]) where Fig. 4A may comprise 72 [0033]) arranged on the first semiconductor chip 10 and the plurality of semiconductor stack structures 12 (see Fig. 4A), the heat radiation member 72/66a comprising:
a first heat radiation wall 66a extending on the first semiconductor chip 10 and the plurality of semiconductor stack structures 12 in a horizontal direction (see Fig. 4A); and
at least one second heat radiation wall 62 [0025] extending from a portion of the first heat radiation wall 66a in the vertical direction and surrounding the first semiconductor chip 10 and the plurality of semiconductor stack structures 12 (Fig. 4A); and
a heat blocking member 66b/66c (thermal barrier portions [0035]) extending from a portion of the heat radiation member 72 and arranged in at least one space (see 66c in Fig. 4A [0033]) among a first space (corresponding to space in which 66c is formed; Fig. 4A) between the first semiconductor chip 10 and at least one of the plurality of second semiconductor chips 12 (see Fig. 4A; where “between” does not necessarily mean “directly between”) and a second space (see Fig. 4G) between at least two of the plurality of second semiconductor chips 12 (where top two chips on are both 12).
Regarding claim 18, Chen anticipates the semiconductor package of claim 14, wherein the at least one second heat radiation wall 62 is a plurality of second heat radiation walls (at four sides of the package; see Fig. 4G) that extend from respective portions of the first heat radiation wall 66a in the vertical direction, and
the heat blocking member 66b/66c comprises:
a first heat blocking wall 66c extending between at least of the plurality of second heat radiation walls 62 (see Figs. 4A and 4G), that face each other, and arranged in the first space between the first semiconductor chip 10 and the at least two of the plurality of semiconductor stack structures 12 (see Fig. 4G where 66c is disposed in holes between 10 and 12 and in between 62 disposed at periphery; see periphery in Fig. 4A); and
a second heat blocking wall 66b extending from a portion of one of the plurality of second heat radiation walls 62 and arranged in the second space between the at least two of the plurality of semiconductor stack structures 12 (see Fig. 4G, where 66b extends from the periphery towards the center of the package, away from the second heat radiation walls 62).
Regarding claim 22, Chen anticipates the semiconductor package of claim 14, wherein a material of the heat blocking member 66c has a thermal conductivity that is lower than a thermal conductivity of a material of the heat radiation member 72 (see [0033] and [0027], where 66c is a low Tk material (air) and 72 is a high Tk material).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 6 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Chen.
Regarding claim 6, Chen anticipates the semiconductor package of claim 5. Chen does not explicitly teach wherein a surface toward the first semiconductor chip 10 among surfaces of the heat blocking wall 66b is coplanar with a surface toward the first semiconductor chip 10 among surfaces of the plurality of second semiconductor chips 12.
However, Chen further teaches wherein TIM layer 58 [0020] may further include air gaps between dies to further act as a heat blocking wall [0020] (see airgap between 58a and 58c in Fig. 4A communicating with heat blocking walls 66c. Wherein the heat blocking walls in layer 58 are disposed so as to be coplanar with the first semiconductor chip 10.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further include the air gap in layer 58 to extend the heat blocking wall 66c to further prevent thermal interaction between dies, as taught by Chen [0020].
Regarding claim 19, Chen anticipates the semiconductor package of claim 18, but does not explicitly teach wherein a thickness of the first heat blocking wall 66c is greater than a thickness of the second heat blocking wall 66b.
However, Chen further teaches wherein TIM layer 58 [0020] may further include air gaps between dies to further act as a heat blocking wall [0020] (see airgap between 58a and 58c in Fig. 4A communicating with heat blocking walls 66c.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further include the air gap in TIM layer 58 to extend the heat blocking wall 66c to further prevent thermal interaction between dies, as taught by Chen [0020], such that a thickness of the first heat blocking wall 66c (comprising the airgap in 58) is greater than a thickness of the second heat blocking wall 66b.
Claims 13, 25 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of US 20220122896 A1, hereafter “Wang”.
Regarding claim 13, Chen anticipates the semiconductor package of claim 1, but does not teach wherein a thickness of the heat blocking member 66c is 50 micrometers to 500 micrometers.
Wang teaches a semiconductor package (Fig. 1D) comprising a thermal layer 306 [0054] in contact with a heat dissipation structure 400 [0056] wherein the thickness of the thermal layer is 10 to 500 micrometers [0054].
Given Chen teaches the heat blocking member 66c is disposed in a thermal layer 66 [0033], similar to thermal layer 306 and does not explicitly disclose the thickness of said layer, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the thickness of the heat blocking member 66c of Chen to be between 50 to 500 micrometers, as taught by Wang, given Chen is silent as to the thickness and Wang teaches such a thickness is sufficient for providing thermal contact with the heat dissipation structure (see MPEP 2144.07).
Regarding claim 25, Chen anticipates the semiconductor package of claim 14, wherein the interposer 18 comprises:
an interposer substrate (wafer portion; see where labeling of 18 [0016]; Fig. 1A) mounted on the package substrate 52;
an interposer through electrode (not labeled; see TSVs corresponding to connectors 14 [0016] passing through at least a portion of the interposer substrate 18 in the vertical direction;
an interposer connection terminal 20 [0017] connected to the interposer through electrode (TSVs) and arranged between the interposer substrate (wafer) and the package substrate 52 (Fig. 1A).
Chen does not teach a redistribution structure arranged on the interposer substrate and comprising: a redistribution insulating layer; and a redistribution pattern extending within the redistribution insulating layer and connected to the interposer through electrode (TSVs).
Wang teaches a semiconductor package (Fig. 1D) comprising an interposer 120 [0031], and further comprising a redistribution structure (RDLs; see [0031]) arranged on a interposer substrate 121 [0030] and comprising: a redistribution insulating layer (polymer layers [0031]); and a redistribution pattern (see interconnect structures 124 [0029]; conductive vias/traces [0031]) extending within the redistribution insulating layer [0031] and connected to a interposer through electrode 128 [0030].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the RDL structure of Wang in the device of Chen in order to provide electrical connection between dies and the package substrate and improving device routing between the dies and substrate, as taught by Wang [0031].
Regarding claim 26, Chen teaches a semiconductor package (Fig. 4A) comprising:
a package substrate 52 [0018];
an interposer 18 [0017] (see Fig. 1A for labeling) mounted on the package substrate 52 (Fig. 4A) and comprising;
an interposer substrate (wafer portion; see where labeling of 18 [0016]; Fig. 1A);
an interposer through electrode (not labeled; see TSVs corresponding to connectors 14 [0016] passing through at least a portion of the interposer substrate 18 in the vertical direction;
an interposer connection terminal 20 [0017] connected to the interposer through electrode (TSVs) and arranged between the interposer substrate (wafer) and the package substrate 52 (Fig. 1A);
a logic semiconductor chip 12a [0015] (Fig. 1A) arranged on the interposer 18;
a plurality of semiconductor stack structures 10 and 12b (“stacked dies” [0015]) arranged on the interposer 18 to surround at least a portion of the logic semiconductor chip 12a (surrounding the top and side surfaces; Fig. 1A and Fig. 4G), and comprising a plurality of memory semiconductor chips (see 12b [0015]) stacked in the vertical direction (Fig. 1A);
a heat radiation member 72/66a [0031] (where 66a and 72 are thermally conductive and move heat away from the chips [0031]) where Fig. 4A may comprise 72 [0033]) arranged on the logic semiconductor chip 12a and the plurality of semiconductor stack structures 10/12b (see Fig. 4A); and
a heat blocking member 66b/66c (thermal barrier portions [0035]) extending from at least a portion of the heat radiation member 72 and arranged in at least one space (see 66c in Fig. 4A [0033]) among a first space (corresponding to space in which 66c is formed; Fig. 4A) between the logic semiconductor chip 12a and at least one of the plurality of semiconductor stack structures 10/12b (see 10 in Fig. 4A; where “between” does not necessarily mean “directly between”) and a second space (see Fig. 4G) between at least two of the plurality of semiconductor stack structures 10/12b.
Chen does not teach a redistribution structure arranged on the interposer substrate, so as to be between the interposer substrate (wafer of 18) and the logic chip 12a and the plurality of semiconductor stack structures 10/12b.
Wang teaches a semiconductor package (Fig. 1D) comprising an interposer 120 [0031], and further comprising a redistribution structure (RDLs; see [0031]) arranged on a interposer substrate 121 [0030] so as to be between the interposer substrate 121 and a plurality of dies 110 [0018].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the RDL structure of Wang in the device of Chen in order to provide electrical connection between dies and the package substrate and improving device routing between the dies and substrate, as taught by Wang [0031].
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim 22 above, and further in view of 20220320008 A1, hereafter “Kusuyama”.
Regarding claim 23, Chen anticipates the semiconductor package of claim 22, wherein the material of the heat radiation member 72/66a comprises copper ([0022] where the materials of 72 are materials of 66a [0027]).
Chen does not teach that the material of the heat blocking member 66b/66c comprises stainless steel.
Kusuyama teaches a semiconductor package (Fig. 7) comprising a copper shield layer 8 [0104] (materially equivalent to the copper heat dissipation layer of Chen) above a plurality of chips (31, 32, 34 and 35 [0046,0047]), and further, an internal shield layer 9 [0103] comprising stainless steel [0103] and extending from said copper shield layer 8.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the internal shield stainless steel layer 9 of Kusuyama in the device of Chen (so as to be between semiconductor chips 10 and 12) in order to prevent interference between adjacent chips, as taught by Kusuyama [0008].
Kusuyama does not explicitly teach that the copper shield layer 8 is a heat dissipation layer and the internal shield layer 9 is a heat blocking layer, however, given the material of the internal shield layer 9 has a low thermal conductivity coefficient (e.g., when compared to copper) and where the instant disclosure teaches “stainless steel” suitably blocks heat transfer between adjacent chips (see [0098,0099] of instant disclosure; MPEP 2111.01), it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the teachings of Kusuyama for the reasons stated above, such that the stainless steel internal shield layer 9 in tandem with the heat blocking patterns 66b and 66c of Chen serve as a heat blocking member within the package.
Conclusion
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/BRUCE R. SMITH/Examiner, Art Unit 2892
/ERIC W JONES/Primary Examiner, Art Unit 2892