DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
The Amendment filed on 11/21/2025, responding to the Office action mailed on 8/22/2025, has been entered into the record. The present Office action is made with all the suggested amendments being fully considered. Accordingly, claims 1-19 are pending in this application. Claims 14-19 are withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-7, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Song et al. (US 20200395409 A1) in view of Park (US 20150310912 A1).
Re Claim 1 Song teaches a semiconductor memory device (FIG. 1), comprising:
a plurality of insulating layers (110) [0041] spaced apart from each other in a stacking direction (FIG. 6);
a slit insulating layer (130) passing through the plurality of insulating layers (110);
a plurality of first variable resistance layers (RP2) alternately disposed with the plurality of insulating layers (110) in the stacking direction ([0053], FIG. 6 & 7);
a plurality of conductive lines (WL1 and WL2) [0064] interposed between the slit insulating layer (130) and the plurality of first variable resistance layers and alternately disposed with the plurality of insulating layers (110) in the stacking direction (FIG. 6);
a conductive pillar (BL) [0065] passing through the plurality of insulating layers (110) and the plurality of first variable resistance layers (RP2);
a second variable resistance layer (RP1) surrounding a sidewall of the conductive pillar (BL, FIG. 6 and 7),
wherein the plurality of first variable resistance layers and the second variable resistance layer include a material (Se) of which threshold voltage varies depending on polarity of a program pulse [0056], and the second variable resistance layer (RP1) directly contacts the plurality of insulating layers (110, FIG. 6 & 7).
Song does not teach each of the plurality of first variable resistance layers surrounds a respective portion of the second variable resistance layer, and the second variable resistance layer directly contacts the plurality of first variable resistance layers.
Park teaches each of the plurality of first variable resistance layers (R1) [0027] surrounds a respective portion of the second variable resistance layer (R2) [0034], and the second variable resistance layer directly contacts the plurality of first variable resistance layers (FIG. 1A & 1C).
The ordinary artisan would have been motivated to modify Park in combination with Song in the above manner for the motivation of optimally integrating the variable resistance layers to the device to conserve space as device size continues to trend towards miniaturization. [0003] states, “Recently, as electronic devices or appliances trend toward miniaturization, low power consumption, high performance, multi-functionality, and so on, there is a demand for electronic devices capable of storing information in various electronic devices or appliances such as a computer, a portable communication device, and so on, and research and development for such electronic devices have been conducted.”
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Park into the structure of Song since Park teaches a semiconductor memory device with variable resistance layers.
Re Claim 4 Song in view of Park teaches the semiconductor memory device of claim 1, wherein the second variable resistance layer (Song, RP1) includes one or more elements (Se and Ge) that constitute each of the plurality of first variable resistance layers (RP2)[0056].
Re Claim 5 Song in view of Park teaches the semiconductor memory device of claim 1, wherein each of the plurality of first variable resistance layers (Song, RP2) and the second variable resistance layer (RP1) include germanium (Ge) and selenium (Se) [0056].
Re Claim 6 Song in view of Park teaches the semiconductor memory device of claim 5, wherein the second variable resistance layer (Song, RP1) includes a material of which content of at least one of germanium (Ge) and selenium (Se) is higher than content of at least one of germanium (Ge) and selenium (Se) of a material in each of the plurality of first variable resistance (RP2) layers ([0055] states, “…RP1 and RP2 may include phase change materials having different chemical compositions.” [0056] states, “RP1 and RP2 may include compound by combination of at least one of chalcogenide materials, such as Te or Se and at least one of Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, P, O and C. Each of the first and second variable resistance patterns RP1 and RP2 may include, for example, at least one of GeSbTe, GeTeAs, SbTeSe” One can use GeSbTe for the second variable resistance layer and SbTeSe for the first variable resistance layer. The second variable resistance layer will have more Ge than the first variable resistance layer.
Re Claim 7 Song in view of Park teaches the semiconductor memory device of claim 1, further comprising a plurality of third variable resistance (Song, RP3) [0073] layers alternately disposed with the plurality of insulating layers (110) in the stacking direction and interposed between the plurality of first variable resistance layers (RP2) and the plurality of conductive lines (WL2, FIG. 6 & 7).
Re Claim 9 Song in view of Park teaches the semiconductor memory device of claim 7, wherein the plurality of third variable resistance layers (RP3) include a material of which threshold voltage varies depending on the polarity of the program pulse ([0094] states, “…the first to fourth variable resistance patterns RP1˜RP4 may include chalcogenide materials…” Chalcogen materials threshold voltage vary depending on the polarity of the program pulse).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Song in view of Park and further in view of Fantini (US 20200203429 A1).
Re Claim 2 Song in view of Park teaches the semiconductor memory device of claim 1, but does not each of the plurality of first variable resistance layers includes a first etched surface facing the conductive pillar.
Fantini teaches each of the plurality of first variable resistance layers (206, Fig. 2, [0033] states, “Examples of the insulation material 206 include, but are not limited to dielectric materials, such as silicon oxide.”) includes a first etched surface (Fig. 5, 6, 7A) [0042] facing the conductive pillar (817) [0047].
The ordinary artisan would have been motivated to modify Fantini in combination with Song in view of Park in the above manner for the motivation of using etching through the variable resist layers to form an opening for the conductive pillar. Etching is critical for optimally integrating multiple layers within each other for building an efficient semiconductor device.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Fantini into the structure of Song in view of Park.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Song in view of Park and further in view of Azuma et al. (US 20120099367 A1).
Re Claim 3 Song in view of Park teaches the semiconductor memory device of claim 1, but does not teach the plurality of first variable resistance layers include a chalcogenide material having substantially the same composition as a chalcogenide material of the second variable resistance layer.
Azuma teaches the plurality of first variable resistance layers (13) [0053] include a chalcogenide material having substantially the same composition as a chalcogenide material of the second variable resistance layer (12). (Azuma [0121] states, “…a first variable resistance layer 13 comprising oxygen-deficient tantalum oxide (TaO.sub.x), a second variable resistance layer 12 formed by oxidation of the first variable resistance layer 13 in an oxygen plasma atmosphere and comprising TaO.sub.y (x<y) lower in oxygen deficiency than TaO.sub.x, …”).
The ordinary artisan would have been motivated to modify Azuma in combination with Song in view of Park in the above manner for the motivation of using substantially the same composition of chalcogenide materials will allow for process/price optimization requiring fewer raw materials.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Azuma into the structure of Song in view of Park.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Song in view of Park and further in view of Ko (US 20150187415 A1).
Re Claim 8 Song in view of Park the semiconductor memory device of claim 7, but does not teach of the plurality of first variable resistance layers includes a second etched surface facing a corresponding conductive line among the plurality of conductive lines.
Ko teaches of the plurality of first variable resistance layers (14a) includes a second etched surface (FIG. 3E) [0040] facing a corresponding conductive line (17) [0026] among the plurality of conductive lines (FIG. 3J).
The ordinary artisan would have been motivated to modify Ko in combination with Song in view of Park in the above manner for the motivation of etching a second face on the first variable resistance layer facing a corresponding conductive line. Etching part of the variable resistance layer will allow for optimal chip design easily allowing multiple layers of different materials to integrate to form the device.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Ko into the structure of Song in view of Park.
Claims 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Song in view of Park and further in view of Arayashiki et al. (US 20180277597 A1).
Re Claim 10 Song in view of Park teaches the semiconductor memory device of claim 7, but does not teach the plurality of first variable resistance layers include a chalcogenide material having substantially the same composition as a chalcogenide material of the plurality of third variable resistance layers.
Arayashiki teaches the plurality of first variable resistance layers (R1) [0041] include a chalcogenide material ([0052] states, “The variable resistance layer R includes, for example, a chalcogen compound. The variable resistance layer R includes, for example, a chalcogen compound including at least one of germanium (Ge)…”) having substantially the same composition as a chalcogenide material of the plurality of third variable resistance layers (R3, [0073], FIG. 3B).
The ordinary artisan would have been motivated to modify Arayashiki in combination with Song in view of Park in the above manner for the motivation of using the same material for the first and third variable resistance layers to help the device maintain optimal current levels.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Arayashiki into the structure of Song in view of Park.
Re Claim 11 Song in view of Park and Arayashiki teaches the semiconductor memory device of claim 7, wherein each of the plurality of third variable resistance layers (Arayashiki, R3) includes one or more elements that constitute each of the plurality of first variable resistance layers (R1, [0052] The variable resistance layer R includes, for example, a chalcogen compound. The variable resistance layer R includes, for example, a chalcogen compound including at least one of germanium (Ge)…” Use Ge for R1 and R3).
Re Claim 12 Song in view of Park and Arayashiki teaches the semiconductor memory device of claim 7, wherein each of the plurality of first variable resistance layers (Arayashiki, R1) and each of the plurality of third variable resistance layers (R3) include germanium (Ge) and selenium (Se) ([0052] states, The variable resistance layer R includes, for example, a chalcogen compound. The variable resistance layer R includes, for example, a chalcogen compound including at least one of germanium (Ge)…”).
Re Claim 13 Song in view of Park and Arayashiki teaches the semiconductor memory device of claim 12, but does not explicitly teach each of the plurality of third variable resistance layers includes a material of which content of at least one of germanium (Ge) and selenium (Se) is higher than content of at least one of germanium (Ge) and selenium (Se) of a material in each of the plurality of first variable resistance layers.
Song in view of Park and Arayashiki does teach the first variable resistance layer (Song, RP2) may NOT contain Ge and/or Se ([0056] states, “…RP2 may include compound by combination of at least one of chalcogenide materials, such as Te or Se and at least one of Ge, Sb, Bi, Pb, Sn, …”)
Song in view of Park and Arayashiki also teaches the third variable resistance layer (Arayashiki, R3) contains Ge ([0052] states, “The variable resistance layer R includes, for example, a chalcogen compound. The variable resistance layer R includes, for example, a chalcogen compound including at least one of germanium (Ge)…”). The third variable resistance layer therefore contains more Ge than the first variable resistance layer.
The ordinary artisan would have been motivated to modify Arayashiki in combination with Song in view of Park and Arayashiki in the above manner for the motivation have the third variable resistance layers contain more of at least one of the elements between Ge and Se. Reducing the Ge or Se materials in the first variable will allow for current optimization in the semiconductor memory device.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Arayashiki into the structure of Song in view of Park and Arayashiki.
Response to Arguments
Applicant’s arguments with respect to claims 1-13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KENNETH MARK SIPLING/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 3/16/26