DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s traversal about the prior art rejections of Claims 9 – 20 on pages 7 – 8 of the reply—filed 12 December 2025—is acknowledged; however, said arguments are moot because they do not apply to the new grounds of rejection presented in this Office Action, necessitated by Applicant’s amendment.
Applicant’s request for rejoinder of withdrawn Claims 1 – 8 in the reply—filed 12 December 2025—is acknowledged. However, no claims are presently allowable. Therefore, a rejoinder at this time is not proper.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on:
1 September 2023; and
8 October 2024
have been considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims.
Regarding Claim 9,
This claim recites the limitations “first active circuitry” and “second active circuitry”.
Regarding Claim 16,
This claim recites the limitations “first active circuitry” and “second active circuitry”.
Therefore, these elements must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
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Claims 9, 11 – 16, & 18 – 20 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by YU (US 201601970055 A1).
Regarding Claim 9,
YU discloses:
A semiconductor device (Fig. 7: 170; Par. 26), comprising:
a first semiconductor die (Fig. 7: 150; Par. 25) including:
a first semiconductor substrate (Fig. 7: 152/154; Par. 12) having a first major surface (Fig. 7: 154/158 interface), and
a first layer of dielectric material (Fig. 7: 158; Par. 15) over the first major surface,
the first layer including a plurality of recesses (Fig. 6: 160), each of the plurality of recesses being defined by a shape (Par. 22); and
a second semiconductor die (Fig. 7: 100; Par. 25) including:
a second semiconductor substrate (Fig. 7: 102/104; Par. 12) having a second major surface (Fig. 7: 104/108 interface) opposite the first major surface, and
a second layer of dielectric material (Fig. 7: 108; Par. 15) over the second major surface,
the second layer including a plurality of protrusions (Fig. 7: 114), each of the plurality of protrusions being vertically aligned with a corresponding one of the plurality of recesses and being defined by the shape of the corresponding one of the plurality of recesses (As shown in Fig. 7), wherein
at least one of the plurality of recesses includes a first conductive contact (Fig. 7: 164; Par. 22) disposed therein, and
at least the corresponding one of the plurality of protrusions includes a second conductive contact (Par. 20, 114 is a protruding conductive contact) disposed thereon,
wherein the first conductive contact is operably coupled to first active circuitry (Fig. 7: 156’; Par. 14) formed in the first semiconductor substrate, and
wherein the second conductive contact is operably coupled to second active circuitry (Fig. 7: 106’; Par. 14) formed in the second semiconductor substrate.
Regarding Claim 11,
YU discloses:The semiconductor device of claim 9,wherein
the first conductive contact comprises a first dual damascene pad (Fig. 7: horizontal portion of 164), and
the second conductive contact comprises a second dual damascene pad (Fig. 7: portion of 114 within 108).
Regarding Claim 12,YU discloses:
The semiconductor device of claim 9,
wherein each one of the plurality of recesses includes a first surface (Fig. 7: 164/114 horizontal interface) and first sidewalls (Fig. 7: 164/114 vertical interfaces), and each one of the plurality of protrusions includes a second surface (Fig. 7: 164/114 horizontal interface) and second sidewalls (Fig. 7: 164/114 vertical interfaces) having the same dimensions as the first surface and first sidewalls, respectively.
Regarding Claim 13,
YU discloses:The semiconductor device of claim 12,
wherein the first sidewalls are configured at an angle (Annotated Fig. 7: PSI) and the second sidewalls are configured at a same angle (Annotated Fig. 7: PSI) of the first sidewalls.
Regarding Claim 14,
YU discloses:The semiconductor device of claim 13,
wherein the angle is greater than 0 degrees and less than 90 degrees.
(Annotated Fig. 7: PSI is about 45 degrees)
Regarding Claim 15,
YU discloses:The semiconductor device of claim 9,
wherein the first layer of dielectric material comprises a same material as the second layer of dielectric material (Par. 15).
Regarding Claim 16,
YU discloses:A method of forming a semiconductor device (Fig. 1 – 7: 170; Par. 26), the method comprising:
forming a first semiconductor die (Fig. 7: 150; Par. 25) including:
providing a first semiconductor substrate (Fig. 7: 152/154; Par. 12) having a first major surface (Fig. 7: 154/158 interface), and
providing a first layer of dielectric material (Fig. 7: 158; Par. 15) over the first major surface, and
forming a plurality of recesses (Fig. 6: 160) in the first layer, each of the plurality of recesses being defined by a shape (Par. 22);forming a second semiconductor die (Fig. 7: 100; Par. 25) including:
providing a second semiconductor substrate (Fig. 7: 102/104; Par. 12) having a second major surface (Fig. 7: 104/108 interface), and
providing a second layer of dielectric material (Fig. 7: 108; Par. 15) over the second major surface, and
forming a plurality of protrusions (Fig. 7: 114) in the second layer, each of the plurality of protrusions being defined by the shape of a corresponding one of the plurality of recesses (As shown in Fig. 7);providing a first conductive contact (Fig. 7: 164; Par. 22) in the first layer of dielectric material and a second conductive contact (Par. 20, 114 is a protruding conductive contact) in the second layer of dielectric material; and
aligning each of the plurality of protrusions with the corresponding one of the plurality of recesses (Fig. 6 & Fig. 7),
wherein the first conductive contact is operably coupled to first active circuitry (Fig. 7: 156’; Par. 14) formed in the first semiconductor substrate, and
wherein the second conductive contact is operably coupled to second active circuitry (Fig. 7: 106’; Par. 14) formed in the second semiconductor substrate.
Regarding Claim 18,
YU discloses:The method of claim 16, further comprising:
electrically coupling the first conductive contact with the second conductive contact (As shown in Fig. 7.).
Regarding Claim 19,
YU discloses:The method of claim 16,
wherein forming the recesses comprises etching away material from the first dielectric layer (Fig. 3B; Par. 16).
Regarding Claim 20,
YU discloses:The method of claim 16,
wherein forming the protrusions comprises etching away material from the second dielectric material (Fig. 3A; Par. 16).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenneth S. Stephenson whose telephone number is (571)272-6686. The examiner can normally be reached Monday through Friday, 9 A.M. to 5 P.M. (EST)..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.S.S./
Examiner, Art Unit 2898
/JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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