Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 6-7, 10, 15, 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Paek et al. (U.S 2016/0276309 A1).
As to claim 1, Paek et al. disclose in Fig. 4C a semiconductor package and a corresponding method, comprising:
mounting a plurality of active dies (comprising “semiconductor die” 110, & “stacked dies” 120a, 120b) on an active die wafer ("substrate" 260) (Fig. 4C, para. [0039]-[0041], [0092]), each of the plurality of active dies (comprising “semiconductor die” 110, & “stacked dies” 120a, 120b) coupled directly to the active die wafer (“substrate" 260) by a plurality of electrical interconnections (“conductive pads” 111, 123) (Fig. 4C, para. [0039]-[0041]), the active dies (comprising “semiconductor die” 110, & “stacked dies” 120a, 120b) having an uppermost surface (top surface) (Fig. 4C);
applying a bonding layer (“adhesive” 139) over and in direct contact with the plurality of active dies (comprising “semiconductor die” 110, & “stacked dies” 120a, 120b), the bonding layer (“adhesive” 139) having a bottommost surface (bottom surface) above the uppermost surface (top surface) of the active dies (comprising “semiconductor die” 110, & “stacked dies” 120a, 120b) (see Fig. 4C, para. [0077]); and
mounting a passive support wafer ("carrier" 140) on the bonding layer (139) (Fig. 4C, para. [0059], [0077]), wherein the passive support wafer ("carrier" 140) includes a non-polymeric material (see Fig. 4C, para. [0059], [0077]).
As to claim 2, as applied to claim 1 above, Paek et al. disclose in Fig. 4C all claimed limitations including the method further comprising: processing a through-silicon-via (as indicated at “conductive vias” 261, Figs. 4B-4C) in the active die wafer ("substrate" 260) after mounting the passive support wafer (140) on the plurality of active dies (comprising “semiconductor die” 110, & “stacked dies” 120a, 120b) (Figs. 4A-4C, para. [0097]).
As to claim 6, Paek et al. disclose in Fig. 4C a semiconductor package and a corresponding method, comprising:
coupling an active die wafer ("substrate" 260) to a package substrate (“package substrate” 20), the package substrate (“substrate” 20, para. [0080]) having a lateral width, the active die wafer ("substrate" 260) having a lateral width less than the lateral width of the package substrate (“substrate” 20) (Fig. 4C, para. [0080]), the active die wafer ("substrate" 260) having a top surface, and the active die wafer ("substrate" 260) comprising one or more electronic circuits (“conductive pads” 111 & 123) (Fig. 4C, para. [0080]);
mounting a plurality of active dies (comprising “semiconductor die” 110, & “stacked dies” 120a, 120b) on the top surface of the active die wafer ("substrate" 260), each of the plurality of active dies (comprising “semiconductor die” 110, & “stacked dies” 120a, 120b) coupled directly to the active die wafer (“substrate" 260) by a plurality of electrical interconnections (“conductive pads” 111, 123) (Fig. 4C, para. [0039]-[0041]), the plurality of active dies (comprising “semiconductor die” 110, & “stacked dies” 120a, 120b) comprising a first active die (110) laterally adjacent to a second active die (comprising 120a, 120b) on the top surface of the active die wafer ("substrate" 260), and the plurality of active dies (comprising “semiconductor die” 110, & “stacked dies” 120a, 120b) having an uppermost surface (top surface) (Fig. 4C, para. [0039]-[0041]);
applying a bonding layer (“adhesive” 139) over and in direct contact with the plurality of active dies (comprising “semiconductor die” 110, & “stacked dies” 120a, 120b), the bonding layer (“adhesive” 139) having a bottommost surface (bottom surface) above the uppermost surface (top surface) of the plurality of active dies (comprising “semiconductor die” 110, & “stacked dies” 120a, 120b) (see Fig. 4C, para. [0077]);
and mounting a passive support wafer ("carrier" 140) on the bonding layer (139), wherein the passive support wafer ("carrier" 140) includes a non-polymeric material (see Fig. 4C, para. [0059], [0077]).
As to claim 7, as applied to claim 6 above, Paek et al. disclose in Fig. 4C all claimed limitations including the limitation: wherein the passive support wafer ("carrier" 140) is a monolith of the non-polymeric material (see Fig. 4C, para. [0059], [0077]).
As to claim 10, as applied to claim 6 above, Paek et al. disclose in Fig. 4C all claimed limitations including the limitation: wherein the passive support wafer (140) includes a bottom surface facing the top surface of the active die wafer (260), and wherein the top surface and the bottom surface have a same profile (Fig. 4C).
As to claim 15, Paek et al. disclose in Fig. 4C a method of fabricating a semiconductor package assembly, the method comprising: providing a printed circuit board (20); and mounting a semiconductor package (400C) on the printed circuit board (20) (Fig. 4C), the semiconductor package (400C) including:
a package substrate (20) having a lateral width; an active die wafer (260) coupled to the package substrate (20), the active die wafer (260) having a lateral width less than the lateral width of the package substrate (20) (Fig. 4C), the active die wafer (260) having a top surface, and the active die wafer (260) comprising one or more electronic circuits (261) (Fig. 4C, para. [0097]),
a plurality of active dies (comprising “semiconductor die” 110, & “stacked dies” 120a, 120b) mounted on the top surface of the active die wafer (260), each of the plurality of active dies (comprising “semiconductor die” 110, & “stacked dies” 120a, 120b) coupled directly to the active die wafer (“substrate" 260) by a plurality of electrical interconnections (“conductive pads” 111, 123) (Fig. 4C, para. [0039]-[0041]), the plurality of active dies (comprising “semiconductor die” 110, & “stacked dies” 120a, 120b) comprising a first active die (110) laterally adjacent to a second active die (120a, 120b) on the top surface of the active die (260), and the plurality of active dies (comprising “semiconductor die” 110, & “stacked dies” 120a, 120b) having an uppermost surface (top surface) (Fig. 4C), a bonding layer (139) over and in direct contact with the plurality of active dies (comprising “semiconductor die” 110, & “stacked dies” 120a, 120b), the bonding layer (139) having a bottommost surface (bottom surface) above the uppermost surface (top surface) of the plurality of active dies (comprising “semiconductor die” 110, & “stacked dies” 120a, 120b) (see Fig. 4C, para. [0077]), and a passive support wafer (140) mounted on the bonding layer (139), wherein the passive support wafer (140) includes a non-polymeric material (see Fig. 4C, para. [0059], [0077]).
As to claim 17, as applied to claim 15 above, Paek et al. disclose in Fig. 4C all claimed limitations including the limitation: wherein the passive support wafer (140) is a monolith of the non-polymeric material (see Fig. 4C).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 8-9, 12-13, 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Paek et al. (U.S 2016/0276309 A1).
As to claim 8, as applied to claims 6 and 7 above, Paek et al. disclose in Fig. 4C all claimed limitations except for the limitation: wherein the passive support wafer has a passive support wafer thickness of less than 1 mm. However, it would have been obvious to one of ordinary skill in the art to use the teaching of Paek et al. to make a passive support wafer with a thickness of less than 1 mm for reducing the package size, as claimed, because it has been held that where the general conditions of the claims are disclosed in the prior art, it is not inventive to discover the optimum or workable range by routine experimentation. See In re Aller, 220 F.2d 454, 105 USPQ 233, 235 (CCPA 1955); Merck & Co. Inc. v. Biocraft Laboratories Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. Denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980); MPEP 2144.05. There is no evidence indicating the thickness range of a passive support wafer is critical. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
As to claim 9, as applied to claims 6, 7 and 8 above, Paek et al. disclose in Fig. 4C all claimed limitations except for the limitation: wherein the non-polymeric material is one or more of a metal, a ceramic, a silicon, or a synthetic diamond. However, at the time of the invention was made; it would have been obvious to one of ordinary skill in the art to use one or more of a metal, a ceramic, a silicon, or a synthetic diamond for making the non-polymeric material in the teaching of Paek et al. in order to reduce production cost, because such material substitution or replacement would have been considered a mere substitution of art-recognized equivalent values, MPEP 2144.06.
As to claims 12 and 13, as applied to claim 6 above, Paek et al. disclose in Fig. 4C all claimed limitations including the limitation: wherein the bonding layer (139) includes one or more of a die attach adhesive (see para. [0077]) or a solder.
Paek et al. do not disclose the bonding layer has a bonding layer thickness of 10-20 microns. However, it would have been obvious to one of ordinary skill in the art to use the teaching of Paek et al. to make a bonding layer with a thickness of 10-20 mm for reducing the package size, as claimed, because it has been held that where the general conditions of the claims are disclosed in the prior art, it is not inventive to discover the optimum or workable range by routine experimentation. See In re Aller, 220 F.2d 454, 105 USPQ 233, 235 (CCPA 1955); Merck & Co. Inc. v. Biocraft Laboratories Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. Denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980); MPEP 2144.05. There is no evidence indicating the thickness range of a bonding layer is critical. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
As to claim 18, as applied to claims 15 and 17 above, Paek et al. disclose in Fig. 4C all claimed limitations including the limitation: wherein the passive support wafer (140) has a passive support wafer thickness (Fig. 4C).
Paek et al. do not disclose the passive support wafer has a passive support wafer thickness of less than 1 mm. However, it would have been obvious to one of ordinary skill in the art to use the teaching of Paek et al. to make the passive support wafer having a thickness of less than 1 mm for reducing the package size, as claimed, because it has been held that where the general conditions of the claims are disclosed in the prior art, it is not inventive to discover the optimum or workable range by routine experimentation. See In re Aller, 220 F.2d 454, 105 USPQ 233, 235 (CCPA 1955); Merck & Co. Inc. v. Biocraft Laboratories Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. Denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980); MPEP 2144.05. There is no evidence indicating the thickness range of the passive support wafer is critical. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
As to claim 20, as applied to claim 15 above, Paek et al. disclose in Fig. 4C all claimed limitations including the limitation: wherein the bonding layer (139) has a bonding layer thickness (Fig. 4C).
Paek et al. do not disclose the bonding layer has a bonding layer thickness of 10-20 microns. However, it would have been obvious to one of ordinary skill in the art to use the teaching of Paek et al. to make a bonding layer with a thickness of 10-20 microns for reducing the package size, as claimed, because it has been held that where the general conditions of the claims are disclosed in the prior art, it is not inventive to discover the optimum or workable range by routine experimentation. See In re Aller, 220 F.2d 454, 105 USPQ 233, 235 (CCPA 1955); Merck & Co. Inc. v. Biocraft Laboratories Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. Denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980); MPEP 2144.05. There is no evidence indicating the thickness range of a bonding layer is critical. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim(s) 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over
Paek et al. (U.S 2016/0276309 A1) in view of Liu et al. (U.S 2014/0042638 A1) (of record).
As to claims 4 and 5, as applied to claim 1 above, Paek et al. disclose in Fig. 4C all claimed limitations except for the limitation wherein the passive support wafer has a passive support wafer thickness of less than 1 mm, wherein the bonding layer has a bonding layer thickness of 10-20 mm; and thinning the passive support wafer to the passive support wafer thickness.
Liu et al. disclose in Figs. 2F-2J a semiconductor package comprising the steps of: mounting a passive support wafer (“support layer” 24) on the plurality of active dies (“chips” 22); and thinning the passive support wafer (“support layer” 24) to the passive support wafer thickness (see Figs. 2F-2J, para. [0028], [0033]).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify reference of Paek et al. by thinning the passive support wafer to the passive support wafer thickness, as taught by Liu et al., in order to reduce the package size.
Paek et al. and Liu et al. do not disclose the passive support wafer has a passive support wafer thickness of less than 1 mm, and wherein the bonding layer has a bonding layer thickness of 10-20 mm. However, it would have been obvious to one of ordinary skill in the art to use the teaching of Paek et al. and Liu et al. to make a passive support wafer with a thickness of less than 1 mm, and a bonding layer with a thickness of 10-20 mm for reducing the package size, as claimed, because it has been held that where the general conditions of the claims are disclosed in the prior art, it is not inventive to discover the optimum or workable range by routine experimentation. See In re Aller, 220 F.2d 454, 105 USPQ 233, 235 (CCPA 1955); Merck & Co. Inc. v. Biocraft Laboratories Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. Denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980); MPEP 2144.05. There is no evidence indicating the thickness range of a passive support wafer and the thickness range of a bonding layer are critical. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over
Paek et al. (U.S 2016/0276309 A1) in view of Lin et al. (U.S 2014/0353838 A1).
As to claim 14, as applied to claim 6 above, Paek et al. disclose in Fig. 4C all claimed limitations including the method further comprising: forming an encapsulating layer (130) surrounding the plurality of active dies (110, 120a, 120b) between the bonding layer (139) and the active die wafer (260) (Fig. 4C, para. [0049]), wherein the bonding layer (139) physically separates the passive support wafer (140) from the encapsulating layer (130) and the plurality of active dies (110, 120a, 120b) (see Fig. 4C), and wherein the bonding layer (139) thermally couples the passive support wafer (140) to the plurality of active dies (110, 120a, 120b) (Fig. 4C, para. [0077]).
Paek et al. are silent to disclose the encapsulating layer is an epoxy layer.
Lin et al. disclose in Fig. 9 a package comprising: forming an encapsulating layer (206) surrounding the plurality of active dies (130, 130) (Fig. 9, para. [0012], [0025]).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify reference of Paek et al. by having the encapsulating layer is an epoxy layer, as taught by Lin et al., in order to improve thermal management for the active dies.
Allowable Subject Matter
Claim 16 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-2, 4-10, 12-15, 17-18, and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST).
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/Thanh Y. Tran/Primary Examiner, Art Unit 2817