DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114 & Claims’ Status
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/7/2026 has been entered.
Claims 1-6 and 9-20 are currently pending, with Claims 1-6, 9-17, and 19-20 being examined (claim 18 was withdrawn due to restriction requirement). Claims 1 and 19 have been amended. No claims have been newly added or newly cancelled.
Specification
The new title submitted 1/7/2026 is accepted by the Office.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6, 9, 14-15, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dheeraj et al (US 2018/0204977 A1, hereafter Dheeraj).
Re Claim 1, Dheeraj discloses a method for manufacturing a semiconductor structure (FIG. 1; [0204]-[0212]) comprising a III-V semiconductor device in a first region (“Region 1”, see FIG. Z1 below) of a base substrate (8; [0210]) and at least part of a further device in a second region (“Region 2”, see FIG. Z1 below) of the base substrate (8; [0210]), the method comprising:
a) obtaining a base substrate (8; [0210]) comprising the first region (“Region 1”) and the second region (“Region 2”; [0210]), the second region (“Region 2”) being spatially separated from the first region (“Region 1”; [0210]);
b) providing a buffer layer (3, specifically monolayer closest to support 1, under the “thicker” configuration; [0206]) over a surface of the base substrate (8; [0210]) at least in the first region (“Region 1”; [0210]), wherein the buffer layer (3, specifically monolayer closest to support 1) comprises at least one monolayer of a first two-dimensional layered crystal material ([0206]);
c) forming, over the buffer layer (3, specifically monolayer closest to support 1) in the first region (“Region 1”), and not in the second region (“Region 2”), a III-V semiconductor material (4; [0207]); and
d) forming, in the second region (“Region 2”), at least part of the further device having at least one monolayer of a second two-dimensional layered crystal material (3, specifically monolayer closest to submount 8; [0206]).
PNG
media_image1.png
405
354
media_image1.png
Greyscale
FIG. Z1: Annotated version of FIG. 1 of Dheeraj
Re Claim 2, Dheeraj discloses the method according to Claim 1, while further disclosing wherein the III-V semiconductor material (4) comprises a III-N semiconductor material ([0207]).
Re Claim 3, Dheeraj discloses the method according to Claim 2, while further disclosing wherein the III-N semiconductor material is selected from the group consisting of GaN, AlN, InN, AlGaN, InGaN, InAlN, and GaInAlN ([0207]).
Re Claim 6, Dheeraj discloses the method according to Claim 1, while further disclosing wherein providing the buffer layer (3, specifically monolayer closest to support 1) comprises providing the buffer layer (3, specifically monolayer closest to support 1) over a surface of the base substrate (8) in the first region (“Region 1”) and in the second region (“Region 2”; [0210]).
Re Claim 9, Dheeraj discloses the method according to Claim 6, while further disclosing wherein the at least part of the further device (see FIG. Z1) comprises the buffer layer (3, specifically monolayer closest to support 1) in the second region (“Region 2”; [0210]).
Re Claim 14, Dheeraj discloses the method according to Claim 1, while further disclosing wherein the buffer layer (3, specifically monolayer closest to support 1) comprises from 1 to 100 monolayers of the first two-dimensional layered crystal material ([0206]).
Re Claim 15, Dheeraj discloses the method according to Claim 1, while further disclosing wherein the at least one monolayer of the first two-dimensional layered crystal material comprises graphene ([0206]), silicene, borophene, germanene, black phosphorus, hexagonal boron nitride, or a transition metal dichalcogenide monolayer.
Re Claim 19, Dheeraj discloses a method for manufacturing a semiconductor structure (FIG. 1; [0204]-[0212]) comprising a III-V semiconductor device in a first region (“Region 1”, see FIG. Z1) of a base substrate (8; [0210]) and at least part of a further device in a second region (“Region 2”, see FIG. Z1) of the base substrate (8; [0210]), the method comprising:
a) obtaining a base substrate (8; [0210]) comprising the first region (“Region 1”) and the second region (“Region 2”; [0210]), the second region (“Region 2”) being spatially separated from the first region (“Region 1”; [0210]);
b) providing a buffer layer (3, specifically monolayer closest to support 1, under the “thicker” configuration; [0206]) over a surface of the base substrate (8; [0210]) at least in the first region (“Region 1”; [0210]), wherein the buffer layer (3, specifically monolayer closest to support 1) comprises at least one monolayer of a first two-dimensional layered crystal material ([0206]);
c) forming, over the buffer layer (3, specifically monolayer closest to support 1) in the first region (“Region 1”), and not in the second region (“Region 2”), a III-V semiconductor material (4; [0207]) having a III-N semiconductor material selected from the group consisting of AlN, InN, AlGaN, InGaN, InAlN, and GaInAlN ([0207]); and
d) forming, in the second region (“Region 2”), at least part of the further device ([0210]).
Re Claim 20, Dheeraj discloses the method according to Claim 19, while further disclosing wherein the at least part of the further device (see FIG. Z1) comprises a silicon semiconductor material or at least one monolayer of a second two-dimensional layered crystal material (3, specifically monolayer closest to submount 8; [0206]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Dheeraj, as applied to Claim 1, in view of Nakanishi et al (US 2004/0071411 A1, hereafter Nakanishi).
Re Claim 4, Dheeraj discloses the method according to Claim 1, but does not explicitly disclose wherein the base substrate (8) comprises crystalline silicon.
However, Nakanishi teaches a method (FIGS. 10A-B; [0031]) wherein the base substrate (“submount”; [0031]) comprises crystalline silicon ([0031]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method as discussed for Claim 1 with the limitations taught by Nakanishi to use crystalline silicon for the submount (Dheeraj: 8) due its ability to be processed with high precision by photolithographic technology as taught by Nakanishi ([0031]).
Re Claim 5, Dheeraj and Nakanishi teach the method according to Claim 4, while Nakanishi further teaches wherein the crystalline silicon is Si(100) ([0069]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method as discussed for Claim 4 with the limitations taught by Nakanishi to use {100} crystalline silicon for the submount (Dheeraj: 8) due its ability to be processed with high precision by photolithographic technology as taught by Nakanishi ([0031]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Dheeraj, as applied to Claim 1, in view of Heilmann et al (DE 102019111225 A1, of record, hereafter Heilmann).
Re Claim 11, Dheeraj discloses the method according to Claim 1, but does not not explicitly disclose the method comprising a step b' after step b and before step c of:
b') introducing crystallographic defects in the buffer layer (3, specifically monolayer closest to support 1) in the first region (“Region 1”) and not in the second region (“Region 2”).
However, Heilmann, teaches a method for manufacturing a semiconductor structure (FIG. 1, pg. 5), comprising a step b' of:
b') introducing crystallographic defects (12; pg. 5, paragraph 4) in the buffer layer (11; pg. 5, paragraph 3) in the first region (section of device covered by mask 41; pg. 5, paragraph 12) and not in the second region (section of device not covered by mask 41; pg. 5, paragraph 12).
Heilmann does not explicitly disclose whether the described step b’ occurs after step b and before step c, specifically when in combination with Dheeraj. However, the difference between multiple sequential steps of formation and incorporation of defects and a simultaneous deposition and incorporation of defects reflects a trivial alteration in a change of sequence that introduces no distinguishable or unexpected difference to the finished product – as the buffer layer would still have the described limitations of introduced defects corresponding to the claimed sequence (see MPEP 2144.04, IV, C).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method discussed for Claim 1 with the limitations taught by Heilmann to introduce crystallographic defects in the buffer layer (Dheeraj: 3, specifically monolayer closest to support 1) prior to the addition of further layers to alter the electrical or optical properties of the buffer layer (Dheeraj: 3, specifically monolayer closest to support 1) as taught by Heilmann (pg. 5, paragraph 6).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Dheeraj, as applied to Claim 1.
Re Claim 13, Dheeraj discloses the method according to Claim 1, while further disclosing a step c’’ of forming a protective layer (5; [0208]) over the III-V semiconductor material (4; [0208], “over” the side of).
Heilmann does not explicitly disclose whether the described step c’’ occurs after step c and before step d. However, the difference between multiple sequential steps of layer formation and a simultaneous layer formation reflects a trivial alteration in a change of sequence that introduces no distinguishable or unexpected difference to the finished product – as the protective layer would still have the described positional limitations relative to the III-V semiconductor material corresponding to the claimed sequence (see MPEP 2144.04, IV, C).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Dheeraj, as applied to Claim 1, in view of Kim et al (US 2018/0226242 A1, of record, hereafter Kim).
Re Claim 16, Dheeraj discloses the method according to Claim 1, does not explicitly disclose the method comprising wherein step c of forming the III-V semiconductor material (4) comprises the steps of:
c1) depositing buffer III-V material at a temperature ranging from 1000 to 1200 C; and
c2) depositing an active III-V material on the buffer III-V material at a temperature ranging from 1210 to 1300°C.
However, Kim teaches a method for manufacturing a semiconductor structure (FIG. 1A; [0135]) comprising wherein step c of forming the III-V semiconductor material (“thin buffer layer” and “nanowire”; [0135]) comprises the steps of:
c1) depositing buffer III-V material (“thin buffer layer”; [0135]) at a temperature ranging from 1000 to 1200 C ([0135]); and
c2) depositing an active III-V material (“nanowire”; [0135]) on the buffer III-V material (“buffer layer”; [0135]) at a temperature ranging from 1210 to 1300°C ([0135]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method discussed for Claim 1 with the limitations taught by Kim to deposit a buffer III-V material (Kim: “thin buffer layer”) prior to deposition of an active III-V material (Kim: “nanowire”) to influence the density, polarity, and alignment of nanowires as taught by Kim ([0135]).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Dheeraj and Kim, as applied to Claim 16, further in view of Fimland et al (US 2020/0161504 A1, of record, hereafter Fimland).
Re Claim 17, Dheeraj and Kim teach the method according to Claim 16, but they do not explicitly disclose the method comprising wherein, in step cl, less than 1000 nm of buffer III-V material (Kim: “thin buffer layer”) is deposited.
However, Fimland teaches a method for manufacturing a semiconductor structure (FIG. 8c; [0161]) comprising wherein, in step cl, less than 1000 nm of buffer III-V material (“buffer layer”; [0161]) is deposited ([0161]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method discussed for Claim 16 with the limitations taught by Fimland to specify the buffer III-V material’s (Kim: “thin buffer layer”) thickness as stated to provide an appropriate surface for the above nanostructure to grow as taught by Fimland ([0086]-[0088]).
Allowable Subject Matter
Claims 10 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Re Claim 10, the prior art cannot anticipate or render obvious the limitations of: a step a' after step a, and before step c of: a') forming a dielectric mask layer over the surface of the base substrate in the second region and not in the first region, in combination with the additionally claimed features of Claim 10.
Re Claim 12, the prior art cannot anticipate or render obvious the limitations of: a step c' after step c of: c') reducing an interface area between the surface of the base substrate in the first region and a surface of the buffer layer in the first region, in combination with the additionally claimed features of Claim 12.
Response to Arguments
Applicant’s arguments, see Remarks, filed 1/7/2026, with respect to the rejections of Claims 1 and 19 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Dheeraj under 35 U.S.C. 102(a)(1). Applicant’s arguments with respect to Claims 1 and 19 have been reconsidered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLIN RUSSELL MCCUTCHEON whose telephone number is (703)756-1897. The examiner can normally be reached Monday-Friday, 12:30-9:30 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DREW N RICHARDS can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/COLIN RUSSELL MCCUTCHEON/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892