DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This Office Action is in response to Amendments/Remarks filed on September 15, 2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-4, 6, 8, 18, and 20-23 are rejected under 35 U.S.C. 103 as being unpatentable over CN 108511516 A to Shan et al. (“Shan”) in view of U.S. Patent Application Publication No. 2001/0048122 A1 to Tada et al. (“Tada”). As to claim 1, Shan in view of Tada discloses a power semiconductor device, comprising: an active region (at 102) configured to conduct a load current between a first load terminal (202) and a second load terminal (201); and an edge termination region (at 103, 104) surrounding the active region (at 102), wherein in the edge termination region (at 103, 104), a field plate structure (301/10) is arranged around the active region (at 102) and comprises at least one electrically conductive track (301/10) electrically connected to a first potential of the first load terminal (202) at a first joint and, at a second joint, electrically connected to a second potential of the second load terminal (201), wherein the at least one electrically conductive track (301/10) forms at least n crossings (FIG. 4/¶ 0083), wherein n is greater 5, with a straight line (FIG. 3, FIG. 8/A-A’) that extends from the active region (at 102) towards an edge of the edge termination region (at 103, 104), wherein: the difference in potential (150V) between adjacent two of the n crossings (FIG. 4/¶ 0083) increases in at least 50% of the length of the straight line (FIG. 3, FIG. 8/A-A’); and/or the difference in potential within, with respect to the active region (at 102), the first 20% of the length of straight line (FIG. 3, FIG. 8/A-A’) is less than 10% of the total difference in potential along the straight line (FIG. 3, FIG. 8/A-A’) (See Shan Fig. 3, Fig. 4, Fig. 8, Page 2, Page 3, Page 6, Page 7 and Tada Fig. 1, Fig. 2, Fig. 13, Fig. 24, Fig. 26, Fig. 27, ¶ 0018-¶ 0022, ¶ 0081-¶ 0085, ¶ 0095, ¶ 0097, ¶ 0100), such that the at least one electrically conductive track that is highly resistive provides almost uniform potential gradients across the depletion layer at high voltage and temperature to obtain a reliable device having a stable breakdown voltage. As to claim 2, Shan in view of Tada further discloses wherein the difference in potential (150V) within, with respect to the active region (at 102), the first 20% of the length of the straight line (FIG. 3, FIG. 8/A-A’) is less than half of the difference in potential (750V) within the last 20% of the length of the straight line (FIG. 3, FIG. 8/A-A’) (See Tada Fig. 13).
As to claim 3, Shan in view of Tada further discloses wherein both the difference in potential within, with respect to the active region (at 102), the first 20% of the length of the straight line (FIG. 3, FIG. 8/A-A’), and the difference in potential within, with respect to the active region (at 102), the last 20% of the length of the straight line (FIG. 3, FIG. 8/A-A’), are less than the difference in potential within another 20% of the length of the straight line (FIG. 3, FIG. 8/A-A’) between the first 20% and the last 20% of the straight line (FIG. 3, FIG. 8/A-A’) (See Tada ¶ 0082) (Notes: the diodes are selected within the length such that difference in potential is greater in the another 20%, where the length between the first and last 20% is longer to obtain a higher potential difference).
As to claim 4, Shan in view of Tada further discloses wherein an ohmic resistance between adjacent two of the n crossings (FIG. 4/¶ 0083) increases in at least 50% of the length of the straight line (FIG. 3, FIG. 8/A-A’) (See Tada ¶ 0082) (Notes: the series of didoes increase the ohmic resistance). As to claim 6, Shan in view of Tada further discloses wherein an electric conductivity of the at least one track (301/10) decreases in a portion of the track (301/10) that forms the crossings (FIG. 4/¶ 0083) in a portion corresponding to at least 50% of the length of the straight line (FIG. 3, FIG. 8/A-A’) (See Tada Fig. 27, ¶ 0100) (Notes: the different resistive materials have relatively lower and higher electric conductivity). As to claim 8, Shan in view of Tada further discloses wherein the first joint is arranged in proximity to the active region (at 102) or, respectively, in the active region (at 102), and wherein the second joint is arranged in proximity to the edge or, respectively, at the edge (See Shan Fig. 3, Fig. 8 and Tada Fig. 1, Fig. 2). As to claim 18, Shan in view of Tada further discloses wherein the field plate structure (301/10) arranged around the active region (at 102) comprises two or more electrically conductive tracks (73, 74) arranged in an interleaved manner with respect to each other (See Tada Fig. 24, ¶ 0095). As to claim 20, Shan in view of Tada further discloses wherein the resistance measured between the first joint and the second joint is at least 100, or at least 1000 times as great as a lowest sheet resistance of a material of the at least one track (301/10) (See Tada Fig. 27, ¶ 0101) (Notes: Silicon 6.40 x 102 and Aluminum 2.82 x 10-8 by https://cleanroom.byu.edu/resistivities). As to claim 21, Shan in view of Tada further discloses wherein the field plate structure (301/10) is coil-shaped (See Shen Fig. 4 and Tada Fig. 1).
As to claim 22, Shan in view of Tada further discloses wherein the straight line (FIG. 3, FIG. 8/A-A’) is perpendicular to the edge (See Shan Fig. 3, Fig. 8 and Tada Fig. 1). As to claim 23, Shan in view of Tada discloses a method of producing a power semiconductor device, the method comprising: forming an active region (at 102) configured to conduct a load current between a first load terminal (202) and a second load terminal (201); and forming an edge termination region (at 103, 104) surrounding the active region (at 102), wherein in the edge termination region (at 103, 104), a field plate structure (301/10) is arranged around the active region (at 102) and comprises at least one electrically conductive track (301/10) electrically connected to a first potential of the first load terminal (202) at a first joint and, at a second joint, electrically connected to a second potential of the second load terminal (201), wherein the at least one electrically conductive track (301/10) forms at least n crossings (FIG. 4/¶ 0083), wherein n is greater 5, with a straight line (FIG. 3, FIG. 8/A-A’) that extends from the active region (at 102) towards an edge of the edge termination region (at 103, 104), wherein the difference in potential (150V) between adjacent two of the n crossings (FIG. 4/¶ 0083) increases in at least 50% of the length of the straight line (FIG. 3, FIG. 8/A-A’), and/or the difference in potential within, with respect to the active region (at 102), the first 20% of the length of straight line (FIG. 3, FIG. 8/A-A’) is less than 10% of the total difference in potential along the straight line (FIG. 3, FIG. 8/A-A’) (See Shan Fig. 3, Fig. 4, Fig. 8, Page 2, Page 3, Page 6, Page 7 and Tada Fig. 1, Fig. 2, Fig. 13, Fig. 24, Fig. 26, Fig. 27, ¶ 0018-¶ 0022, ¶ 0081-¶ 0085, ¶ 0095, ¶ 0097, ¶ 0100), such that the at least one electrically conductive track that is highly resistive provides almost uniform potential gradients across the depletion layer at high voltage and temperature to obtain a reliable device having a stable breakdown voltage.
Response to Arguments
Applicant's arguments with respect to claims 1 and 23 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DAVID CHEN/Primary Examiner, Art Unit 2815