Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on 07/07/2022 and 05/16/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
Applicant has amended the specification clarifying that 124a is a fourth semiconductor element. As such, the objection is withdrawn.
Claim Rejections - 35 USC § 112
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In particular, it is unclear what the Applicant means by, “the buffer layer is overlapped with the chip body in a direction parallel to the first surface”. The Examiner considers two possible interpretations. The first is that the chip body overlaps the buffer layer along the first direction as illustrated below:
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528
1042
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Annotated FIG. 1 #3
As is evident in the figure above, since the chip body is vertically stacked directly on the buffer layer, the chip body overlaps the buffer layer along a direction parallel to the first surface.
The second interpretation is that the chip body overlaps the buffer layer and that the direction in which the chip body overlaps the buffer layer is the direction parallel to the first surface as illustrated below using an annotated version of Applicant’s FIG. 3:
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612
820
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Applicant’s FIG. 3 #1
The Examiner notes that the first interpretation is more representative of the claim language. Further, Applicant’s specification makes no mention of an overlap direction parallel to the first surface. Therefore, the Examiner will interpret the above limitation according to the first interpretation.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4-7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al (CN 110957992 A), and further in view of Tseng et al (US 20050102827 A1). Jiang et al and Tseng et al will be referenced to as Jiang and Tseng henceforth.
Regarding Claim 1,
Jiang teaches:
“An electronic device, comprising: a substrate (substrate 2, [0029], FIG. 1);
a first semiconductor element (wave filter chip 1, plastic sealing material, functional area 11, [0029], [0018], FIG. 1) disposed on the substrate and electrically connected to the substrate (FIG. 1: electrically connected through 12.) wherein the first semiconductor element has a first surface (annotated FIG. 1 #1) away from the substrate (Jiang: annotated FIG. 1 #1: the first surface is vertically away from the substrate);
and a first protective structure (plastic packaging structure 5, [0029], FIG. 1) covering at least a portion of the first surface (annotated FIG. 1 #1: 5 partially surrounds a first surface), a chip body (wave filter chip 1, [0029], FIG. 1), and a buffer laver (plastic sealing material, [0018], FIG. 1), and the buffer layer is adjacent to or surrounds the chip body (annotated FIG. 1 #2: the buffer layer is beneath the chip body.), wherein the buffer layer is overlapped with the chip body in a direction parallel to the first surface (annotated FIG. 1 #3: The buffer layer is overlapped by the chip body along a direction parallel to the first surface.).”
Jiang doesn’t substantially teach:
“wherein the first semiconductor element further comprises a carrier board, the chip body is disposed on one side of the carrier board,”
However, Tseng teaches:
“wherein the first semiconductor element further comprises a carrier board (Tseng: transparent substrate 310, [0024], FIG. 3D), the chip body is disposed on one side of the carrier board (Tseng: FIG. 3D: chip 320 is below a bottom side of carrier board 320), ”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Jiang is modifiable in view of Tseng.
This is because the invention of Tseng teaches that covering a functional area with glass brings the improvement of protecting the functional area and prevents moisture and particles from entering the functional area (Tseng: [0007]).
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346
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Annotated FIG. 1 #1
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348
840
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Annotated FIG. 1 #2
Regarding Claim 2,
Jiang/Tseng teaches:
“The electronic device of claim 1, wherein(Tseng: [0024]).”
Regarding Claim 4,
Jiang/Tseng teaches:
“The electronic device of claim 1, wherein the first protective structure is disposed between the substrate and the first semiconductor element (Jiang: FIG. 1: the first protective structure is vertically between the substrate and the first semiconductor element.).”
Regarding Claim 5,
Jiang/Tseng teaches:
“The electronic device of claim 4, further comprising: a material layer (Jiang: outer dam layer 33, [0030], FIG. 1) disposed between the substrate and the first semiconductor element (Jiang: FIG. 1: 33 is vertically between the substrate and the first semiconductor element.), and the material layer is in contact with the first protective structure (Jiang: FIG. 1).”
Regarding Claim 6,
Jiang/Tseng teaches:
“The electronic device of claim 5, wherein an orthographic projection of the material layer on the substrate is overlapped with an orthographic projection of [[a]] the chip body (Jiang: wave filter chip 1, [0029], FIG. 1) of the first semiconductor element on the substrate (Jiang: FIG. 1: the chip body and material layer are overlapping in an orthographic projection onto the substrate.).”
Regarding Claim 7,
Jiang/Tseng teaches:
“The electronic device of claim 5, wherein an orthographic projection of the material layer on the substrate is not overlapped with an orthographic projection of a pad (Jiang: input/output port 12, [0033], FIG. 1) of the first semiconductor element on the substrate (Jiang: FIG. 1: 12 and 3 are not overlapping in an orthographic projection onto the substrate.).”
Regarding Claim 17,
Jiang/Tseng teaches:
“The electronic device of claim 1, wherein a material of the first protective structure comprises, for example, silicone, acrylic, urethane, or epoxy (Jiang: [0037]: plastic encapsulation material LM8895 is an epoxy as would be understood by one of ordinary skill in the art.).”
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Jiang/Tseng as applied to claims 1, 2, and 4-7, and 17 above, and further in view of Lee et al (US 20180374798 A1). Lee et al will be referenced to as Lee henceforth.
Regarding Claim 14,
Jiang/Tseng teaches:
“The electronic device of claim 1”
Jiang/Tseng doesn’t substantially teach:
“further comprising: a partition structure surrounding the first protective structure.”
However, Lee teaches:
“The electronic device of claim 1, further comprising: a partition structure (Lee: conductive spaced apart pillar structures 131, shielding layer 150, [0028], [0044], FIG. 8C) surrounding the first protective structure (Lee: FIG. 8C: 131 and 150 together surround package body 140 which physically protects semiconductor dies 120a and 120b).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Jiang/Tseng is modifiable in view of Lee.
This is because the invention of Lee provides the benefit of reducing electromagnetic interference (EMI) radiation from affecting the behavior of the semiconductor dies. Such interference may disrupt the electromagnetic signals in the semiconductor device disrupting or causing errors in its operation as one of ordinary skill in the art would recognize.
Response to Arguments
Applicant’s amendments to the Claims have not overcome the Examiner’s 103 rejections. The Examiner’s rejections are not withdrawn.
Applicant’s arguments have been fully considered and are considered not persuasive. See the Examiner’s 112(b) rejection above.
Applicant also wrote on page 12 of their remarks that:
“Jiang’s wave filter chip 1 (highlighted in yellow for emphasis in annotated FIG. 1 is positioned above the plastic sealing material”
The Examiner would like to remind the Applicant that responses to the Examiner’s actions will be displayed in gray-scale to the Examiner and therefore these yellow highlights are not visible to the Examiner.
In the interest of compact prosecution, if the Applicant were to amend an independent claim 1 by replacing the limitation:
“wherein the buffer layer is overlapped with the chip body in a direction parallel to the first surface.”
with
“wherein the chip body overlaps the buffer layer along a direction perpendicular to the first surface.”
It would overcome the current rejections for claim 1. The Examiner is available for interview at Applicant’s convenience for discussion of claim amendments.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ whose telephone number is (571)272-2715. The examiner can normally be reached Monday - Friday 8:30 AM to 6:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDRE X RAMIREZ/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights