Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is nonfinal and is in response to claims filed on 01/12/2026 via amendment. Claims 6 and 8-26 are pending examination. Claims 6, 11-12, 14-15, and 19 are currently amended. Claims 8-10, 13, 16-18, and 20 are as originally filed. Claims 21-26 are newly presented.
Information Disclosure Statement
The Information Disclosure Statements (IDS) submitted on 11/13/2023 and 04/29/2024 are in compliance with the provisions of 37 CFR 1.97, 1.98, and MPEP §609. They have been placed in the application file, and the information referred to therein has been considered as to the merits.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 6 and 8-26 are rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract ideas without significantly more.
With regards to claim 6, at step 1, the claim is directed to a method, which is a statutory category of invention.
At Step 2A Prong 1, the examiner notes that the claim is directed to mental processes and/or mathematical concepts. The claim language has been reproduced below:
A method comprising: (mental process, evaluation)
reading a first set of bits from a set of weighting vectors from a memory device utilizing a first read energy; (mental process, evaluation)
multiplying a set of inputs by the first set of bits to obtain a first product; (mathematical calculation)
bit shifting an accumulated product sum to generate a bit-shifted value; (mathematical calculation
adding the first product to the bit-shifted value to generate an updated value for the accumulated product sum; (mathematical calculation)
in response to detecting that the updated value for the accumulated product sum is positive and a bit-condition of the updated value for the accumulated product sum changes from a 0 to a 1, asserting a reduced read energy signal; and (mental process evaluation)
after asserting the reduced read energy signal, reading a second set of bits from the set of weighting vectors from the memory device utilizing a second read energy less than the first read energy. (mental process, evaluation)
Each of the non-bolded limitations are mental processes and/or mathematical calculations. The “A method comprising:” limitation is an evaluation mental process that can be performed by choosing what the method comprises. The “a first set of bits from a set of weighting vectors” limitation is an evaluation mental process that can be performed by choosing how the vectors are input. The “multiplying a set of inputs by the first set” limitation is a mathematical calculation that can be performed multiplying the inputs by the bits by hand using pen and paper. The “bit shifting an accumulated product sum” limitation is a mathematical calculation that can be performed by shifting the product sum by hand using pen and paper. The “adding the first product to the bit-shifted value” limitation is a mathematical calculation that can be performed by adding the product and bit-shifted value by hand using pen and paper. The “in response to detecting that the updated value for the accumulated product sum is positive and a bit-condition” limitation is an evaluation mental process that can be performed by seeing if those conditions are true and asserting the reduced read energy. The “after asserting the reduced read energy signal,” limitation is an evaluation mental process that can be performed by choosing what happens after the reduced read energy is asserted.
At step 2A Prong 2, the additional elements are bolded above. The “reading” limitations, as claimed under BRI, are additional elements that are insignificant extra-solution activity. The ‘reading’ in the context of the claim encompasses mere data gathering. The remaining additional elements amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f).
Under Step 2B, the claim recites “reading a first set of bits from a set of weighting vectors”, “reading a second set of bits from the set of weighting vectors”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claim 21, it recites similar language to claim 1and is rejected for, at least, the same reasons therein. Herein claim 21 is directed towards the statutory category of a method, thus also satisfying step 1. At step 2A prong 1, the claim does not recite any additional limitations. Moreover under step 2A prong 2, the additional elements of the multiplier circuit, the adder circuit, the dynamic read circuit, etc. are no more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under Step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 14, at step 1, the claim is directed to a machine, which is a statutory category of invention.
At Step 2A Prong 1, the examiner notes that the claim is directed to mental processes and/or mathematical concepts. The claim language has been reproduced below:
A device comprising: (mental process, evaluation)
a computer readable memory, the computer readable memory storing a set of inputs and a corresponding set of weighting vectors; (mental process, evaluation)
a multiply accumulate device including (mental process, evaluation) an adder, a multiplier, and a partial sum (PS) register, the PS register configured to (mental process, evaluation) store a PS that corresponds to accumulated results from iterative product sum operations of the set of inputs and the corresponding set of weighting vectors; (mathematical calculation)
a multiplexer configured to (mental process, evaluation) provide a bias voltage to a sense amplifier for reading the weighting vectors; and
a dynamic read logic configured to (mental process, evaluation) evaluate the PS, determine whether a reduced read energy (RRE) signal should be asserted, and assert the RRE signal, (mental process, evaluation; mathematical calculation) the RRE signal provided to the multiplexer (mental process, evaluation).
Each of the non-bolded limitations are mental processes and/or mathematical calculations. The “A device comprising” limitation is an evaluation mental process that can be performed by choosing what the device comprises. The “a set of inputs and a corresponding set of weighting vectors” limitation is an evaluation mental process that can be performed by choosing what the memory stores. The “a multiply accumulate device including” limitation is an evaluation mental process that can be performed by choosing what the multiply accumulate device includes. The “the PS register configured to” limitation is an evaluation mental process that can be performed by choosing what the PS register is configured to do. The a PS that corresponds to accumulated results from iterative product sum operations of the set of inputs and the corresponding set of weighting vectors” limitation is a mathematical calculation that can be performed by performing the product sum operations by hand using pen and paper. The “a multiplexer configured to” limitation is an evaluation mental process that can be performed by choosing what the multiplexer is configured to do. The “a dynamic read logic configured to” limitation is an evaluation mental process that can be performed by choosing what the dynamic read logic is configured to do. The “evaluate the PS, determine” limitation is an evaluation mental process and mathematical calculation that can be performed by evaluating the PS, determine whether a reduced read energy signal should be asserted, and assert the RRE signal by hand using pen and paper. The “the RRE signal provided to” limitation is an evaluation mental process that can be performed by choosing where the RRE signal is provided.
At step 2A Prong 2, the additional elements are bolded above. The “storing” limitation, as claimed under BRI, is an additional element that is insignificant extra-solution activity. The ‘storing’ in the context of the claim encompasses mere data gathering. The “reading” limitation, as claimed under BRI, is an additional element that is insignificant extra-solution activity. The ‘reading’ in the context of the claim encompasses mere data gathering. The remaining additional elements amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f).
Under Step 2B, the claim recites “storing a set of inputs and a corresponding set of weighting vectors”, “reading the weighting vectors;”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claim 8, it is directed to mental processes and/or mathematical concepts. The “wherein reading the second set of bits utilizes” limitation is an evaluation mental process that can be performed by choosing what reading utilizes. At step 2A Prong 2, the “reading” limitation, as claimed under BRI, is an additional element that is insignificant extra-solution activity. The ‘reading’ in the context of the claim encompasses mere data gathering. The claim does not recite any other additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception. Under Step 2B, the claim recites “reading the second set of bits utilizes a shorter timing period than a timing period used to read the first set of bits”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claim 9, it is directed to mental processes and/or mathematical concepts. The “wherein reading the second set of bits utilizes a second precharge voltage” limitation is an evaluation mental process that can be performed by choosing what reading utilizes. At step 2A Prong 2, the “reading” limitation, as claimed under BRI, is an additional element that is insignificant extra-solution activity. The ‘reading’ in the context of the claim encompasses mere data gathering. The claim does not recite any other additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception. Under Step 2B, the claim recites “reading the second set of bits utilizes a shorter timing period than a timing period used to read the first set of bits”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claim 10, it is directed to mental processes and/or mathematical concepts. The “wherein reading the second set of bits is performed without providing a positive” limitation is an evaluation mental process that can be performed by choosing how the reading is performed. At step 2A Prong 2, the “reading” limitation, as claimed under BRI, is an additional element that is insignificant extra-solution activity. The ‘reading’ in the context of the claim encompasses mere data gathering. The claim does not recite any other additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception. Under Step 2B, the claim recites “wherein reading the second set of bits is performed without providing a positive precharge voltage for a read amplifier”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claims 11 and 17, they are directed to mental processes and/or mathematical concepts. The “wherein the bit-condition corresponds to a chosen bit of the updated value for the accumulated product sum having a” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the bit-condition corresponds to. The “wherein the first index is equal to a bit-length of a first input of the set of inputs plus a logarithm base2” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the first index is equal to and evaluating the first index by hand using pen and paper. The “wherein the second index equals the first index plus one, wherein the third index” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the second, third, and fourth indices are equal to and evaluating them by hand using pen and paper. Under Steps 2A Prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception. Under Steps 2A Prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 12, it is directed to mental processes and/or mathematical concepts. The “wherein the bit-condition corresponds to a logical combination” limitation is an evaluation mental process and mathematical calculation that can be performed by choosing what the bit-condition is and evaluating it by hand using pen and paper. Under Steps 2A Prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception. Under Steps 2A Prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 13, it is directed to mental processes and/or mathematical concepts. The “wherein reading the second set of bits from the weighting vectors determines” limitation is an evaluation mental process that can be performed by choosing how the reading is performed. At step 2A Prong 2, the “reading” limitation, as claimed under BRI, is an additional element that is insignificant extra-solution activity. The ‘reading’ in the context of the claim encompasses mere data gathering. The claim does not recite any other additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception. Under Step 2B, the claim recites “wherein reading the second set of bits from the weighting vectors determines a value of one or more of the second set of bits incorrectly.”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claim 15, it is directed to mental processes and/or mathematical concepts. The “further comprising” limitation is an evaluation mental process that can be performed by choosing what the device comprises. The “wherein the RRE signal is further provided to” limitation is an evaluation mental process that can be performed by choosing where the signal goes. The “the control block providing” limitation is an evaluation mental process that can be performed choosing what the control block provides. The “the control block configured to” limitation is an evaluation mental process that can be performed choosing what the control block is configured to do. At step 2A Prong 2, the “reading” limitation, as claimed under BRI, is an additional element that is insignificant extra-solution activity. The ‘reading’ in the context of the claim encompasses mere data gathering. None of the remaining additional elements regarding the generic computer components (i.e. the control block, The RRE signal, the computer readable memory, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under Step 2B, the claim recites “reading the computer readable memory when the RRE signal is asserted.”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claim 16, it is directed to mental processes and/or mathematical concepts. The “wherein the dynamic read logic is configured to” limitation is an evaluation mental process that can be performed by choosing what the dynamic read logic is configured to do. The “evaluate the PS by examining a sign bit of the PS and a selected bit of the PS” limitation is an evaluation mental process and mathematical relationship that can be performed by evaluate the PS by hand using pen and paper. Under step 2A Prong 2, none of the additional elements regarding the generic computer components (i.e. the dynamic read logic, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under Step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 18, it is directed to mental processes and/or mathematical concepts. The “wherein the multiplexer is configured to” limitation is an evaluation mental process that can be performed by choosing what the multiplexer is configured to do. The “select the bias voltage based on the RRE signal” limitation is an evaluation mental process that can be performed by choosing the bias voltage based on the RRE signal. The “wherein when the RRE signal is asserted, the multiplexer is configured to” limitation is an evaluation mental process that can be performed by choosing what the multiplexer is configured to do. The “provide a smaller bias voltage than when the RRE signal is not asserted” limitation is an evaluation mental process that can be performed by choosing the bias voltage based on the RRE signal. Under step 2A Prong 2, none of the additional elements regarding the generic computer components (i.e. the multiplexer, the RRE signal, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under Step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 19, it is directed to mental processes and/or mathematical concepts. The “wherein when the RRE signal is asserted, the multiplexer is configured to” limitation is an evaluation mental process that can be performed by choosing what the multiplexer is configured to do. The “wherein when the RRE signal is asserted, the multiplexer is configured to provide a bias voltage which causes the sense amplifier to output” limitation is an evaluation mental process that can be performed by choosing the bias voltage. At step 2A Prong 2, the “output” limitation, as claimed under BRI, is an additional element that is insignificant extra-solution activity. The ‘output’ in the context of the claim encompasses mere data gathering. None of the remaining additional elements regarding the generic computer components (i.e. The RRE signal, the multiplexer, the sense amplifier, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under Step 2B, the claim recites “wherein when the RRE signal is asserted, the multiplexer is configured to provide a bias voltage which causes the sense amplifier to output a zero”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claim 20, it is directed to mental processes and/or mathematical concepts. The “wherein the dynamic read logic is configured to” limitation is an evaluation mental process that can be performed by choosing what the dynamic read logic is configured to do. The “evaluate the PS by examining a sign bit of the PS and a logical combination of two or more selected bits of the PS” limitation is an evaluation mental process and mathematical calculation that can be performed by evaluating the PS by hand using pen and paper. Under step 2A Prong 2, none of the additional elements regarding the generic computer components (i.e. the dynamic read logic, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under Step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 22, it is directed to mental processes and/or mathematical concepts. The “wherein determining whether the dynamic read condition is met comprises” limitation is an evaluation mental process that can be performed by choosing what the determining whether the dynamic read condition is met comprises. The “determining whether a sign bit of the accumulated product sum is zero” limitation is an evaluation mental process and mathematical relationship that can be performed by determining whether a sign bit of the accumulated product sum is zero by hand using pen and paper. The “at least a non-sign bit at a pre-determined bit location of the accumulated product sum is one” limitation is an evaluation mental process and mathematical relationship that can be performed by determining that at least a non-sign bit at a pre-determined bit location of the accumulated product sum is one by hand using pen and paper. Under Steps 2A Prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 23, it is directed to mental processes and/or mathematical concepts. The “wherein a bit index of the pre-determined bit location is equal to N + ceil(log2 M) – 1” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the pre-determined bit location is equal to. The “wherein N is a bit length of a first input vector of the set of input vectors” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what N is equal to. The “M is a total number of vectors in the set of input vectors” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what M is equal to. The “ceil(.) is a round up function” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what ceil(.) is. Under Steps 2A Prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 24, it is directed to mental processes and/or mathematical concepts. The “wherein reading the second set of bits comprises” limitation is an evaluation mental process that can be performed by choosing what the reading comprises. The “the second set of bits from the set of weighting vectors using a second read voltage” limitation is an evaluation mental process that can be performed by choosing what the read voltage is. At step 2A Prong 2, the “reading” limitation, as claimed under BRI, is an additional element that is insignificant extra-solution activity. The ‘reading’ in the context of the claim encompasses mere data gathering. None of the remaining additional elements regarding the generic computer components (i.e. The memory device, the first read voltage, the second read voltage, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under Step 2B, the claim recites “wherein reading the second set of bits comprises reading, from the memory device, the second set of bits”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claim 25, it is directed to mental processes and/or mathematical concepts. The “wherein reading the first set of bits comprises” limitation is an evaluation mental process that can be performed by choosing what the reading comprises. The “the first set of bits from the set of weighting vectors within a first period of time” limitation is an evaluation mental process that can be performed by choosing what the first period of time is. The “wherein reading the second set of bits comprises” limitation is an evaluation mental process that can be performed by choosing what the reading comprises. The “the second set of bits from the set of weighting vectors within a second period of time” limitation is an evaluation mental process that can be performed by choosing what the second period of time is. At step 2A Prong 2, the “reading” limitations, as claimed under BRI, are additional elements that are insignificant extra-solution activity. The ‘reading’ in the context of the claim encompasses mere data gathering. None of the remaining additional elements regarding the generic computer components (i.e. The memory device, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under Step 2B, the claim recites “reading, from the memory device, the first set of bits”, “reading, from the memory device, the second set of bits”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
With regards to claim 26, it is directed to mental processes and/or mathematical concepts. The “wherein reading the second set of bits from the set of weighting vectors using the second read energy produces one or more bit errors in the second set of bits” limitation is an evaluation mental process that can be performed by choosing what happens when reading the bits. At step 2A Prong 2, the “reading” limitation, as claimed under BRI, is an additional element that is insignificant extra-solution activity. The ‘reading’ in the context of the claim encompasses mere data gathering. Under Step 2B, the claim recites “wherein reading the second set of bits from the set of weighting vectors using the second read energy”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092- 93.
Allowable Subject Matter
Claims 6 and 8-26 would be allowable if rewritten to overcome the rejections under 35 U.S.C. 101 set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Chiu et al. (“A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors”) teaches a sum of products and using the partial sum to make calculations more efficient. They fail to teach asserting a reduced read energy based on if the partial sum is positive and a bit-condition.
Berger et al. (US 20210089455 A1), teaches reducing the power consumption of read operations. They fail to teach asserting a reduced read energy based on if the partial sum is positive and a bit-condition.
While prior art teaches of circuits to perform sums of products and reducing the read energy required, they fail to teach asserting a reduced read energy based on if the partial sum is positive and a bit-condition. They also fail to teach picking between the normal read energy and the reduced read energy.
Conclusion
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/J.O.G./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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