Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
Claim 38 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 38 recites the limitation "the first substrate" in the first line. There is insufficient antecedent basis for this limitation in the claim. Specifically, no such term is previously disclosed in claim 1 (upon which claim 36 depends), and at best is either used to discuss the “array substrate” or the “first interposer”. Due to claim 38 also disclosing a relationship between the first shielding layers of the first interposer and the at least one ground via (which the “first substrate” supposedly comprises), it is interpreted that the term “the first substrate” is referring to the “first interposer” of claim 1, and will be analyzed and discussed as such.
Claim Rejections - 35 USC § 103
Claim(s) 1, 4-7, 21-25, and 36-38 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US Patent No. 10595407) in further view of Baek (KR 20200055277A) and Vogt (PGPub No. 20160315055).
Regarding claim 1, Kim teaches an array substrate comprising: a first dummy forming an outer perimeter of the array substrate, wherein an inner space is formed to be surrounded by the first dummy (Fig. points to a PCB laminated structure 200 comprising a first substrate 220 with an outer perimeter (first dummy) and a central area (inner space).); a first interposer disposed in the inner space surrounded by the first dummy and having a closed-loop shape, wherein a first inner space is formed to be surrounded by the first interposer (Fig. 3 and 4A point to an interposer assembly 210 (first interposer) positioned on the central area (inner space) of the first substrate 220 and creating a smaller central area (first inner space).); a second interposer disposed in the first inner space and having a closed-loop shape, wherein a second inner space is formed to be surrounded by the second interposer; and a second dummy disposed in the second inner space (The court has held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). Thus, it is considered obvious that one of ordinary skill in the art would form a duplicate second interposer within the first interposer that surrounds a smaller central area (second inner space) of the substrate 220 (second dummy) in order to provide greater physical stability and/or increase signal density.), wherein the first interposer includes: a first side surface including a first region on which a first conductive material is plated and second regions on which the plurality of first bridges are connected, a second side surface including a third region on which a second conductive material is plated and fourth regions on which the plurality of second bridges are connected, wherein the second side surface is opposite to the first side surface facing the first dummy, and wherein a conductive material is not plated on the second regions and the fourth regions (Fig. 4A points to metal coating layers 212 formed on the inner (second side surface) and outer (first side surface) of the interposer assembly 210.).
Kim fails to teach a plurality of first bridges connecting the first dummy of the array substrate and the first interposer; a plurality of second bridges connecting the first interposer and the second interposer; and a plurality of third bridges connecting the second interposer and the second dummy, first shielding layers, wherein each of the first shielding layers is disposed inside the first interposer to be adjacent to each of the second regions and has a width wider than a width of each of the second regions, and second shielding layers, wherein each of the second shielding layers is disposed inside the first interposer to be adjacent to each of the fourth regions and has a width wider than a width of each of the fourth regions.
Baek teaches a plurality of first bridges connecting the first dummy and the first interposer (Fig. 1 points to a PCB panel 100 comprising a series of extensions (a plurality of first bridges) between the PCBs 111/121 and the outer perimeter (first dummy) of the panel.); a plurality of second bridges connecting the first interposer and the second interposer (Id. points to a series of extensions (a plurality of second bridges) between the PCBs 111/121 and a region A.); and a plurality of third bridges connecting the second interposer and the second dummy (In light of Kim as discussed above, it is considered obvious that one of ordinary skill in the art would not only form an additional second interposer, but form an additional plurality of bridges (a plurality of third bridges) in order to further improve physical stability from within a central area.). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Kim and Baek, such that multiple pluralities of bridges are formed in order to create an assembly structure to aid in the formation of the first and second interposers.
Kim et al. still fails to teach first shielding layers, wherein each of the first shielding layers is disposed inside the first interposer to be adjacent to each of the second regions and has a width wider than a width of each of the second regions, and second shielding layers, wherein each of the second shielding layers is disposed inside the first interposer to be adjacent to each of the fourth regions and has a width wider than a width of each of the fourth regions.
Vogt teaches first shielding layers, wherein each of the first shielding layers is disposed inside the first interposer to be adjacent to each of the second regions and has a width wider than a width of each of the second regions, and second shielding layers, wherein each of the second shielding layers is disposed inside the first interposer to be adjacent to each of the fourth regions and has a width wider than a width of each of the fourth regions (Fig. 1 and [0043] point to an interposer layer 14 comprising one or more electrical webs 46 (first shielding layers; second shielding layers) which can be used to electrical shield components. It is considered obvious that one of ordinary skill in the art would rearrange the electrical webs 46 (i.e., adjust the placement, change the width, etc.) in order to have specific control over the shielding properties and its effect on nearby components.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kim et al. and Vogt, such that the first interposer comprises a first and second shielding layers in order to provide a controlled level of protection against electromagnetic interference.
Regarding claim 4, Kim teaches wherein the first interposer and the second interposer are simultaneously formed in a manufacturing process (Fig. 4A points to the interposer assembly 210 (first interposer; second interposer). It is considered obvious that both interposers would be formed simultaneously in order to streamline the manufacturing process.).
Regarding claim 5, Kim teaches wherein the first interposer and the second interposer are formed to have the same height (Fig. 4A points to the interposer assembly 210 (first interposer; second interposer). It is considered obvious that both interposers would be formed to have the same height in order to streamline the manufacturing process.).
Regarding claim 6, Kim teaches a first plating layer corresponding to the first conductive material and formed on the first side surface of the first interposer, a second plating layer corresponding to the second conductive material and formed on the second side surface of the first interposer (Fig. 3 points to the interposer assembly 210 (first interposer) comprising metal coating layers 212 formed on both the outer surfaces (first plating layer) and the inner surfaces (second plating layer).), a third plating layer formed on a third side surface of the second interposer, and a fourth plating layer formed on a fourth side surface of the second interposer, wherein the third side surface faces the first interposer and the fourth side surface faces the second dummy (The court has held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). Thus, it is considered obvious that one of ordinary skill in the art would form a duplicate second interposer within the first interposer comprising metal coating layers 212 formed on both the outer surfaces (third plating layer) and the inner surfaces (fourth plating layer) in order to provide greater physical stability and/or increase signal density.).
Regarding claim 7, Baek teaches wherein the plurality of first bridges and the plurality of second bridges are removed to separate the first interposer and the second interposer ([0005] points to discarding the margins (plurality of first bridges) and loss areas (plurality of second bridges).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kim and Baek, such that the plurality of first bridges and the plurality of second bridges are removed in order to clean up the areas around the first and second interposers and create space for further processing.
Regarding claim 21, Kim teaches wherein the first interposer includes a plurality of first conductive vias, and wherein the second interposer includes a plurality of second conductive vias (Figs. 4A-4B point to the interposer assembly 210 (first interposer; second interposer) comprising a signal via 213 and a ground via 214 (plurality of first conductive vias; plurality of second conductive vias).).
Regarding claim 22, Vogt teaches wherein a first shield layer among the first shield layers is disposed adjacent to a bridge among the plurality of first bridges (Fig. 1 and [0043] point to an interposer layer 14 comprising one or more electrical webs 46. It is considered obvious that one of ordinary skill in the art would position/rearrange said electrical web(s) to focus on certain areas that require further shielding, such as an interconnect bridge communicating with external components.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kim et al. and Vogt, such that a first shield layer is disposed adjacent to a bridge among the plurality of first bridges in order to improve the level of shielding by focusing on an area of the interposer in communication with external components.
Regarding claim 23, Vogt teaches wherein the first shield layer includes a conductive material ([0043] points to the electrical webs 46 (first shield layer) which may be formed out of conductive filler material 26.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kim et al. and Vogt, such that the first shield layer is formed of a conductive material in order to provide superior noise immunity.
Regarding claim 24, Vogt teaches wherein a width of the first shield layer is greater than a width of the bridge among the plurality of first bridges (Fig. 1 and [0043] point to an interposer layer 14 comprising one or more electrical webs 46 (first shielding layers; second shielding layers) which can be used to electrical shield components. It is considered obvious that one of ordinary skill in the art would rearrange the electrical webs 46 (i.e., adjust the placement, change the width, etc.) in order to have specific control over the shielding properties and its effect on nearby components.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kim et al. and Vogt, such that a first shield layer is formed with a sufficient width in order to provide an adequate level of noise immunity.
Regarding claim 25, Kim teaches wherein each of the first interposer and the second interposer is disposed between a first printed circuit board and a second printed circuit board (Fig. 3 points to a PCB laminated structure 200 comprising a first substrate 220 (first printed circuit board) and a second substrate 230 (second printed circuit board).).
Regarding claim 36, Vogt teaches wherein a height of each of the first shielding layers is the same as a height of the first interposer, and wherein a height of each of the second shielding layers is the same as the height of the first interposer (Fig. 1 and [0043] point to an interposer layer 14 comprising one or more electrical webs 46 (first shielding layers; second shielding layers) which can be used to electrical shield components. It is considered obvious that one of ordinary skill in the art would rearrange the electrical webs 46 (i.e., adjust the placement, change the height, etc.) in order to have specific control over the shielding properties and its effect on nearby components.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kim et al. and Vogt, such that a first shield layer is formed with a sufficient height in order to provide an adequate level of noise immunity.
Regarding claim 37, Vogt teaches wherein an electromagnetic interference (EMI) on the first interposer is reduced by the first shielding layers and the second shielding layers (Fig. 1 and [0043] point to an interposer layer 14 comprising one or more electrical webs 46 (first shielding layers; second shielding layers), formed from the conductive filler material 26, which can be used to electrical shield components.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kim et al. and Vogt, such that the shielding layers are formed to reduce EMI on the first interposer in order to prevent signal corruption and/or improve power integrity.
Regarding claim 38, Kim in combination with Vogt teaches wherein the first substrate further comprises at least one ground via (Fig. 4B of Kim points to ground vias 214), and wherein the first shielding layers are electrically connected with the at least one ground via (Fig. 1 of Vogt points to the one or more electrical webs 46 (first shielding layers). It is considered obvious that said electrical webs would be grounded in some way so as to safely dump the unwanted electrical/EMI signals.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kim et al. and Vogt, such that the first shielding layers are electrically connected to at least one ground via in order to maintain an adequate level of protection by creating a path of disposal for unwanted interference.
Response to Arguments
Applicant’s arguments, see Remarks, filed 02/13/2026, with respect to the objection and rejection under 35 U.S.C. §112(a) of claim 26 have been fully considered and are persuasive. Both the objection and rejection of said claim have been withdrawn.
Applicant’s arguments, see Remarks, filed 02/13/2026, with respect to the rejection(s) of claim(s) 1 (and by extension any dependent claims) under 35 U.S.C. §103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kim et al. in further view of Vogt (PGPub No. 20160315055).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Patrick L Cullen whose telephone number is (703)756-1221. The examiner can normally be reached Monday - Friday, 8:30AM - 5PM EST.
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/PATRICK CULLEN/ Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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