DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claims
Claims 1-15, 19, 28-29 pending. Claims 16-18, 20-27 and 30 canceled.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the wherein the first spacer covers at least a portion of a sidewall of the second interlayer dielectric layer and at least a portion of a sidewall of the third interlayer dielectric layer, and wherein a sidewall of the first interlayer dielectric layer is spaced apart from a sidewall of the second bit line in claim 1 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, a first spacer including a first portion disposed between the buried dielectric pattern and the upper part of the bit-line contact, wherein the first spacer includes a second portion between the upper contact dielectric pattern and each of the first lower contact dielectric pattern and the second lower contact dielectric pattern in claim 19 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Regarding claim 1. Claim 1 recites the limitation “a first spacer contacting an upper portion of a sidewall of the bit-line contact; a contact insulator contacting a lower portion of the sidewall of the bit-line contact, wherein an upper end of the contact insulator is connected to a bottom surface of the first spacer” and the limitation “wherein the first spacer covers at least a portion of a sidewall of the second interlayer dielectric layer and at least a portion of a sidewall of the third interlayer dielectric layer, and wherein a sidewall of the first interlayer dielectric layer is spaced apart from a sidewall of the second bit line” in the claim language.
Regarding claim 19. Claim 19 recites “a first spacer including a first portion disposed between the buried dielectric pattern and the upper part of the bit-line contact” and “wherein the first spacer includes a second portion between the upper contact dielectric pattern and each of the first lower contact dielectric pattern and the second lower contact dielectric pattern” in the claim language.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-15, 19, 28 and 29 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1. Applicant does not have written support in the originally filed specifications for wherein the first spacer covers at least a portion of a sidewall of the second interlayer dielectric layer and at least a portion of a sidewall of the third interlayer dielectric layer, and wherein a sidewall of the first interlayer dielectric layer is spaced apart from a sidewall of the second bit line.
Claims 2-15 are rejected for dependence upon a 112(a) rejected instance claim.
Regarding claim 19. Applicant does not have written support in the originally filed specifications for wherein the first spacer includes a second portion between the upper contact dielectric pattern and each of the first lower contact dielectric pattern and the second lower contact dielectric pattern.
Claims 28 and 29 are rejected for dependence upon a 112(a) rejected instance claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4-6, 8-12, 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al (U.S. 2013/0256769), Kim et al (U.S. 2014/0117492), Sel et al (U.S. 2007/0075336), Yoo (U.S. 9,368,399) and Kim et al (U.S. 2022/0384449).
Regarding claim 1. Jeong et al discloses a semiconductor memory device (FIG. 1C), comprising:
a first impurity region (FIG. 1C, item 13) in a substrate (FIG. 1C, item 1);
a first bit line (FIG. 1B, item BL above item DC) that crosses (FIG. 1A/B, item BL) over the substrate (FIG. 1B, item 1) and is connected (FIG. 1B, item DC) to the first impurity region (FIG. 1A, item 13);
a second bit line (FIG. 1B, item BL above item 21a) adjacent the first bit line (FIG. 1B, item BL above item DC); and
an interlayer insulator (FIG. 1B, item 27) between the second bit line (FIG. 1B, item BL above item 21a) and the substrate (FIG. 1C, item 1);
a bit-line contact (FIG. 1C, item DC) between the first bit line (FIG. 1C, item BL above item DC) and the first impurity region (FIG. 1C, item 13).
a first spacer (FIG. 1B, item 50)
the contact insulator (FIG. 1B, item 14)
wherein the interlayer insulator (FIG. 1B, item 27) includes a first interlayer dielectric layer (FIG. 1B, item 27)
and wherein a sidewall (FIG. 1B, sidewall of item 27) of the first interlayer dielectric layer (FIG. 1B, item 27) is spaced (FIG. 1B, shows a sidewall of item 27 is spaced apart from sidewall of item BL above item 21a) apart from a sidewall (FIG. 1B, sidewall of item BL above item 21a) of the second bit line (FIG. 1B, item BL above item 21a)
Jeong et al fails to explicitly disclose further comprising
a first spacer contacting an upper portion of a sidewall of the bit-line contact; a contact insulator contacting a lower portion of the sidewall of the bit-line contact, wherein an upper end of the contact insulator is connected to a bottom surface of the first spacer; a contact ohmic layer between the bit-line contact and the first impurity region, wherein a width of a bottom surface of the bit-line contact is greater than a width of a bottom surface of the contact ohmic layer, and wherein the bottom surface of the bit line contact is higher than the bottom surface of the contact ohmic layer relative to an upper surface of the first impurity region.
wherein the interlayer insulator includes a second interlayer dielectric layer, and a third interlayer dielectric layer that are sequentially stacked,
wherein the first spacer covers at least a portion of a sidewall of the second interlayer dielectric layer and at least a portion of a sidewall of the third interlayer dielectric layer
However, Kim et al (‘492) teaches a first spacer (FIG. 18B, item 155) contacting ([0004]) an upper portion of a sidewall (FIG. 18B, a sidewall of item 135) of the bit-line contact (FIG. 18B, item 135); a contact insulator (FIG. 18B, item 153) contacting ([0004]) a lower portion of the sidewall (FIG. 18B, a lower portion of a sidewall of item 135) of the bit-line contact (FIG. 18B, item 135), wherein an upper end of the contact insulator (FIG. 18B, item 153) is connected ([0043],[0061]) to a bottom surface of the first spacer (FIG. 18B, item 155);
Since Jeong et al and Kim et al (‘492) teach bit lines, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor memory device as disclosed to modify Jeong et al with the teachings of a first spacer contacting an upper portion of a sidewall of the bit-line contact; a contact insulator contacting a lower portion of the sidewall of the bit-line contact, wherein an upper end of the contact insulator is connected to a bottom surface of the first spacer as disclosed by Kim et al (‘492). The use of the semiconductor device may include an insulating spacer on an inner side surface of the contact hole in Kim et al provides for separating the bit line contact from the storage node contact such that the bit line contact is electrically isolated from the storage node contact. (Kim et al, [0005]).
Jeong et al and Kim et al (‘492) fails to explicitly disclose further comprising a contact ohmic layer between the bit-line contact and the first impurity region, wherein a width of a bottom surface of the bit-line contact is greater than a width of a bottom surface of the contact ohmic layer, and
wherein the bottom surface of the bit line contact is higher than the bottom surface of the contact ohmic layer relative to an upper surface of the first impurity region, wherein the interlayer insulator includes a second interlayer dielectric layer, and a third interlayer dielectric layer that are sequentially stacked,
wherein the first spacer covers at least a portion of a sidewall of the second interlayer dielectric layer and at least a portion of a sidewall of the third interlayer dielectric layer
However, Sel et al teaches further comprising a contact ohmic layer (FIG. 6, item 111B; [0050]) between the bit-line contact (FIG. 6, item 117) and the first impurity region (FIG. 6, item 101A’), wherein a width (FIG. 6, item W2) of a bottom surface ([0054]-[0055]) of the bit-line contact (FIG. 6, item 117) is greater ([0054]-[0055], i.e. This can increase the contact area between the bit line contact plug 117 and the sub active region 101A' to decrease the contact resistance of the bit line) than a width (FIG. 6, item W1) of a bottom surface ([0055]) of the contact ohmic layer (FIG. 6, item 111B).
Since Jeong et al, Kim et al (‘492) and Sel et al teach bit lines, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor memory device as disclosed to modify Jeong et al and Kim et al (‘492) with the teachings of further comprising a contact ohmic layer between the bit-line contact and the first impurity region, wherein a width of a bottom surface of the bit-line contact is greater than a width of a bottom surface of the contact ohmic layer as disclosed by Sel et al. The use of the increase contact area between the bit line contact plug and the sub active region in Sel et al provides for decreasing the contact resistance of the bit line (Sel et al, [0055]).
Jeong et al, Kim et al (‘492), and Sel et al fails to explicitly disclose wherein the bottom surface of the bit line contact is higher than the bottom surface of the contact ohmic layer relative to an upper surface of the first impurity region.
However, both Sel et and Yoo disclose an ohmic contact layer.
Furthermore, Yoo teaches wherein the bottom surface (FIG. 2A, bottom surface of item 140) of the bit line contact (FIG. 2A, item 140) is higher ([Col 4, lines 10-12], i.e. a barrier film 132A is formed over the ohmic contact layer 130A. A bit line structure 140 is formed over a barrier film 132A) than the bottom surface (FIG. 2A, bottom surface of item 130A) of the contact ohmic layer (FIG. 2A, item 130A) relative to an upper surface (FIG. 2A, upper surface of item 112) of the first impurity region (FIG. 2A, item 112).
Since Jeong et al, Kim et al (‘492), Sel et al and Yoo teach bit line structures, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor memory device as disclosed to modify Jeong et al, Kim et al (‘492), and Sel et al with the teachings of wherein the bottom surface of the bit line contact is higher than the bottom surface of the contact ohmic layer relative to an upper surface of the first impurity region as disclosed by Yoo. The use of a barrier film is formed over the ohmic contact layer and A bit line structure is formed over a barrier film in Yoo provides for bit line parasitic capacitance can be minimized, resulting in improvement of semiconductor device characteristics (Yoo, [Col 9, lines 1-3]).
Jeong et al, Kim et al (‘492), Sel et al and Yoo fail to explicitly disclose
wherein the interlayer insulator includes a second interlayer dielectric layer, and a third interlayer dielectric layer that are sequentially stacked,
wherein the first spacer covers at least a portion of a sidewall of the second interlayer dielectric layer and at least a portion of a sidewall of the third interlayer dielectric layer
However, Kim et al (‘449) teaches wherein the interlayer insulator (FIG. 21B/22A, item 420) includes a second interlayer dielectric layer (FIG. 21B/22A, item 409), and a third interlayer dielectric layer (FIG. 21B/22A, item 411) that are sequentially stacked ([0100]),
wherein the first spacer covers (FIG. 21B/22A, item 321) at least a portion ([0100]) of a sidewall ([0100]) of the second interlayer dielectric layer (FIG. 21B/22A, item 409) and at least a portion ([0100]) of a sidewall ([0100]) of the third interlayer dielectric layer (FIG. 21B/22A, item 411).
Since Jeong et al, Kim et al (‘492), Sel et al, Yoo and Kim et al (‘449) teach bit line structures, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor memory device as disclosed to modify Jeong et al, Kim et al (‘492), Sel et al and Yoo with the teachings of wherein the interlayer insulator includes a second interlayer dielectric layer, and a third interlayer dielectric layer that are sequentially stacked, wherein the first spacer covers at least a portion of a sidewall of the second interlayer dielectric layer and at least a portion of a sidewall of the third interlayer dielectric layer as disclosed by Kim et al (‘449). The use of first, second, and third interlayer dielectric layers that are sequentially stacked, the second and third interlayer dielectric layers and may have sidewalls aligned with that of the bit line BL in Kim et al (‘449) provides for suppressing BBD defects (i.e., defects arising from BBD). (Kim et la (‘449), [0097]).
Regarding claim 4. Jeong et al, Kim et al (‘492), Sel et al, Yoo and Kim et al (‘449) discloses all the limitations of the device as claimed in claim 1 above.
Jeong et al further discloses further comprising: a second impurity region (FIG. 1B, item 11) in the substrate (FIG. 1B, item 1), the second impurity region (FIG. 1B, item 11) being spaced apart (FIG. 1B, item 3) from the first impurity region (FIG. 1B, item 13); and
a storage node pad (FIG. 1B, item 25a) on the second impurity region (FIG. 1B, item 11),
a buried dielectric pattern (FIG. 1B, item 47b) between the storage node pad (FIG. 1B, item 25a) and an upper part of the bit-line contact (FIG. 1B, item DC); and
Wherein the contact insulator (FIG. 1B, item 14) between the storage node pad (FIG. 1B, item 25a) and a lower part of the bit-line contact (FIG. 1B, item DC);
wherein a first spacer (FIG. 1B, item 50) between the buried dielectric pattern (FIG. 1B, item 47b) and the storage node pad (FIG. 1B, item 25a) and between the buried dielectric pattern (FIG. 1B, item 47b) and the bit-line contact (FIG. 1B, item DC),
Kim et al discloses wherein an outer sidewall of the first spacer (FIG. 18B, item 155) is aligned ([0043]) with an outer sidewall of the contact insulator (FIG. 18B, item 153).
Regarding claim 5. Jeong et al, Kim et al (‘492), Sel et al, Yoo and Kim et al (‘449) discloses all the limitations of the device as claimed in claim 4 above.
Kim et al (‘492) further discloses wherein: the contact insulator (FIG. 18B, item 153) surrounds the bit-line contact (FIG. 18B, item 135) and extends beneath the first bit line (FIG. 18B, item 145), and the contact insulator (FIG. 18B, item 153, 133) includes a first lower contact dielectric pattern (FIG. 18B, item 133a) and an upper contact dielectric pattern (FIG. 18B, item 153) that are sequentially stacked ([0042]-[0044]).
Regarding claim 6. Jeong et al, Kim et al (‘492), Sel et al, Yoo and Kim et al (‘449) discloses all the limitations of the device as claimed in claim 5 above.
Jeong et al discloses the upper contact dielectric pattern (FIG. 1B, item 39) and the first lower contact dielectric pattern (FIG. 1B, item 47b).
Kim et al (‘492) discloses further comprising a second lower contact dielectric pattern (FIG. 18B, item 133b) beneath the upper contact dielectric pattern (FIG. 18B, item 153), a sidewall (FIG. 18B, side wall of item 133b) of the second lower contact dielectric pattern (FIG. 18B, item 133b) and a bottom surface (FIG. 18B, bottom side surface of item 133b) of the second lower contact dielectric pattern (FIG. 18B, item 133b) being covered with the first lower contact dielectric pattern (FIG. 18B, item 133a)
Regarding claim 8. Jeong et al, Kim et al (‘492), Sel et al, Yoo and Kim et al (‘449) discloses all the limitations of the device as claimed in claim 4 above.
Jeong et al further discloses
wherein:
the storage node pad (FIG. 1B, item 13) includes a pad silicon layer (FIG. 1B, item 25a), a pad ohmic layer (FIG. 1B, item BC), and a pad metal layer (FIG. 1B, item BEP) that are sequentially stacked ([0073]).
A bottom of the first spacer (FIG. 1B, item 50) is higher than a top of the pad silicon layer (FIG. 1B, item 25a)
Regarding claim 9. Jeong et al, Kim et al (‘492), Sel et al, Yoo and Kim et al (‘449) discloses all the limitations of the device as claimed in claim 1 above.
Sel et al further discloses wherein: each of the bit-line contact (FIG. 3, item 117) and the contact ohmic layer (FIG. 3, item 111B) includes a first metal ([0048]-[0050]), and the first bit line (FIG. 3, item 120) includes a second metal ([0048]-[0050]).
Regarding claim 10. Jeong et al, Kim et al (‘492), Sel et al, Yoo and Kim et al (‘449) discloses all the limitations of the device as claimed in claim 1 above.
Jeong et al further discloses further comprising:
a second impurity region (FIG. 1B, item 11 next to item 13) and a third impurity region (FIG. 1B, item 11 not next to item 13) in the substrate (FIG. 1B, item 1) and spaced apart (FIG. 1B, item 3) from the first impurity region (FIG. 1B, item 13), the first impurity region (FIG. 1B, item 13), the second impurity region (FIG. 1B, item 11 next to item 13), and the third impurity region (FIG. 1B, item 11 not next to item 13) being linearly arranged in a first direction (FIG. 1B, item CAR);
a first storage node pad (FIG. 1B, item 25a next to item 13) on the second impurity region (FIG. 1B, item 11 next to item 13);
a second storage node pad (FIG. 1B, item 25a not next to item 13) on the third impurity region (FIG. 1B, item 11 not next to item 13); and
a pad separation pattern (FIG. 1B, item 21a) between the first storage node pad (FIG. 1B, item 25a next to item 13) and the second storage node pad (FIG. 1B, item 25a not next to item 13),
wherein:
each of the first storage node pad (FIG. 1B, item 25a next to item 13) and the second storage node pad (FIG. 1B, item 25a not next to item 13) includes a pad silicon layer (FIG. 1B, item 25a), a pad ohmic layer (FIG. 1B, item BC), and a pad metal layer (FIG. 1B, item BEP) that are sequentially stacked ([0073]), and
a bottom surface (FIG. 3C, item H1) of the pad separation pattern (FIG. 1B, item 21a) is lower ([0094]) than a bottom surface (FIG. 3E, item H3) of the pad silicon layer (FIG. 1B, item 25a) of each of the first storage node pad (FIG. 1B, item 25a next to item 13) and the second storage node pad (FIG. 1B, item 25a not next to item 13).
Regarding claim 11. Jeong et al, Kim et al (‘492), Sel et al, Yoo and Kim et al (‘449) discloses all the limitations of the device as claimed in claim 10 above.
Jeong et al further discloses
further comprising: the second bit line (FIG. 1B, item BL above item 21a) is disposed on the pad separation pattern (FIG. 1B, item 21a);
wherein the interlayer insulator (FIG. 1B, item 27) is disposed between the second bit line (FIG. 1B, item BL above item 21a) and the pad separation pattern (FIG. 1B, item 21a),
Kim et al (‘449) discloses the second interlayer dielectric layer includes a material different from materials of the first interlayer dielectric layer and the third interlayer dielectric layer ([0100], i.e. The first, second, and third interlayer dielectric layers may include materials different from each other).
Regarding claim 12. Jeong et al, Kim et al (‘492), Sel et al, Yoo and Kim et al (‘449) discloses all the limitations of the device as claimed in claim 11 above.
Kim et al (‘449) discloses further discloses wherein: sidewalls of the second interlayer dielectric layer and the third interlayer dielectric layer are aligned with a sidewall of the second bit line ([0100], i.e. The second and third interlayer dielectric layers 409 and 411 may have sidewalls aligned with that of the bit line BL),
and the sidewall of the first interlayer dielectric layer is not aligned with the sidewall of the second bit line ([0100], i.e. The first interlayer dielectric layer 407 may have a width greater that those of the second and third interlayer dielectric layers 409 and 411).
Regarding claim 14. Jeong et al, Kim et al (‘492), Sel et al, Yoo and Kim et al (‘449) discloses all the limitations of the device as claimed in claim 1 above.
Jeong et al further discloses further comprising the contact insulator (FIG. 1B, item 14) surrounds ([0063],[0069]-[0072]) the bit-line contact (FIG. 1C, item DC),
Sel et al discloses wherein a bottom end of the contact insulator (FIG. 6, item 112) is at a level the same as or higher (FIG 6, shows a bottom of item 112 is higher than a bottom of item 111B) than a level of the bottom surface of the contact ohmic layer (FIG. 6, item 111B).
Regarding claim 15. Jeong et al, Kim et al (‘492), Sel et al, Yoo and Kim et al (‘449) discloses all the limitations of the device as claimed in claim 1 above.
Sel et al further discloses wherein a lateral surface of a lower part of the bit-line contact (FIG. 6, item 117) is aligned (FIG. 6, the bottom of item 117 is aligned with the bottom of item 111B) with a lateral surface of the contact ohmic layer (FIG. 6, item 111B).
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al (U.S. 2013/0256769), Kim et al (U.S. 2014/0117492), Sel et al (U.S. 2007/0075336), Yoo (U.S. 9,368,399) and Kim et al (U.S. 2022/0384449) as applied to claim 1 above, and further in view of Choi et al (U.S. 2016/0233164).
Regarding claim 2. Jeong et al, Kim et al (‘492), Sel et al, Yoo and Kim et al (‘449) discloses all the limitations of the device as claimed in claim 1 above.
Jeong et al further discloses further comprising: a second impurity region (FIG. 1B, item 11) in the substrate (FIG. 1B, item 1), the second impurity region (FIG. 1B, item 11) being spaced apart (FIG. 1B, item 3) from the first impurity region (FIG. 1B, item 13); and
a storage node pad (FIG. 1B, item 25a) on the second impurity region (FIG. 1B, item 11),
wherein:
the storage node pad (FIG. 1B, item 13) includes a pad silicon layer (FIG. 1B, item 25a), a pad ohmic layer (FIG. 1B, item BC), and a pad metal layer (FIG. 1B, item BEP) that are sequentially stacked ([0073]).
Jeong et al, Kim et al (‘492), Sel et al, Yoo and Kim et al (‘449) fail to explicitly disclose a width of a bottom surface of the pad ohmic layer is less than a width of a bottom surface of the pad silicon layer and is greater than a width of a bottom surface of the pad metal layer.
However Choi et al teaches a width (FIG. 21, W2; [0181]-[0182]) of a bottom surface of the pad ohmic layer (FIG. 21, item 140; [0181]-[0182]) is less (FIG 21, width of item W2 is less than a width of item 120) than a width (FIG. 21, width of item 120 below item W2) of a bottom surface of the pad silicon layer (FIG. 21, item 120; [0181]-[0182]) and is greater (item W2 is greater than a width of item 130) than a width (FIG. 21, width of item 130 above item W2) of a bottom surface of the pad metal layer (FIG. 21, item 130; [0181]-[0182]).
Since Jeong et al, Kim et al (‘492), Sel et al, Yoo, Kim et al (‘449) and Choi et al teach bit line contacts, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor memory device as disclosed to modify Jeong et al, Kim et al (‘492), Sel et al, Yoo, and Kim et al (‘499) with the teachings of a width of a bottom surface of the pad ohmic layer is less than a width of a bottom surface of the pad silicon layer and is greater than a width of a bottom surface of the pad metal layer as disclosed by Choi. The use of widths of the metal layer, the conductive barrier layer, and the contact plug sequentially on the metal silicide layer in fourth device region IV may be respectively greater than widths of corresponding elements in Choi et al provides for improved resistance characteristic as between the source/drain region and the contact plug (Choi et al, [Abstract]).
Regarding claim 3. Jeong et al, Kim et al (‘492), Sel et al, Yoo, Kim et al (‘499) and Choi et al discloses all the limitations of the device as claimed in claim 2 above.
Jeong et al further discloses f further comprising a storage node contact (FIG. 1B, item CP) on the pad metal layer (FIG. 1B, item BEP), the storage node contact (FIG. 1B, item CP) being in contact (FIG. 1B, item 60) with the pad metal layer (FIG. 1B, item BEP), wherein: the pad metal layer (FIG. 1B, item BEP) includes a first metal ([0069]), and the storage node contact (FIG. 1B, item 60) includes a second metal ([0069]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al (U.S. 2013/0256769), Kim et al (U.S. 2014/0117492), Sel et al (U.S. 2007/0075336), and Yoo (U.S. 9,368,399) and Kim et al (U.S. 2022/0384449) as applied to claim 1 above, and further in view of Hasunuma (U.S. 2012/0132972).
Regarding claim 13. Jeong et al, Kim et al Sel et al, and Yoo discloses all the limitations of the device as claimed in claim 1 above.
Jeong et al further discloses
Wherein: the bit-line contact (FIG. 1B, item DC) includes an upper part (FIG. 1B, item DC)
the upper part (FIG. 1B, item DC) of the bit-line contact (FIG. 1B, item DC) has a width that increases in a downward direction ([0105]),
Jeong et al, Kim et al and Sel et al fail to explicitly disclose
the bit-line contact includes a lower part,
an intermediate part, when viewed from bottom,
the intermediate part of the bit-line contact has a width that decreases in the downward direction, and
an edge of the lower part of the bit-line contact laterally protrudes from a sidewall of the intermediate part of the bit-line contact.
However, Hasunuma teaches the bit-line contact includes a lower part (FIG. 15, item 18a),
an intermediate part (FIG. 15, item 20), when viewed from bottom (FIG. 15),
the intermediate part (FIG. 15, item 20) of the bit-line contact (FIG. 15, items 18a and 20) has a width ([0051]) that decreases ([0051]) in the downward direction ([0051]), and
an edge of the lower part (FIG. 15, item 18a) of the bit-line contact (FIG. 15, items 18a and 20) laterally protrudes from a sidewall ([0049]-[0051]) of the intermediate part (FIG. 15, item 20) of the bit-line contact (FIG. 15, items 18a and 20).
Since Jeong et al, Kim et al, Sel et al, Yoo and Hasunuma teach bit line contacts, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor memory device as disclosed to modify Jeong et al, Sel et al and Yoo with the teachings of the bit-line contact includes a lower part, an intermediate part, when viewed from bottom, the intermediate part of the bit-line contact has a width that decreases in the downward direction, and an edge of the lower part of the bit-line contact laterally protrudes from a sidewall of the intermediate part of the bit-line contact as disclosed by Hasunuma. The use of the top diameter (diameter) of the bit line contacts 20 is preferably about 120 nm, and the bottom diameter (diameter) is preferably about 93 nm and the top diameter of the cell contacts 18 is preferably about 140 nm, and the bottom diameter is preferably about 93 nm in Hasunuma provides for creating a high-precision, high-density layout of the storage capacitors when the storage node contact pads are laid out at maximum density (Hasunuma, [0012]).
Claim 19, 28, and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (U.S. 2021/0296237), Yoo (U.S. 9,368,399), and Jeong et al (U.S. 2013/0256769).
Regarding claim 19. Kim et al discloses a semiconductor memory device (FIG. 1A, 21; [0022]), comprising:
a device isolation pattern (FIG. 21, item 302) in a substrate (FIG. 21, item 301), the device isolation pattern (FIG. 21, item 302) defining a first active section (FIG. 1A, item ACT first active section), a second active section (FIG. 1A, item ACT second active section), and a third active section (FIG. 1A, item ACT third active section) that are linearly adjacent to each other in a first direction (FIG. 1A, item D2);
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a first impurity region (FIG. 21, item 312A) on the first active section (FIG. 1A, first active section), a second impurity region (FIG. 21, item 312B right of item 312A) on the second active section (FIG. 1A, second active section), and a third impurity region (FIG. 21, item 312B left side of item 312A) on the third active section (FIG. 1A, third active section);
a word line (FIG. 21, item WL) disposed the substrate (FIG. 21, item 301);
a word-line capping pattern (FIG. 21, item 301) on the word line (FIG. 21, item WL);
a bit-line contact (FIG. 21 and 23A, item DC) on the first active section (FIG. 21, item 312a of first active section);
a bit line (FIG. 21, item BL) on the bit-line contact (FIG. 21, item DC), the bit line (FIG. 21, item BL) crossing over the word line (FIG. 21 and 23A, item WL);
a first storage node pad (FIG. 21, item BC right of item 312A) on the second active section (FIG. 21, item 312B right of item 312A); a second storage node pad (FIG. 21, item BC left of item 312A) on the third active section (FIG. 21, item 312B left of item 312A);
a buried dielectric pattern (FIG. 21, item AG) between the first storage node pad (FIG. 21, item BC right of item 312A) and an upper part of the bit- line contact (FIG. 21, item DC);
a first spacer (FIG. 21, item 321) including a first portion (annotated FIG. 21, first portion of item 321) disposed between the buried dielectric pattern (FIG. 21 and 23A, item AG) and the upper part of the bit-line contact (FIG. 21, item DC)
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a first lower contact dielectric pattern (FIG. 21, item 22B) between the bit-line contact (FIG. 21, item DC) and the first storage node pad (FIG. 21, item BC right of item 312A), the first lower contact dielectric pattern (FIG. 21, item 22B) surrounding a lower part of the bit-line contact (FIG. 21, item DC); and
an upper contact dielectric pattern (FIG. 21, item 22U and 22AU) beneath the bit line (FIG. 21, item BL) and on the first lower contact dielectric pattern (FIG. 21, item 22B and 22AB).
wherein the first lower contact dielectric pattern (FIG. 21, section B-B’, item 22B) and the upper contact dielectric pattern (FIG. 21, section B-B’, item 22U) are connected to a sidewall (FIG. 21, section B-B’, a sidewall of item DC) the bit-line contact (FIG. 21, section B-B’, item DC), and
wherein an upper surface (FIG. 21, upper surface of item 22U) of the upper contact dielectric pattern (FIG. 21, item 22U) is coplanar with an upper surface (FIG. 21, upper surface of item DC) of the bit-line contact (FIG. 21, item DC)
and a second lower contact dielectric pattern (FIG. 21, item 22AB) disposed between the first lower contact dielectric pattern (FIG. 21, section B-B’, item 22AB) and the first storage node pad (FIG. 21, item BC right of item 312A),
wherein the first spacer (FIG. 21, item 321) includes a second portion (FIG. 21, second portion of item 321) between the upper contact dielectric pattern (FIG. 21, section B-B’, item 22AU) and each of the first lower contact dielectric pattern (FIG. 21, section B-B’, item 22B) and the second lower contact dielectric pattern (FIG. 21, item 22AB)
Kim et al fails to explicitly disclose a contact ohmic layer between the first active section and the bit-line contact; a pad separation pattern between the first storage node pad and the second storage node pad;
However, Yoo teaches a contact ohmic layer (FIG. 2A, item 130A) between ([Col 4, lines 3-17]) the first active section (FIG. 2A, item 112) and the bit-line contact (FIG. 2A, item 140)
Since Kim et al and Yoo teach bit line structures, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor memory device as disclosed to modify Kim et al with the teachings of a contact ohmic layer between the first active section and the bit-line contact as disclosed by Yoo. The use of a barrier film is formed over the ohmic contact layer and A bit line structure is formed over a barrier film in Yoo provides for bit line parasitic capacitance can be minimized, resulting in improvement of semiconductor device characteristics (Yoo, [Col 9, lines 1-3]).
Kim et al and Yoo fail to explicitly disclose a pad separation pattern between the first storage node pad and the second storage node pad.
However, Jeong et al teaches a pad separation pattern (FIG. 1B, item 21a) between ([0063]) the first storage node pad (FIG. 1B, item 25a next to item 13) and the second storage node pad (FIG. 1B, item 25a not next to item 13).
Since Kim et al, Yoo and Jeong et al teach bit line structures, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor memory device as disclosed to modify Kim et al and Yoo with the teachings of a pad separation pattern between the first storage node pad and the second storage node pad as disclosed by Jeong et al. The use of isolation patterns may be provided between adjacent storage node pads in Jeong et al provides for the storage node pads, which will be formed in subsequent steps, to be electrically isolated from each other (Jeong et al, [0092]).
Regarding claim 28. Kim et al, Yoo, and Jeong et al discloses all the limitations of the device as claimed in claim 19 above.
Kim et al and Yoo et al fails to explicitly disclose wherein the upper contact dielectric pattern has a thickness of about 4 nm to about 10 nm.
However, Jeong et al discloses the wherein the upper contact dielectric pattern (FIG. 1B, item 39) has a thickness of about 4 nm to about 10 nm ([0070]),
Since Kim et al, Yoo and Jeong et al teach bit line structures, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor memory device as disclosed to modify Kim et al and Yoo with the teachings of wherein the upper contact dielectric pattern has a thickness of about 4 nm to about 10 nm as disclosed by Jeong et al. The use of spacer with this thickness in Jeong et al provides for the thickness allows the storage node pad to be effectively separated electrically from the bit line node contact DC er (Jeong et al, [0070]).
Regarding claim 29. Kim et al, Yoo, and Jeong et al discloses all the limitations of the device as claimed in claim 19 above.
Kim et la further discloses the wherein a bottom end of the first lower contact dielectric pattern (FIG. 21, section B-B’, item 22B) is connected to the bit-line contact (FIG. 21, section B-B’, item DC).
Response to Arguments
Applicant's arguments filed June 29, 2026. have been fully considered but they are not persuasive.
Applicant has invoked 102(b)(2)(c) exception on page 21 of applicant’s remarks, therefore Jang et al (U.S. 2023/0039205) as prior art is withdrawn.
On page 17 of applicant’s remarks, applicant appears to argue that Lee fails to disclose applicant’s amended claim limitation of wherein the interlayer insulator includes a first dielectric layer, a second dielectric layer, and a third dielectric layer that are sequentially stacked
Examiner respectfully points out that Lee was not used to disclose applicant’s amended claim limitation, and that Jeong et al, Kim et al (‘492), Sel et al, Yoo and Kim et al (‘449) discloses applicant’s amended claim limitation.
On page 20 of applicant’s remarks, applicant appears to argue that Jeong does not disclose wherein a bottom end of the contact insulator is at the same level as the bottom surface of the bit-line contact.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., wherein a bottom end of the contact insulator is at the same level as the bottom surface of the bit-line contact) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
On page 21 of applicant’s remarks, applicant appears to argue that Jang et al cannot be used for claim 11.
Examiner respectfully points out that Jeong et al, Kim et al (‘492), Sel et al, Yoo and Kim et al (‘449) discloses applicant’s claim 11 limitation.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
On page 21 of applicant’s remarks, applicant appears to argue that the amended claim limitations of a second lower contact dielectric pattern disposed between the first lower contact dielectric pattern and the first storage node pad are not address in the rejection.
Examiner respectfully disagrees with applicant’s assertion, and that applicant’s amended claim limitations are addressed in the rejection above.
On page 24 of applicant’s remarks, applicant appears to argue that Kim et al FIG. 21 and 23A fails to disclose the amended claim limitations of a second lower contact dielectric pattern disposed between the first lower contact dielectric pattern and the first storage node pad, wherein the first spacer includes a second portion between the upper contact dielectric pattern and each of the first lower contact dielectric pattern and the second lower contact dielectric pattern.
Examiner respectfully disagrees with applicant’s assertion, and that Kim et al FIG. 21 discloses applicant’s argued amended claim limitation.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Shin et al (U.S. 7,728,375) discloses a semiconductor memory device.
Cho et al (U.S. 2013/0161832) discloses semiconductor device with buried bit line.
Lee et al (U.S. 2015/0061134) discloses semiconductor devices including air gap spacers.
Cheng et al (U.S. 2020/0020524) discloses semiconductor structure.
Fukushima (U.S. 2012/0193696) discloses a semiconductor device.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/S.E.B./Examiner, Art Unit 2815
/JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
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