Prosecution Insights
Last updated: April 19, 2026
Application No. 17/861,834

MEMS MODULE AND METHOD OF MANUFACTURING MEMS MODULE

Non-Final OA §103
Filed
Jul 11, 2022
Examiner
SANDVIK, BENJAMIN P
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Rohm Co. Ltd.
OA Round
3 (Non-Final)
76%
Grant Probability
Favorable
3-4
OA Rounds
2y 8m
To Grant
82%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allow Rate
874 granted / 1142 resolved
+8.5% vs TC avg
Moderate +6% lift
Without
With
+6.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
25 currently pending
Career history
1167
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
60.5%
+20.5% vs TC avg
§102
25.2%
-14.8% vs TC avg
§112
6.7%
-33.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1142 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/17/2025 has been entered. Response to Arguments Applicant's amendments and arguments filed 12/17/2025 have been fully considered but they are not persuasive. The applicant argues that the Chou reference does not disclose the stress relaxation material being arranged between the printed circuit board and the claimed electronic component. It is noted that Chou discloses that the stress relaxation material 201 extends across the entire bottom surface of the MEMS substrate 200, and is arranged between the entire MEMS substrate and the printed circuit board 100. The combination of the Sakuragi and Hsieh references establishes a MEMS substrate (which is equivalent to the substrate 200 of Chou) that includes both the MEMS element and the claimed electronic component. Hence, the further combination of Sakuragi/Hsieh and Chou will result in the stress relaxation layer being between the electronic component on the substrate (i.e. the electronic component will be on the equivalent substrate 200) and the printed circuit board. The office action has been updated below to address the newly amended limitations. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Sakuragi (U.S. Pub #2018/0346322), in view of Hsieh et al (U.S. Pub #2011/0183456), in view of Chou et al (U.S. Pub #2013/0119493). With respect to claim 1, Sakuragi teaches a MEMS module comprising: a MEMS element (Fig. 5, 3) provided with a substrate (Fig. 5, 30) in which a hollow portion (Fig. 5, 340) is formed, and including a movable portion (Fig. 5, 360 and Paragraph 76), which is a part of the substrate, around the hollow portion, the movable portion having a thickness whose shape is changeable by an air pressure difference between an air pressure inside the hollow portion and an air pressure outside the substrate; and an electronic component, to which an output signal of the MEMS element is inputted (Paragraph 71), a printed circuit board (Fig. 5, 1). but does not teach an electronic component formed on the substrate, wherein the electronic component and the MEMS element are spaced apart from each other in a direction perpendicular to a thickness direction of the movable portion. Hsieh teaches an electronic component formed on a MEMS substrate, wherein the electronic component (Fig. 2J, 206; Fig. 17D, 702, etc.) and the MEMS element are spaced apart from each other in a direction perpendicular to a thickness direction of the movable portion. It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to provide an electronic component on the substrate of Sakuragi, such that the component is spaced apart from the MEMS element, as taught by Hsieh in order to achieve the predictable result of integrating a CMOS signal sensing processing circuit on the MEMS wafer (Paragraph 6, 8, and 70). Sakuragi and Hsieh does not teach a stress relaxation material arranged between the printed circuit board and the MEMS element and between the printed circuit board and the electronic component. Chou teaches a MEMS element substrate (Fig. 1D, 200), a PCB (Fig. 1D, 100 and Paragraph 9), and a stress relaxation material (Fig. 1D, 201 and Paragraph 11-12) arranged between the printed circuit board and the MEMS element substrate. It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to provide a stress relaxation material between the MEMS element and electronic of the MEMS substrate of Sakuragi and Hsieh and a printed circuit board as taught by Chou in order to achieve the predictable result of attaching/bonding the MEMS element substrate while also buffering the stress in the structure (Paragraph 11-12). With respect to claim 2, Sakuragi does not teach that the substrate includes a groove, which extends from a main surface of the substrate in a thickness direction of the substrate, between the MEMS element and the electronic component. Hsieh teaches that the substrate includes a groove (Fig. 2J, 230; Fig. 17D, 710), which extends from a main surface of the substrate in a thickness direction of the substrate, between the MEMS element and the electronic component. It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to provide a groove between the MEMS element and the electronic component as taught by Hsieh in order to provide circuit isolation (Paragraph 46 and 84). With respect to claim 3, Hsieh teaches a first wiring (Fig. 2J, 235 and/or 240; Paragraph 46) having a region located on an outer edge side of the substrate from an end of the groove, in a direction in which the electronic component and the MEMS element (Fig. 2J, 204) are spaced apart from each other and a direction which is perpendicular to the thickness direction of the movable portion, wherein the MEMS element and the electronic component are electrically connected to the first wiring. It is also noted that Sakuragi teaches that the MEMS element is electrically connected to the electronic component (Fig. 6). It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to provide a first wiring connecting the MEMS elements and electronic component of Sakuragi as taught by Hsieh in order to achieve the predictable result of integrating a CMOS signal sensing processing circuit on the MEMS wafer (Paragraph 6, 8, and 70). With respect to claim 7, Sakuragi teaches that the substrate is made of silicon (Paragraph 76). Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Sakuragi, Hsieh, and Chou, in view of Sakuragi et al (U.S. Pub #2013/0062713). With respect to claim 4, Sakuragi2018 does not teach a protective film including an opening on the substrate, wherein the protective film covers at least a part of the electronic component, and wherein the opening is located above the movable portion when viewed in the thickness direction of the movable portion. Sakuragi2013 teaches a protective film (Fig. 3a, 25 and Paragraph 347) including an opening on the substrate, wherein the protective film covers at least a part of the electronic component, and wherein the opening is located above the movable portion when viewed in the thickness direction of the movable portion. It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to provide a protective film on the substrate of Sakuragi2018 as taught by Sakuragi2013 in order to passivate the substrate structures (Paragraph 347). Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Sakuragi, Hsieh, and Chou, in view of Emmerich et al (U.S. Pub #2005/0103105). With respect to claim 5, Sakuragi does not teach a stress relaxation material having a thickness of the stress relaxation material is 35 to 80 um. Emmerich teaches a stress relaxation material arranged between the substrate and the MEMS element, wherein a thickness of the stress relaxation material is 35 to 80 um (Fig. 1, 11 and Paragraph 18). It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to provide a layer having a thickness of 35-80 um between the MEMS element and printed circuit board of Sakuragi and Chou as taught by Emmerich in order to achieve good stress decoupling between the MEMS and the underlying substrate (Paragraph 18). With respect to claim 6, Sakuragi teaches a second wiring configured to electrically connect the printed circuit board (Fig. 5, 11) and the electronic component (Fig. 5, 21), wherein the second wiring is electrically connected to the electronic component, on a side of the electronic component that is opposite to a side on which the MEMS element is located. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN P SANDVIK whose telephone number is (571)272-8446. The examiner can normally be reached M-F: 10-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BENJAMIN P SANDVIK/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Jul 11, 2022
Application Filed
Jun 11, 2025
Non-Final Rejection — §103
Sep 12, 2025
Response Filed
Sep 19, 2025
Final Rejection — §103
Dec 17, 2025
Request for Continued Examination
Jan 08, 2026
Response after Non-Final Action
Jan 10, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
76%
Grant Probability
82%
With Interview (+6.0%)
2y 8m
Median Time to Grant
High
PTA Risk
Based on 1142 resolved cases by this examiner. Grant probability derived from career allow rate.

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