Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending. Claims 1-20 have been examined and rejected.
Response to Arguments
The 35 USC 112(b) rejections of claims 4, 12, and 18 have been withdrawn in light of amendments to the claims.
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection relies on a new additional reference in addition to previously used references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 9-12, and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kasuya (US 6077304) in view of Dubash (US 11281584).
As per claim 1, Kasuya teaches a method comprising:
preparing, in response to a programming interface call by a testbench, a schedule of states of a signal at two or more intervals in a circuit simulation by a simulator, respectively, wherein the programming interface call specifies a sequence of the states and indicates durations of the states during the simulation (Fig. 1, col. 4 lines 39-44, col. 5 lines 10-17, lines 25-33; Kasuya teaches a testbench sending procedure calls for defining input signal waveforms to a simulator, via an API, for the simulator to prepare starting and restarting of signal waveforms; the API corresponds to a programming interface, and starting and restarting a simulation using signal waveforms read onto preparing a schedule of states of a signal at two or more intervals in a circuit simulation by a simulator as recited);
setting the signal to a first state of the sequence by the simulator during the simulation according to the schedule (col. 1 lines 25-28, col. 4 lines 39-44; Kasuya teaches a simulation engine in the simulator determines input signal waveforms received via API; this teaching means the input signal waveforms of specified inputs are set to a sequence of states, comprising at least a first state, forming waveforms); and
setting the signal to a second state of the sequence by the simulator during the simulation according to the schedule (col. 1 lines 25-28, col. 4 lines 39-44; Kasuya teaches a simulation engine in the simulator determines input signal waveforms received via API; this teaching means the input signal waveforms of specified inputs are set to a sequence of states forming waveforms, comprising at least a first state and a second states, forming waveforms).
Kasuya does not teach:
wherein the schedule is prepared based on the programming interface call without further programming interface calls during the simulation.
However, Dubash teaches:
the schedule is prepared based on the programming interface call without further programming interface calls during the simulation (col. 9 line 59 – col. 10 line 9; Dubash teaches a single API call to configure data value to perform simulation operations).
Kasuya and Dubash are analogous art because they are in the same field of performing simulation of a circuit design. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kasuya and Dubash. One of ordinary skill in the art would have been motivated to make such a combination because Dubash’s teachings would have provided the benefit of freeing the main system processor from having to make API calls to send data to peripheral components in latency-sensitive applications such as real-time simulation environments (Dubash, col. 15 lines 3-14).
As per claim 2, Kasuya and Dubash in combination teach the method of claim 1, Kasuya further teaches wherein the signal is a periodic signal and further comprising repeating the setting of the signal to the first state and setting of the signal to the second state (col. 6 lines 34-37; Kasuya teaches the signal is a clock, which is a periodic signal comprising repeating the setting of the signal as recited).
As per claim 3, Kasuya and Dubash in combination teach the method of claim 2, Kasuya further teaches wherein:
the programming interface call specifies a repeat-cycle time that indicates a duration between cycles of setting the signal to the first state and setting of the signal to the second state (col. 4 lines 12-24, col. 6 lines 34-37; Kasuya teaches a clock signal, which is a periodic signal with alternate logical values of 0 and 1 in a cycle, and each logical value is define at each point in time; these teachings reads onto this limitation of indication of a duration between cycles as recites); and
preparing the schedule specifies the duration between the cycles of setting the signal to the second state in one cycle and setting the signal to the first state in a next cycle (col. 4 lines 12-24, col. 6 lines 34-37; Kasuya teaches a clock signal, which is a periodic signal with alternate logical values of 0 and 1 in a cycle, and each logical value is define at each point in time, so the teaching inhere.
As per claim 4, Kasuya and Dubash in combination teach the method of claim 1, Kasuya further teaches wherein:
the programming interface call specifies a cancel time that indicates a simulation time to stop the repeating of the setting of the signal to the first state and setting of the signal to the second state (col. 10 lines 16-21; Kasuya teaches specifying simulation end to terminate the circuit simulation; this teaching means the API call specifies a cancel time indicating time to stop the repeating as recited in this limitation); and
preparing the schedule specifies the simulation time to stop the repeating of the setting of the signal to the first state and setting of the signal to the second state (col. 10 lines 16-21; Kasuya teaches specifying simulation end to terminate the circuit simulation; this teaching reads onto this limitation).
As per claim 9, Kasuya teaches a method comprising:
preparing, in response to a programming interface call by a testbench, a schedule of states of a set of signals at two or more intervals in a circuit simulation by a simulator, respectively, wherein the programming interface call specifies a sequence of values and indicates durations of the values during the simulation, and each value specifies respective states of the signals of the set of signals (Fig. 1, col. 4 lines 39-44, col. 5 lines 10-17, lines 25-33; Kasuya teaches a testbench sending procedure calls for defining input signal waveforms to a simulator, via an API, for the simulator to prepare starting and restarting of signal waveforms; the API corresponds to a programming interface, and starting and restarting a simulation using signal waveforms, corresponding to a sequence, read onto preparing a schedule of states of signals at two or more intervals in a circuit simulation by a simulator as recited);
setting the signals of the set of signals to respective first states indicated by a first value of the sequence by the simulator during the simulation according to the schedule (col. 1 lines 25-28, col. 4 lines 39-44; Kasuya teaches a simulation engine in the simulator determines input signal waveforms received via API; this teaching means the input signals’ waveforms of specified inputs are set to a sequence of states, comprising at least a first state, forming waveforms); and
setting signals of the set of signals to respective second states indicated by a second value of the sequence by the simulator during the simulation according to the schedule (col. 1 lines 25-28, col. 4 lines 39-44; Kasuya teaches a simulation engine in the simulator determines input signal waveforms received via API; this teaching means the input signal waveforms of specified inputs are set to a sequence of states forming waveforms, comprising at least a first state and a second states, forming waveforms).
Kasuya does not teach:
wherein the schedule is prepared based on the programming interface call without further programming interface calls during the simulation.
However, Dubash teaches:
the schedule is prepared based on the programming interface call without further programming interface calls during the simulation (col. 9 line 59 – col. 10 line 2; Dubash teaches a single API call to configure data value to perform simulation operations).
Kasuya and Dubash are analogous art because they are in the same field of performing simulation of a circuit design. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kasuya and Dubash. One of ordinary skill in the art would have been motivated to make such a combination because Dubash’s teachings would have provided the benefit of freeing the main system processor from having to make API calls to send data to peripheral components in latency-sensitive applications such as real-time simulation environments (Dubash, col. 15 lines 3-14).
As per claim 10, these limitations have already been discussed in claim 2. They are, hence, rejected for the same reasons.
As per claim 11, these limitations have already been discussed in claim 3. They are, hence, rejected for the same reasons.
As per claim 12, these limitations have already been discussed in claim 4. They are, hence, rejected for the same reasons.
As per claim 15, Kasuya teaches a system, comprising:
one or more computer processors configured to execute program code (col. 3 line 66 – col. 4 line 6); and
a memory arrangement coupled to the one or more computer processors, wherein the memory arrangement is configured with instructions that when executed by the one or more computer processors cause the one or more computer processors to perform operations (col. 3 line 66 – col. 4 line 6) including:
preparing, in response to a programming interface call by a testbench, a schedule of states of a signal at two or more intervals in a circuit simulation by a simulator, respectively, wherein the programming interface call specifies a sequence of the states and indicates durations of the states during the simulation (Fig. 1, col. 4 lines 39-44, col. 5 lines 10-17, lines 25-33; Kasuya teaches a testbench sending procedure calls for defining input signal waveforms to a simulator, via an API, for the simulator to prepare starting and restarting of signal waveforms; the API corresponds to a programming interface, and starting and restarting a simulation using signal waveforms read onto preparing a schedule of states of a signal at two or more intervals in a circuit simulation by a simulator as recited);
setting the signal to a first state of the sequence by the simulator during the simulation according to the schedule (col. 1 lines 25-28, col. 4 lines 39-44; Kasuya teaches a simulation engine in the simulator determines input signal waveforms received via API; this teaching means the input signal waveforms of specified inputs are set to a sequence of states, comprising at least a first state, forming waveforms); and
setting the signal to a second state of the sequence by the simulator during the simulation according to the schedule (col. 1 lines 25-28, col. 4 lines 39-44; Kasuya teaches a simulation engine in the simulator determines input signal waveforms received via API; this teaching means the input signal waveforms of specified inputs are set to a sequence of states forming waveforms, comprising at least a first state and a second states, forming waveforms).
Kasuya does not teach:
wherein the schedule is prepared based on the programming interface call without further programming interface calls during the simulation.
However, Dubash teaches:
the schedule is prepared based on the programming interface call without further programming interface calls during the simulation (col. 9 line 59 – col. 10 line 9; Dubash teaches a single API call to configure data value to perform simulation operations).
Kasuya and Dubash are analogous art because they are in the same field of performing simulation of a circuit design. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kasuya and Dubash. One of ordinary skill in the art would have been motivated to make such a combination because Dubash’s teachings would have provided the benefit of freeing the main system processor from having to make API calls to send data to peripheral components in latency-sensitive applications such as real-time simulation environments (Dubash, col. 15 lines 3-14).
As per claim 16, these limitations have already been discussed in claim 2. They are, hence, rejected for the same reasons.
As per claim 17, these limitations have already been discussed in claim 3. They are, hence, rejected for the same reasons.
As per claim 18, these limitations have already been discussed in claim 4. They are, hence, rejected for the same reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-8, 13-14, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kasuya (US 6077304) in view of Dubash (US 11281584) as applied to claims 1, 9, and 15 above, and further in view of Yang et al. (US 2013/0097568).
As per claim 5, Kasuya and Dubash in combination teach the method of claim 1,
Kasuya and Dubash do not teach:
the durations of the states of the signal are specified in the programming interface call by offsets associated with the states in the sequence, respectively; and
preparing the schedule determines timing of the first state of the signal based on a current simulation time and the associated offsets, wherein the current simulation time is a simulation time at which the programming interface call made.
However, Yang teaches:
the durations of the states of the signal are specified in the programming interface call by offsets associated with the states in the sequence, respectively (¶ 0022; Yang teaches that states and durations comprising duty cycle, stop & start time of one clock are specified with offset relative to another clock signal in sequence); and
preparing the schedule determines timing of the first state of the signal based on a current simulation time and the associated offsets, wherein the current simulation time is a simulation time at which the programming interface call made (¶ 0022; Yang teaches that states and durations comprising duty cycle, stop & start time of one clock are specified with offset relative to another clock signal in sequence by API calls for simulation; this teaching indicates the preparing the schedule as recited in this limitation).
Kasuya, Dubash, and Yang are analogous art because they are in the same field of performing simulation of a circuit design. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kasuya, Dubash, and Yang. One of ordinary skill in the art would have been motivated to make such a combination because Yang’s teachings would have generated and controlled simulated clock signals in DL environment (Yang, ¶ 0002).
As per claim 6, Kasuya, Dubash, and Yang in combination teach the method of claim 5, Kasuya further teaches comprising:
performing the circuit simulation in response to initial input signals from the testbench (col. 9 lines 43-46; Kasuya teaches starting simulation of a circuit design using input signals);
Kasuya and Dubash do not teach:
wherein preparing the schedule is in response to the programming interface call made after the simulation on the initial input signals, and the current simulation time is a simulation time at which the programming interface call made.
However, Yang teaches:
preparing the schedule is in response to the programming interface call made after the simulation on the initial input signals, and the current simulation time is a simulation time at which the programming interface call made (¶ 0022; Yang teaches that states and durations comprising duty cycle, stop & start time of one clock are specified with offset relative to another clock signal; the term “relative to” indicates that a new clock’s timing is specified with respect to an existing clock’s time, and this teaching means the current simulation time for preparing the schedule for the new clock in response to the programming interface call made after the simulation is a simulation time at which the programming interface call made).
As per claim 7, Kasuya and Dubash in combination teach the method of claim 1,
Kasuya and Dubash do not teach:
preparing the schedule determines timing for setting the signal to each state other than the first state in the sequence, based on the associated offset and a simulation time at which the signal is to be set to a preceding state in the sequence.
However, Yang teaches:
preparing the schedule determines timing for setting the signal to each state other than the first state in the sequence, based on the associated offset and a simulation time at which the signal is to be set to a preceding state in the sequence (¶ 0022; Yang teaches that states and durations comprising duty cycle, stop & start time of one clock are specified with offset relative to another clock signal; the term “relative to” indicates that a new clock’s timing is specified with respect to an existing clock’s time, and this teaching means the preparing the schedule for the new clock in response to the programming interface call made after the simulation is a based on time at which the programming interface call made).
Kasuya, Dubash, and Yang are analogous art because they are in the same field of performing simulation of a circuit design. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kasuya, Dubash, and Yang. One of ordinary skill in the art would have been motivated to make such a combination because Yang’s teachings would have generated and controlled simulated clock signals in DL environment (Yang, ¶ 0002).
As per claim 8, Kasuya, Dubash, and Yang in combination teach the method of claim 7,
Yang further teaches:
the programming interface call specifies a repeat-cycle time (¶ 0022; Yang teaches a periodic clock signal with start and stop time, corresponding to repeat -cycle time); and
preparing the schedule determines timing between setting the signal to a last state in the sequence and setting the signal to the first state in the sequence based on a simulation time of setting the signal to the last state in the sequence, offset by the repeat-cycle time (¶ 0022; Yang teaches a periodic clock signal with start and stop time and a number of cycles to run; this teaching indicates preparing the schedule determines timing between setting the signal as recited in this limitation).
As per claim 13, these limitations have already been discussed in claim 5. They are, hence, rejected for the same reasons.
As per claim 14, these limitations have already been discussed in claim 6. They are, hence, rejected for the same reasons.
As per claim 19, these limitations have already been discussed in claim 5. They are, hence, rejected for the same reasons.
As per claim 20, these limitations have already been discussed in claim 6. They are, hence, rejected for the same reasons.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Cuong Van Luu whose telephone number is 571-272-8572. The examiner can normally be reached on Monday - Friday from 8:30 to 5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rehana Perveen, can be reached at telephone number (571)272-3676, the fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CUONG V LUU/Examiner, Art Unit 2189
/REHANA PERVEEN/Supervisory Patent Examiner, Art Unit 2189
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