DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10, 16-17 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takaya et al. (US 20030030994 A1, “Takaya”) in view of Hsu et al. (US 20230066370 A1, “Hsu”).
Regarding claim 1, Takaya discloses (Fig. 1 - 2, 11 & 12) a package structure, comprising: a first circuit (13d); a second circuit (11) located above the first circuit; a redistribution structure located above the first circuit and comprising a first conductive pad (13b) and a second conductive pad; a dielectric layer (10b) located above the redistribution structure, wherein the dielectric layer is made of a material including silicon nitride or titanium oxide; a first conductive portion electrically connected to the first conductive pad; a second conductive portion (13a) electrically connected to the second conductive pad (para [0182]), wherein the first conductive portion at least partially overlaps the second conductive portion; and a third conductive portion located at the same layer as the second conductive portion, wherein the second conductive portion and the third conductive portion are located above the dielectric layer, wherein the third conductive portion does not overlap any conductive portion located at the same layer as the first conductive portion, and a chip disposed on the second circuit and electrically connected with the redistribution structure. (see annotated figure below).
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Takaya is silent on wherein the dielectric layer is made of a material including silicon nitride or titanium oxide, and a chip disposed on the second circuit and electrically connected with the redistribution structure.
However, Hsu discloses (Fig. 1B) wherein the dielectric layer (122) is made of a material including silicon nitride or titanium oxide (para [0011]), and a chip (130, 140) disposed on the second circuit and electrically connected with the redistribution structure (See Fig. 1B and para [0012]).
Takaya and Hsu are both considered to be analogous to the claimed invention because they are in the same field of package structure. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Takaya to incorporate the teachings of Hsu and provide wherein the dielectric layer (122) is made of a material including silicon nitride or titanium oxide (para [0011]), and a chip (130, 140) disposed on the second circuit and electrically connected with the redistribution structure (See Fig. 1B and para [0012]). Doing so would can provide high-bandwidth memory capability and reduce system latency and power consumption (para [0012] and [0034]).
Regarding claim 2, Takaya in view of Hsu discloses the package structure of claim 1, wherein the dielectric layer (10b) is located between the first conductive portion and the second conductive portion, wherein the first conductive portion, the dielectric layer and the second conductive portion form a capacitor (See para [0195] & [0196] and Fig. 11).
Regarding claim 3, Takaya in view of Hsu discloses the package structure of claim 2, wherein an area of a surface of the second conductive portion facing the dielectric layer is different from an area of a surface of the third conductive portion facing the dielectric layer (See annotated figure below).
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Regarding claim 4, Takaya in view of Hsu discloses the package structure of claim 1, further comprising: a conductive pillar located in the dielectric layer and electrically connected to the first conductive portion and the second conductive portion, wherein the dielectric layer (10b) is located between the first conductive portion (13a) and the second conductive portion (13b)
In the embodiment of Fig. 2, Takaya fails to disclose a conductive pillar located in the dielectric layer and electrically connected to the first conductive portion and the second conductive portion.
However, in another embodiment, Takaya discloses (Fig. 6) a conductive pillar (14) located in the dielectric layer (10) and electrically connected to the first conductive portion (13) and the second conductive portion (13).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified an embodiment of Takaya in view of Hsu to incorporate the teachings of another embodiment of Takaya and provide a conductive pillar (14) located in the dielectric layer (10) and electrically connected to the first conductive portion (13) and the second conductive portion (13). Doing so would provide electrical connection to the conductive portions (para [0182]).
Regarding claim 5, Takaya in view of Hsu and another embodiment of Takaya discloses the package structure of claim 4, further comprising: a first resistance line (conductor vias inherently have resistance) electrically connected between the second conductive portion and the second conductive pad (See annotated figure below).
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Regarding claim 6, Takaya in view of Hsu and another embodiment of Takaya discloses the package structure of claim 5, further comprising: a second resistance line (electrical conductors (13) inherently have resistance) electrically connected to the third conductive portion, wherein the second resistance line is located at the same layer as the third conductive portion, and the second resistance line does not overlap any conductive portion located at the same layer as the first conductive portion (See annotated figure above).
Regarding claim 7, Takaya in view of Hsu and another embodiment of Takaya discloses the package structure of claim 6, wherein a length of the first resistance line is different from a length of the second resistance line (See annotated figure above).
Regarding claim 8, Takaya in view of Hsu and another embodiment of Takaya discloses the package structure of claim 4, further comprising: a first inductive coil electrically connected between the second conductive portion and the second conductive pad (See para [0182] and Figs. 1 & 5).
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Regarding claim 9, Takaya in view of Hsu and another embodiment of Takaya discloses the package structure of claim 8, further comprising: a second inductive coil electrically connected to the third conductive portion, wherein the second inductive coil is located at the same layer as the third conductive portion, and the second inductive coil does not overlap any conductive portion located at the same layer as the first conductive portion (See annotated figure above).
Regarding claim 10, Takaya in view of Hsu and another embodiment of Takaya discloses the package structure of claim 9, wherein the number of turns of the first inductive coil is different from the number of turns of the second inductive coil (See annotated figure above).
Regarding claim 16, Takaya in view of Hsu discloses the package structure of claim 1, further comprising a first patterned material layer, wherein the first circuit (13d) is located above the first patterned material layer (See annotated figure below).
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Regarding claim 17, Takaya in view of Hsu discloses the package structure of claim 16, further comprising a second patterned material layer, a third patterned material layer, a fourth patterned material layer and a fifth patterned material layer, wherein the second patterned material layer, the third patterned material layer, and the fourth patterned material layer are located between the dielectric layer (10b) and the first patterned material layer (See annotated figure above).
Regarding claim 20, Takaya in view of Hsu discloses the package structure of claim 1, wherein Takaya further discloses the redistribution structure is located between the dielectric layer (10b) and the first circuit (13d), wherein the dielectric layer does not overlap the second circuit (See Fig. 2).
Allowable Subject Matter
Claim 18 and 19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIDI MOHAMED MAIGA whose telephone number is (703)756-1870. The examiner can normally be reached Monday - Friday 8 am 5 pm.
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/SIDI M MAIGA/
Examiner, Art Unit 2847
/STANLEY TSO/Primary Examiner, Art Unit 2847