Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant argues that the rejections of record are insufficiently clear. In response, it is noted that Claim 1 of Hosaka was cited for teaching the limitations of instant claim 1. The cited claim was explained at length in the specification and drawing of Hosaka. However, to better articulate the rejection, more precise citations for the same grounds of rejection are provided below.
Applicant argues that Hosaka fails to teach the structure of claim 41. This is not persuasive. Figs. 40-41 of Hosaka, and the specification describing said Figures, discloses each and every limitation.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 9-13, and 18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hosaka et al (US 20190198306 A1)
In Re to claim 1, Hosaka teaches a device for controlling trapped ions, the device comprising:
a first substrate comprising a semiconductor and/or dielectric material; (first main substrate, claim 1)
a first metal structure disposed at a main side of the first substrate; (first face of the first main substrate, claim 1)
a second substrate comprising a semiconductor and/or dielectric material; a second metal structure disposed at a main side of the second substrate opposite the main side of the first substrate;
a spacer disposed between and bonded to the first substrate and the second substrate, the spacer comprising an electrical interconnect which electrically connects the first metal structure to the second metal structure,
wherein a bond between the spacer and the first substrate or the spacer and the second substrate is a bond formed by waferbonding (note that waferbonding is a product by process limitation, see para 362-363); and
at least one ion trap configured to trap ions in a space between the first substrate and the second substrate (See paras 362-363 and Figs 40-41 of Hosaka as shown and mapped below), the first metal structure and the second metal structure comprising electrodes of the ion trap. See paras 362-363 and Figs 40-41 of Hosaka as shown and mapped below.
In Re to claim 2, Hosaka teaches a bond is a glass bond or a eutectic bond or an anodic bond or a thermocompression bond or an adhesive bond or a solid liquid interdiffusion bond. (a first lower substrate adhered to the second face of the first main substrate, claim 1)
In Re to claim 9, Hosaka teaches a electrical interconnect comprises a plurality of vertical holes with metallized inner walls. (Plurality of cavities, claim 1)
In Re to claim 10, Hosaka teaches a spacer comprises at least one spacer member provided with metallized side walls facing the ion trap. (An ion generation cavity in which the charged particles are generated or an extraction and acceleration electrode cavity, claim 2)
In Re to claim 11, Hosaka teaches a spacer comprises at least one spacer member configured as an inner partition wall of the device, wherein the spacer member is configured to act as an optical shield between a first ion trap and a second ion trap of the device. (at least one of the cavities penetrating from the first face of the main substrate to the second face of the main substrate is an ion detection cavity, and a secondary electron multiplier is disposed in the ion detection cavity, claim 8)
In Re to claim 12, Hosaka teaches a spacer is a glass spacer. (a first lower substrate adhered to the second face of the first main substrate, claim 1)
In Re to claim 13, Hosaka teaches a metallized walls of the spacer are of Au, Pt, Pd, Nb, Al, or Cu. (first main substrate, claim 2)
In Re to claim 18, Hosaka teaches the device of claim 1 wherein the electrical interconnect is arranged within the spacer. See annotated Fig. 41 below.
PNG
media_image1.png
799
876
media_image1.png
Greyscale
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 14, 15 ,and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over prior art Hosaka in view of Enquist et al (CN 108369913 A).
In Re. to claims 14, 15, and 17 Hosaka teaches providing a first wafer comprising a semiconductor and/or dielectric material;
forming a pattern of first metal structures at a main side of the first wafer;
providing a second wafer comprising a semiconductor and/or dielectric material;
forming a pattern of second metal structures at a main side of the second wafer;
providing a spacer wafer comprising a dielectric material;
forming a pattern of electrical interconnects in the spacer wafer, wherein an electrical interconnect is configured to electrically connect first metal structures to second metal structures;
structuring the spacer wafer to form a structured spacer wafer including a pattern of spacer members, wherein at least some of the spacer members comprise an electrical interconnect;
singulating the devices for controlling trapped ions from the bonded-together first wafer and spacer wafer or second wafer and spacer wafer. The above claimed providing, forming, and structuring is evident by the structure shown in annotated Fig. 41 below
However, Hosaka fails to teach a method for manufacturing devices for trapped ions, the same method that is carried out by bonding. See figs 40/41.
However, Enquist teaches a semiconductor assembly which includes substrates, metal contact areas on a wafer which can be made of glass, and a second wafer. Detailed description, first three paragraphs.
It would have been obvious to one of ordinary skill in the art to modify Hosaka with the semiconductor assembly introduced by Enquist. The ability to manufacture devices for control of trapped ions in important within the field of semiconductors. Enquist’s method for conductive contact structures are ideal to be used in a wafer to electrically connect the two wafers together for bonding. Enquist introduces this idea with contact structures and non-metallic bonding areas, the wafers, which can be made out of glass or other non-metallic substances.
In Re to claim 19, Hosaka teaches the method of claim 14 wherein the electrical interconnect is arranged within the spacer. See annotated Fig. 41 above.
Allowable Subject Matter
Claims 3-8, 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
In regard to applicant’s argument that the claimed elements, particularly independent claims 1/14, are not anticipated by Hosaka reference, is not persuasive. As noted in the rejection above, Hosaka discloses all the claimed elements, and they are articulated in the rejection. For instance, as shown in figs. 40/41, Hosaka reference teaches the first substrate comprising a semiconductor and/or dielectric material and the first metal structure, which is disposed at a main side of the first substrate, as presently claimed. In addition, Hosaka teaches second substrate, second metal structure, spacer, bond, etc, as shown in figure 40/41. Moreover, figs 40/41 shows multi-layers with different metals/material in the etching process.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Robert Kim whose telephone number is (571)272-2293. The examiner can normally be reached M-F 7-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Allana Bidder can be reached on 571-272-5560. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ROBERT H KIM/Supervisory Patent Examiner, Art Unit 2881
Prosecution Insights