DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/28/2025 has been entered.
Response to Amendment
The amendments filed 7/28/2025 have been entered and considered. The amendments to claim 1, 2, 7, and 17 are acknowledged.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 4, and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Ting et al. US 20190148329 A1 (hereinafter referred to as Ting), in view of Pan et al. US 20160056125 A1 (hereinafter referred to as Pan), in view of Karikalan et al. US 20150235992 A1 (hereinafter referred to as Karikalan).
Regarding claim 1, Ting teaches
A semiconductor package (“package 60” para. 0051 FIG. 24 rotated 180°) comprising:
a package substrate (structure comprising “RDLs 68, 76, and 78” para. 0040-0043);
a first interposer (“interconnect die 38A” para. 0030) on the package substrate;
a second interposer (“interconnect die 38B” para. 0030) on the package substrate;
a lower molding layer on the package substrate and surrounding the first interposer and the second interposer (“encapsulating material 44” encapsulates “interconnect dies 38”, para. 0025 FIG. 24);
a first semiconductor chip (“package component 50B” para. 0030) on the lower molding layer;
a second semiconductor chip on the lower molding layer and at an outer side of the first semiconductor chip (“package component 50A” para. 0050);
interposer connection terminals configured to connect the first and second semiconductor chips to the first interposer (the bonding between “bond pads 52” of “package components 50” and “bond pads 118” of “interconnect die 38A” may include solder, para. 0029, as the interposer connection terminals), the interposer connection terminals including a first interposer connection terminal between the first semiconductor chip and the first interposer (solder between “bond pads 52” of “package component 50B” and “bond pads 118”), a second interposer connection terminal between the second semiconductor chip and the first interposer (solder between “bond pads 52” of “package component 50A” and “bond pads 118”), and a third interposer connection terminal between the first semiconductor chip and the second interposer (solder between “bond pads 52” of “package component 50A” and “bond pads 118” of “interconnect die 38B”); and
an upper molding layer on the lower molding layer, and surrounding the first and second semiconductor chips (“underfill 54” is on “encapsulating material 44” and surrounds “package component 50B” and parts of “package component 50A”, para. 0049).
a bottom surface of the first semiconductor chip, a bottom surface of the second semiconductor chip, and a top surface of the lower molding layer are coplanar with each other (bottoms of “package components 50A and 50B” contact a top surface of “encapsulant 44”).
a first conductive pillar (“through-vias 48” para. 0047) connected to the first semiconductor chip;
a second conductive pillar at an outer side of the first conductive pillar, and between the first semiconductor chip and the first interposer connection terminal ("bond pads 52" protrude out from the surface of "package component 50B" as seen in FIG. 21 and 24 and can be considered pillars. "Bond pads 52" are between "package component 50B" and the solder material used for bonding described in para. 0029); and
a third conductive pillar at an outer side of the second conductive pillar, and between the second semiconductor chip and the second interposer connection terminal ("bond pads 52" protrude out from the surface of "package component 50A" as seen in FIG. 21 and 24 and can be considered pillars. "Bond pads 52" are between "package component 50A" and the solder material used for bonding).
However, Ting fails to teach a chip connection terminal between the first semiconductor chip and the package substrate and between the first interposer and the second interposer, and surrounded by the lower molding layer, the chip connection terminal configured to connect the first semiconductor chip to the package substrate
wherein a vertical length of the chip connection terminal in a direction perpendicular to an upper surface of the package substrate is greater than a vertical length of the interposer connection terminals, and wherein a vertical length of the first conductive pillar in a direction perpendicular to an upper surface of the package substrate is greater than a vertical length of each of the second conductive pillar and the third conductive pillar.
Nevertheless, Pan teaches
a chip connection terminal (“first conductive bumps 510” with “first contact pads 104” para. 0028 and 0034 FIG. 6) between the first semiconductor chip (“second semiconductor device 500”, comprising “third substrate 502” and “second metallization layers 504”, para. 0028) and the package substrate (“first substrate 102” para. 0013), and surrounded by the lower molding layer (“underfill 602” para. 0047), the chip connection terminal configured to connect the first semiconductor chip to the package substrate (“second semiconductor device 500” and “first substrate 102” are bonded through “first conductive pillars 506”, “first conductive bumps 510”, and “first contact pads 104”, para. 0045)
wherein a vertical length of the chip connection terminal in a direction perpendicular to an upper surface of the package substrate is greater than a vertical length of the interposer connection terminals (“the first conductive pillars 506” have a “first thickness T.sub.1” between about 60 μm and 100 μm” and “thickness t.sub.3” between “second semiconductor device 500” and “first substrate 102” is 80 μm and 120 μm, such that the “first conductive bumps 510” with “first contact pads 104” have a height of 20 µm to 60µm, para. 0031 and 0048. Meanwhile, “second conductive pillars 508” have “a second thickness T.sub.2 of between about 20 μm and 40 μm” and “thickness t.sub.4” between “third semiconductor device 514” and “first semiconductor device 110” is between about 20 μm and 50 μm, so the “third conductive bumps 524” and “third contact pads 116” have a height of 0 µm to 30µm, para. 0033 and 0048).
and wherein a vertical length of the first conductive pillar in a direction perpendicular to an upper surface of the package substrate is greater than a vertical length of each of the second conductive pillar and the third conductive pillar (“the first conductive pillars 506 may be formed to have a first thickness T.sub.1 of between about 60 μm and 100 μm” while “second conductive pillars 508” have “a second thickness T.sub.2 of between about 20 μm and 40 μm”, para. 0032-0033).
Ting and Pan teach packages comprising semiconductor chips and bridge die connected to a substrate. While the substrate in Ting is directly formed on "through-vias 48", "first substrate 102" is formed separately and then “second semiconductor device 500" is bonded using “first conductive bump 510”. In this manner, different groups of bonded “second semiconductor die 500" and "first semiconductor die 110" can be applied to different “first substrates 102” that have already been fabricated instead of forming a specific “first substrate 102” for each set of die, depending on the intended applications. The separation between “substrate 102” and “second semiconductor device 500” is greater than the separation between “first semiconductor device 110” and “second semiconductor device 500”. This is why the vertical length of “the first conductive pillars 506” and “first conductive bumps 510” with “first contact pads 104” is greater than the vertical length of “third conductive pillars 520” and “third conductive bumps 524” with “third contact pads 116”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “first conductive bumps 510” can be used to connect separately made semiconductor devices to “first substrate 102”. Furthermore, the length of the interconnection structure between “first substrate 102” and “second semiconductor device 500” is greater than the length interconnection structure between “first semiconductor device 110” and “second semiconductor device 500” because of the separation is greater.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught in Ting with the chip connection terminal and vertical lengths of the chip connection terminal, interposer connection terminal, and the first to third conductive pillars in Pan. The chip connection terminals allow the first semiconductor chip and the package substrate to be formed individually and then bonded. The vertical lengths of the chip connection terminal and the first conductive pillar area greater than the interposer connection terminal and the second and third conductive pillar since the separation between the first semiconductor chip and the package substrate is greater than the separation between the first semiconductor chip and the first interposer and second interposer.
Ting, modified by Pan, further teaches
The chip connection terminal is between the first interposer and the second interposer (the added “first conductive bumps 510” from Pan are between “interconnect die 38A and 38B”),
the first conductive pillar between the first semiconductor chip and the chip connection terminal (“through-vias 48” are between “package component 50B” and the added “first conductive bumps 510”);
However, a first adhesive layer, wherein a bottom surface of the upper molding layer, a bottom surface of the first semiconductor chip, a bottom surface of the second semiconductor chip, a top surface of the lower molding layer, and a top surface of the first adhesive layer are coplanar with each another.
Nevertheless, Karikalan teaches a first adhesive layer (“adhesion layer 338” para. 0027 FIG. 3), wherein a bottom surface of the first semiconductor chip (“active die 310” para. 0027), a bottom surface of the second semiconductor chip (“active die 320” para. 0027), and a top surface of the first adhesive layer are coplanar with each another (“active die 310 and 320” are bonded to “adhesion layer 338” and the bottoms of “active dies 310 and 320” and the top surface of “adhesion layer 338” are coplanar as shown in FIG. 3).
Ting, modified by Pan, and Karikalan teach packages comprising dies bonded to interposers and a substrate. Karikalan uses “adhesion layer 338” to “secure bridge interposer 330 to first portion 311 of first active die 310 and first portion 321 of second active die 320” (para. 0027). In other words, the “adhesion layer 380” provides a more secure physical bond between “bridge interposer 330” and “active die 310 and 320”. The examiner understands that “underfill 54” in Ting may make the package more rigid and protect against deformation but the “adhesion layer 380” in Karikalan ensures the die are connected together. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “adhesion layer 380” can secure the bond between die and the interposer. Replacing the “underfill 54” formed in the gaps between “package components 50” and “interconnection die 30”, such as by depositing the “adhesion layer 380” first and then filling the rest with “underfill 54”, will yield an improved physical connection.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught between Ting and Pan with the adhesive layer taught in Karikalan. An adhesive layer between the semiconductor chips and the interposers forms a more secure bond. The resulting structure will have a top surface of the adhesive layer, bottom surface of first semiconductor chip, and the bottom surface of the second semiconductor chip
As a result of the combination, Ting, modified by Pan and Karikalan, further teaches
wherein a bottom surface of the upper molding layer, a bottom surface of the first semiconductor chip, a bottom surface of the second semiconductor chip, a top surface of the lower molding layer, and a top surface of the first adhesive layer are coplanar with each another (bottoms of “package components 50A and 50B” contact a top surface of “encapsulant 44”. “Package components 50” and “interconnect die 30” now have an “adhesion layer 338” in between as taught in Karikalan where the “adhesion layer 338” has a top surface coplanar with bottom surfaces of “package components 50”. “Underfill 54” fills in the gaps between “package components 50” such that the bottom surface of “underfill 54”, bottom surface of “package components 50A and 50B”, top surface of “encapsulant 44”, and top surface of “adhesion layer 338” are coplanar.).
Regarding claim 2, Ting, modified by Pan and Karikalan, teach the semiconductor package of claim 1 the first adhesive layer being between a first portion of a top surface of the first interposer and a portion of the bottom surface of the first semiconductor chip (“adhesive layer 338” is disposed between a left portion of “package component 50B” and a right portion of “interconnect die 38A”, as taught in FIG. 3 of Karikalan with “active die 310” and “bridge interposer 330”), between a second portion of the top surface of the first interposer and a portion of the bottom surface of the second semiconductor chip (“adhesive layer 338” is disposed between a right portion of “package component 50A” and a left portion of “interconnect die 38A”), and between a third portion of the top surface of the first interposer and the bottom surface of the upper molding layer (since “adhesion layer 338” is now formed first, “underfill 54” between “package components 50A and 50B” has a bottom surface in contact with “adhesion layer 338” overlapping “interconnect die 38A”), and the first adhesive layer surrounding the interposer connection terminals (as taught in para. 0030 of Karikalan, “micro-bumps corresponding to micro-bumps 144” are interconnect elements between “active die 310 and 320” and “bridge interposer 330”. As such “adhesion layer 338” surrounds the solder elements between “bond pads 52” and “bond pads 118” of “interconnect die 38A” in Ting.).
Regarding claim 4,Ting, modified by Pan and Karikalan, teach the semiconductor package of claim 3, wherein the vertical length of the chip connection terminal is about 30 micrometers to about 300 micrometers (“the first conductive pillars 506” have a “first thickness T.sub.1” between about 60 μm and 100 μm” and “thickness t.sub.3” between “second semiconductor device 500” and “first substrate 102” is 80 μm and 120 μm, such that the “first conductive bumps 510” with “first contact pads 104” have a height of 20 µm to 60µm, para. 0031 and 0048.), and the vertical length of the interposer connection terminals is about 10 micrometers to about 100 micrometers and is smaller than the vertical length of the chip connection terminal (“second conductive pillars 508” have “a second thickness T.sub.2 of between about 20 μm and 40 μm” and “thickness t.sub.4” between “third semiconductor device 514” and “first semiconductor device 110” is between about 20 μm and 50 μm, so the “third conductive bumps 524” and “third contact pads 116” have a height of 0 µm to 30µm, para. 0033 and 0048).
Regarding claim 7, Ting, modified by Pan and Karikalan, teach the semiconductor package of claim 1 but fail to teach further comprising a second adhesive layer between a bottom surface of the first interposer and a top surface of the package substrate, and configured to fix the first interposer to the package substrate.
Nevertheless, an alternate embodiment in Ting shown in FIG. 9 shows a “package 60” where “interconnect die 30” are attached to ‘RDL 36” by a “die attach film 42” which is an adhesive (para. 0019). This is used in a process of forming “package 60” where the substrate is formed first, then the “interconnects die 30” and the “package components 50” are bonded. Regardless of the method, the examiner understands that the use of an adhesive “die attach film 42” can secure the “interconnect die 30” to the substrate just how “adhesion layer 338” from Karikalan secures the “active die 310 and 320” to “bridge interposer 330”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “die attach film 42” can securely bond the “interconnect 30A” to the “RDL 68” of the substrate.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught between Ting, Pan, and Karikalan with the second adhesive as taught in an alternate embodiment of Ting. The second adhesive can securely bond the first interposer to the package substrate, improving the device robustness.
Regarding claim 8, Ting, modified by Pan and Karikalan, teach the semiconductor package of claim 1, wherein a top surface of the upper molding layer is coplanar with a top surface of the first semiconductor chip and a top surface of the second semiconductor chip (“underfill 54” is coplanar with top surfaces of the “package components 50” in FIG. 25 para. 0036 and 0049).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Ting et al. US 20190148329 A1 (hereinafter referred to as Ting), in view of by Kim et al. US 20200243422 A1 (hereinafter referred to as Kim), in view of Pan et al. US 20220352075 A1 (hereinafter referred to as Pan), and in view of Karikalan et al. US 20150235992 A1 (hereinafter referred to as Karikalan).
Ting teaches
A semiconductor package (“package 60” para. 0051 FIG. 24 rotated 180°) comprising:
a package substrate (structure comprising “RDLs 68, 76, and 78” para. 0040-0043);
a first interposer (“interconnect die 38A” para. 0030) on the package substrate;
a second interposer (“interconnect die 38B” para. 0030) on the package substrate;
a lower molding layer on the package substrate and surrounding the first interposer and the second interposer a lower molding layer on the package substrate and surrounding the first interposer and the second interposer (“encapsulating material 44” encapsulates “interconnect dies 38”, para. 0025 FIG. 24);
a first semiconductor chip (“package component 50B” para. 0030) on the lower molding layer;
a second semiconductor chip on the lower molding layer and at an outer side of the first semiconductor chip (“package component 50A” para. 0050);
interposer connection terminals configured to connect the first semiconductor chip and the semiconductor stack structure to the first interposer (the bonding between “bond pads 52” of “package components 50” and “bond pads 118” of “interconnect die 38A” may include solder, para. 0029, as the interposer connection terminals), the interposer connection terminals including a first interposer connection terminal between the first semiconductor chip and the first interposer (solder between “bond pads 52” of “package component 50B” and “bond pads 118”), a second interposer connection terminal between the second semiconductor chip and the first interposer (solder between “bond pads 52” of “package component 50A” and “bond pads 118”), and a third interposer connection terminal between the first semiconductor chip and the second interposer (solder between “bond pads 52” of “package component 50A” and “bond pads 118” of “interconnect die 38B”);
conductive pillars including a first conductive pillar (“through-vias 48”, para. 0048 FIG. 24) between the first semiconductor chip and the package substrate, and other conductive pillars between the first semiconductor chip and the first interposer connection terminal (“bond pads 52” protrude out from the surface of “package component 50B” as seen in FIG. 21 and 24 and can be considered pillars. “Bond pads 52” are between “package component 50B” and the solder material used for bonding with “interconnect die 38A” as described in para. 0029), between the second semiconductor chip and the second interposer connection terminal (“Bond pads 52” between “package component 50A” and the solder material used for bonding with “interconnect die 30A”), and between the first semiconductor chip and the third interposer connection terminal (“Bond pads 52” between “package component 50B” and the solder material used for bonding with “interconnect die 30B”);
an upper molding layer on the lower molding layer, and surrounding the first semiconductor chip (“underfill 54” is on “encapsulating material 44” and surrounds “package component 50B” and parts of “package component 50A”, para. 0049); and
a bottom surface of the first semiconductor chip, a bottom surface of the second semiconductor chip, and a top surface of the lower molding layer are coplanar with each other (bottoms of “package components 50A and 50B” contact a top surface of “encapsulant 44”).
However, Ting fails to teach a chip connection terminal between the first semiconductor chip and the package substrate and between the first interposer and the second interposer, and surrounded by the lower molding layer, the chip connection terminal configured to connect the first semiconductor chip to the package substrate;
a semiconductor stack structure on the lower molding layer and at an outer side of the first semiconductor chip, the semiconductor stack structure including a plurality of semiconductor chips;
upper molding layer surrounding the semiconductor stack structure;
interposer connection terminals configured to connect the semiconductor stack structure to the first interposer, second interposer connection terminal between the semiconductor stack structure and the first interposer
the conductive pillars between the first semiconductor chip and the chip connection terminal,
a first adhesive layer between the first interposer and the upper molding layer, between the second interposer and the upper molding layer, and surrounding the interposer connection terminals,
wherein a bottom surface of the upper molding layer, a bottom surface of the first semiconductor chip, a bottom surface of the semiconductor stack structure, a top surface of the lower molding layer, and a top surface of the first adhesive layer are coplanar with each another,
wherein a vertical length of the chip connection terminal in a direction perpendicular to an upper surface of the package substrate is greater than a vertical length of each of the interposer connection terminals, and
wherein a vertical length of the first conductive pillar in the direction perpendicular to the upper surface of the package substrate is greater than vertical lengths of the other conductive pillars.
Nevertheless, Kim teaches
a semiconductor stack structure (“stack 300” para. 0025 FIG. 1) on the lower molding layer (“molding layer 800” para. 0025 FIG. 1) and at an outer side of the first semiconductor chip (“first semiconductor die 200” para. 0025 FIG. 1), the semiconductor stack structure including a plurality of semiconductor chips (“stack 300 of second semiconductor dies 301” para. 0025 FIG. 1).
Ting and Kim teach packages comprising dies connected directly to a semiconductor structure and a substrate under the semiconductor structure. The “semiconductor package 10” in Kim features a “stack 300” of DRAM dies connected to a “semiconductor die 700” and a “substrate 100” (para. 0025 and 0044 FIG. 1). The “semiconductor package 10” is a memory device package (para. 0022). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that stacked DRAM dies can be used in the “package 60” of Ting to form a memory device package.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package taught Ting with the semiconductor die stack taught in Kim. A semiconductor die stack of DRAM dies can be used to form a memory device.
Ting, modified by Kim, further teaches
The upper molding layer surrounding the semiconductor stack structure (by replacing “package component 50A” with a stack structure suck as “stack 300”, the “underfill 54” no surrounds “stack 300”);
interposer connection terminals configured to connect the semiconductor stack structure to the first interposer, second interposer connection terminal between the semiconductor stack structure and the first interposer (a stack such as “stack 300” is bonded to “interconnection die 30A” through solder material under “bond pads 52” instead of “package component 50A”).
However, Ting, modified by Kim, fail to teach a chip connection terminal between the first semiconductor chip and the package substrate and between the first interposer and the second interposer, and surrounded by the lower molding layer, the chip connection terminal configured to connect the first semiconductor chip to the package substrate; conductive pillars between the first semiconductor chip and the chip connection terminal, a first adhesive layer between the first interposer and the upper molding layer, between the second interposer and the upper molding layer, and surrounding the interposer connection terminals, wherein a bottom surface of the upper molding layer, a bottom surface of the first semiconductor chip, a bottom surface of the semiconductor stack structure, a top surface of the lower molding layer, and a top surface of the first adhesive layer are coplanar with each another, wherein a vertical length of the chip connection terminal in a direction perpendicular to an upper surface of the package substrate is greater than a vertical length of each of the interposer connection terminals, and wherein a vertical length of the first conductive pillar in the direction perpendicular to the upper surface of the package substrate is greater than vertical lengths of the other conductive pillars.
Nevertheless, Pan teaches
a chip connection terminal (“first conductive bumps 510” with “first contact pads 104” para. 0028 and 0034 FIG. 6) between the first semiconductor chip (“second semiconductor device 500”, comprising “third substrate 502” and “second metallization layers 504”, para. 0028) and the package substrate (“first substrate 102” para. 0013), and surrounded by the lower molding layer (“underfill 602” para. 0047), the chip connection terminal configured to connect the first semiconductor chip to the package substrate (“second semiconductor device 500” and “first substrate 102” are bonded through “first conductive pillars 506”, “first conductive bumps 510”, and “first contact pads 104”, para. 0045)
wherein a vertical length of the chip connection terminal in a direction perpendicular to an upper surface of the package substrate is greater than a vertical length of the interposer connection terminals (“the first conductive pillars 506” have a “first thickness T.sub.1” between about 60 μm and 100 μm” and “thickness t.sub.3” between “second semiconductor device 500” and “first substrate 102” is 80 μm and 120 μm, such that the “first conductive bumps 510” with “first contact pads 104” have a height of 20 µm to 60µm, para. 0031 and 0048. Meanwhile, “second conductive pillars 508” have “a second thickness T.sub.2 of between about 20 μm and 40 μm” and “thickness t.sub.4” between “third semiconductor device 514” and “first semiconductor device 110” is between about 20 μm and 50 μm, so the “third conductive bumps 524” and “third contact pads 116” have a height of 0 µm to 30µm, para. 0033 and 0048).
and wherein a vertical length of the first conductive pillar in a direction perpendicular to an upper surface of the package substrate is greater than a vertical length of each of the second conductive pillar and the third conductive pillar (“the first conductive pillars 506 may be formed to have a first thickness T.sub.1 of between about 60 μm and 100 μm” while “second conductive pillars 508” have “a second thickness T.sub.2 of between about 20 μm and 40 μm”, para. 0032-0033).
Ting, modified by Kim, and Pan teach packages comprising semiconductor chips and bridge die connected to a substrate. While the substrate in Ting is directly formed on "through-vias 48", "first substrate 102" is formed separately and then “second semiconductor device 500" is bonded using “first conductive bump 510”. In this manner, different groups of bonded “second semiconductor die 500" and "first semiconductor die 110" can be applied to different “first substrates 102” that have already been fabricated instead of forming a specific “first substrate 102” for each set of die, depending on the intended applications. The separation between “substrate 102” and “second semiconductor device 500” is greater than the separation between “first semiconductor device 110” and “second semiconductor device 500”. This is why the vertical length of “the first conductive pillars 506” and “first conductive bumps 510” with “first contact pads 104” is greater than the vertical length of “third conductive pillars 520” and “third conductive bumps 524” with “third contact pads 116”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “first conductive bumps 510” can be used to connect separately made semiconductor devices to “first substrate 102”. Furthermore, the length of the interconnection structure between “first substrate 102” and “second semiconductor device 500” is greater than the length interconnection structure between “first semiconductor device 110” and “second semiconductor device 500” because of the separation is greater.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught between Ting and Kim with the chip connection terminal and vertical lengths of the chip connection terminal, interposer connection terminal, and the first to third conductive pillars in Pan. The chip connection terminals allow the first semiconductor chip and the package substrate to be formed individually and then bonded. The vertical lengths of the chip connection terminal and the first conductive pillar area greater than the interposer connection terminal and the second and third conductive pillar since the separation between the first semiconductor chip and the package substrate is greater than the separation between the first semiconductor chip and the first interposer and second interposer.
Ting, modified by Kim and Pan, further teach
The chip connection terminal is between the first interposer and the second interposer (the added “first conductive bumps 510” from Pan are between “interconnect die 38A and 38B”),
the first conductive pillar between the first semiconductor chip and the chip connection terminal (“through-vias 48” are between “package component 50B” and the added “first conductive bumps 510”).
However, Ting, modified by Kim and Pan, fail to teach a first adhesive layer between the first interposer and the upper molding layer, between the second interposer and the upper molding layer, and surrounding the interposer connection terminals, wherein a bottom surface of the upper molding layer, a bottom surface of the first semiconductor chip, a bottom surface of the semiconductor stack structure, a top surface of the lower molding layer, and a top surface of the first adhesive layer are coplanar with each another.
Nevertheless, Karikalan teaches a first adhesive layer (“adhesion layer 338” para. 0027 FIG. 3), wherein a bottom surface of the first semiconductor chip (“active die 310” para. 0027), a bottom surface of the second semiconductor chip (“active die 320” para. 0027), and a top surface of the first adhesive layer are coplanar with each another (“active die 310 and 320” are bonded to “adhesion layer 338” and the bottoms of “active dies 310 and 320” and the top surface of “adhesion layer 338” are coplanar as shown in FIG. 3).
Ting, modified by Kim and Pan, and Karikalan teach packages comprising dies bonded to interposers and a substrate. Karikalan uses “adhesion layer 338” to “secure bridge interposer 330 to first portion 311 of first active die 310 and first portion 321 of second active die 320” (para. 0027). In other words, the “adhesion layer 380” provides a more secure physical bond between “bridge interposer 330” and “active die 310 and 320”. The examiner understands that “underfill 54” in Ting may make the package more rigid and protect against deformation but the “adhesion layer 380” in Karikalan ensures the die are connected together. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “adhesion layer 380” can secure the bond between die and the interposer. Replacing the “underfill 54” formed in the gaps between “package components 50” and “interconnection die 30”, such as by depositing the “adhesion layer 380” first and then filling the rest with “underfill 54”, will yield an improved physical connection.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught between Ting, Kim, and Pan with the adhesive layer taught in Karikalan. An adhesive layer between the semiconductor chips and the interposers forms a more secure bond. The resulting structure will have a top surface of the adhesive layer, bottom surface of first semiconductor chip, and the bottom surface of the second semiconductor chip
As a result of the combination, Ting, modified by Pan and Karikalan, further teaches
wherein a bottom surface of the upper molding layer, a bottom surface of the first semiconductor chip, a bottom surface of the second semiconductor chip, a top surface of the lower molding layer, and a top surface of the first adhesive layer are coplanar with each another (bottoms of “package components 50A and 50B” contact a top surface of “encapsulant 44”. “Package components 50” and “interconnect die 30” now have an “adhesion layer 338” in between as taught in Karikalan where the “adhesion layer 338” has a top surface coplanar with bottom surfaces of “package components 50”. “Underfill 54” fills in the gaps between “package components 50” such that the bottom surface of “underfill 54”, bottom surface of “package components 50A and 50B”, top surface of “encapsulant 44”, and top surface of “adhesion layer 338” are coplanar.).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Ting, modified by Kim, Pan, and Karikalan as applied to claim 17 and further in view of Kim et al. US 20190221520 A1 (hereinafter referred to as Kim’520).
Ting, modified by Kim, Pan, and Karikalan, teaches the semiconductor package of claim 17 and further teaches
wherein the semiconductor stack structure comprises:
a second semiconductor chip on the lower molding layer (as combined, lowermost “second semiconductor dies 301” of “stack 300” from Kim is on “encapsulant 44” taught in Ting);
a plurality of third semiconductor chips stacked on the second semiconductor chip in a vertical direction perpendicular to an upper surface of the package substrate (more “second semiconductor dies 301” are stacked over the first “second semiconductor dies 301”, FIG. 1 of Kim showing two).
However, Karikalan, modified by Chien and Kim, fail to teach each of the plurality of third semiconductor chips having a horizontal length that is less than a horizontal length of the second semiconductor chip; and a molding layer on the second semiconductor chip and surrounding the plurality of third semiconductor chips.
Nevertheless, Kim’520 teaches
each of the plurality of third semiconductor chips (“semiconductor chips 120-1~120-4” of “chip stack 120”, para. 0021 FIG. 1 and 8) having a horizontal length that is less than a horizontal length of the second semiconductor chip (“The base chip 110 may have a size, namely, a footprint, larger than that of each of semiconductor chips 120-17120-4” para. 0021 FIG. 1 and 8); and
a molding layer on the second semiconductor chip and surrounding the plurality of third semiconductor chips (“encapsulant 140” para. 0020 FIG. 1 and 8).
Ting, modified by Kim, Pan, and Karikalan, and Kim’520 teach semiconductor packages comprising semiconductor chip stacks and a separate chip connected to an interposer. The “base chip 110” in Kirm’520 may have different dimensions or the same dimensions as the “semiconductor chips 120- 1°120-4” (para. 0021). By having a larger “base die 110”, more “bumps 118” can be placed, which increases the amount of possible electrical connections for the stack and the structural stability of the stack. The “encapsulant 140” further insulates and physically protects the “chip stack 120”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that a longer horizontal length of “base die 110” allows for greater device connectivity and improves the physical bond between the semiconductor chip stack and other devices and “encapsulant 140” further protects the sides and gaps between the third semiconductor chips.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package taught between Ting, Kim, Pan, and Karikalan with the second semiconductor chip and the molding layer taught in Kim’520. A second semiconductor chip with greater horizontal length enable greater device connectivity and a molding layer improves the protection of the third semiconductor chips.
Prior art not cited but relevant to applicant’s disclosure
Ryu et al. US 20200168550 A1, teaching a first semiconductor chip and a semiconductor stack structure connected to an interposer through interposer connection terminals, the first semiconductor chip is connected to the package substrate through chip connection terminals.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ERIC MANUEL MULERO FLORES/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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