Prosecution Insights
Last updated: July 17, 2026
Application No. 17/862,675

MEMORY DEVICE AND ELECTRONIC APPARATUS INCLUDING THE SAME

Non-Final OA §103
Filed
Jul 12, 2022
Priority
Jul 13, 2021 — RE 10-2021-0091856 +1 more
Examiner
KHALIFA, MOATAZ
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Industry-Academic Cooperation Foudation Yonsei University
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
91%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
54 granted / 59 resolved
+23.5% vs TC avg
Minimal -0% lift
Without
With
+-0.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
37 currently pending
Career history
108
Total Applications
across all art units

Statute-Specific Performance

§103
93.6%
+53.6% vs TC avg
§102
1.9%
-38.1% vs TC avg
§112
2.9%
-37.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 59 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Invention A along with the corresponding claims 1-19 in the reply filed on 02/13/2026 is acknowledged. Claim 20 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention B, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02/13/2026. Specification The disclosure is objected to because of the following informalities: the specification contains reference to the element numbered “112” in 4 different places in the specification and is referred to in the context of: “… the second two-dimensional material region 112…”. However, the “second two-dimensional material region” is referenced as “122” throughout the specification. Additionally, the reference “112” does not exist in any of the drawings submitted in the disclosure. The examiner believes that this is a typographical error and that “112” needs to be corrected to “122” to establish clarity and consistency in the specification. Appropriate correction is required. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 11 and 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over Reed et al, US 20160181516 A1 (Reed) in view of Wu et al. Strain-based room-temperature non-volatile MoTe2 ferroelectric phase change transistor. Nat. Nanotechnol. 14, 668–673 (2019), https://doi.org/10.1038/s41565-019-0466-2 (Wu). Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s) Regarding claim 1; Reed teaches a memory device (Reed: Annotated Fig (13) shared in this OA: 100)B comprising: a two-dimensional material layer (110) including a two-dimensional material ([0083]); a contact region (Contact Region) at an edge of the two-dimensional material layer (110); and one or more electrodes (120; 130) which are electrically connected to the contact region (Contact Region) and configured to apply voltage ([0083]) to change a domain of an adjacent region, which is adjacent to the contact region of the two-dimensional material layer. PNG media_image1.png 599 812 media_image1.png Greyscale Reed does not explicitly teach configured to apply voltage to change a domain of an adjacent region, which is adjacent to the contact region of the two-dimensional material layer. Wu teaches configured to apply voltage (Wu: Annotated Fig (1) shared in this OA: VDS ; See page 1 right column lines 40-44 of the PDF copy of Wu attached to OA or see the section titled “Main” of the web-based version of the article “…, where the strain in the MoTe2 flakes evolves with applied gate voltage across the ferroelectric” ) to change a domain of an adjacent region, which is adjacent to the contact region (Contact Region) of the two-dimensional material layer (Two-Dimensional Material Layer). Reed and Wu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Reed by using the applied voltage from the electrodes in the contact region to change the domain of the two-dimensional material layer as disclosed in Wu to achieve the predictable result of increasing the processing speed of the memory device while decreasing the volatility of the system leading to a better performing device. PNG media_image2.png 609 1150 media_image2.png Greyscale Regarding claim 11; Reed in view of Wu teaches all the limitations of the memory device of claim 1. Further, Reed teaches wherein the contact region (Reed: Annotated Fig (13) shared in this OA: Contact Region) comprises at least one of a hole structure, a groove structure, or a step terrace structure (step structure right under the electrodes 120 and 130). Regarding claim 14; Reed in view of Wu teaches all the limitations of the memory device of claim 1 Further, Reed teaches wherein the two-dimensional material (Reed: Annotated Fig (13) shared in this OA: 110) comprises transition metal dichalcogenide (TMD) ([0083]). Regarding claim 15; Reed in view of Wu teaches all the limitations of the memory device of claim 1. Further, Reed teaches wherein the two-dimensional material (Reed: Fig (13): 240) comprises at least one of MoS2, MoTe2, MoSe2, WS2, WSe2, or WTe2 ([0096]). Regarding claim 16; Reed in view of Wu teaches all the limitations of the memory device of claim 1. Further, Reed teaches wherein the voltage is applied by the one or more electrodes (Reed: Annotated Fig (13) shared in this OA: 120; 130) at a direction parallel to a planar surface of the two-dimensional material layer (110). Regarding claim 17; Reed in view of Wu teaches all the limitations of the memory device of claim 1. Further, Reed teaches wherein the voltage applied by the one or more electrodes (Reed: Annotated Fig (13) shared in this OA: 120; 130) is -2 V to - 4 V ([0077]). Regarding claim 18; Reed in view of Wu teaches all the limitations of the memory device of claim 1. Reed does not teach wherein the voltage applied by the one or more electrodes is applied for 50 ms to 400 ms. Wu teaches wherein the voltage applied by the one or more electrodes (Wu: Annotated Fig (1) shared in this OA: Electrode) is applied for 50 ms to 400 ms (see page 7 left column lines 26-28 of the PDF copy of Wu shared in this OA Page 7 or the section titled “Device Characterization” in the web-based version of the article “The devices were characterized using low-frequency a.c. lock-in techniques (3 Hz) with the a.c. voltage signal provided by a separate phase-locked function generator.”. Where it can be seen that applying the signal at 3 Hz implies the duration recited in the claim). Reed and Wu are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Reed by using the voltage application times disclosed in Wu to achieve the anticipated result of switching the domains and pashes of the two-dimensional material in a quick fashion to allow for fast switching capabilities of the device which leads to a better performing device. Regarding claim 19; Reed in view of Wu teaches all the limitations of the memory device of claim 1. Further, Reed teaches further comprising: a source region (Reed: Fig (15): 210); and a drain region (220) spaced apart from the source region (210). Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Reed et al, US 20160181516 A1 (Reed) in view of Wu et al. Strain-based room-temperature non-volatile MoTe2 ferroelectric phase change transistor. Nat. Nanotechnol. 14, 668–673 (2019), https://doi.org/10.1038/s41565-019-0466-2 (Wu) in further view of Li et al, CN 210607295 U (Li). Regarding claim 12; Reed in view of Wu teaches all the limitations of the memory device of claim 1. Reed in view of Hou does not teach wherein the contact region has a long- axis length of 10 nm to 200 nm Li teaches wherein the contact region (Li: Fig (1): Region under electrodes 3 and 4) has a long- axis length of 10 nm to 200 nm (Translated copy of Li attached to this OA: Page 2 Line 41) Reed in view of Wu and Li are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to modify Reed in view of Wu by constructing the contact region in the range disclosed in Li to achieve the predictable result of miniaturizing the device and thus being able to add more component to the chip and thus making the device better and faster performing for being able to utilize these extra components simultaneously. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Reed et al, US 20160181516 A1 (Reed) in view of Wu et al. Strain-based room-temperature non-volatile MoTe2 ferroelectric phase change transistor. Nat. Nanotechnol. 14, 668–673 (2019), https://doi.org/10.1038/s41565-019-0466-2 (Wu) in further view of Hou et al, CN 111521262 A (Hou). Regarding claim 13; Reed in view of Wu teaches all the limitations of the memory device of claim 1. However, Reed in view of Wu does not teach wherein the contact region has a depth of 0.07 nm to 1 nm. Hou teaches wherein the contact region (Hou: Fig (1): Regions under electrodes 5 and 6) has a depth of 0.07 nm to 1 nm (Translated copy of Hou attached to this OA: see Page: 3 Line: 6). Reed in view of Wu and Hou are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art to modify Reed in view of Wu by making the contact areas thickness in the range disclosed in Hou to make the device thinner and thus achieve the predictable result of being able integrate more devices in a vertical direction to improve the performance of the device. Allowable Subject Matter Claims 2-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 2; while Reed in view of Hou teaches all the limitations of the memory device of claim 1, wherein the two-dimensional material layer comprises a first two-dimensional material region having a first domain based on a first voltage being applied by a first electrode among the one or more electrodes. Reed alone or in combination with any other available art does not teach the adjacent region is changed into a second two-dimensional material region having a second domain that is different from the first domain and a third two-dimensional material region having a third domain, and based on a voltage being applied by a second electrode among the one or more electrodes, the adjacent region is changed into the first two-dimensional material region. Claims 3-10 are objected to but otherwise allowable for their dependence on an objected to but otherwise allowable base claim (claim 2). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Moataz Khalifa whose telephone number is (703)756-1770. The examiner can normally be reached Monday - Friday (8:30 am - 5:00). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /M.K./Examiner, Art Unit 2817 /Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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Prosecution Timeline

Jul 12, 2022
Application Filed
May 05, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
91%
With Interview (-0.4%)
3y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 59 resolved cases by this examiner. Grant probability derived from career allowance rate.

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