DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 09/18/2025 has been entered.
Response to Amendment
The Amendment filed on 09/18/2025 has been entered. Claims 1-21 and newly added claim 22, remain pending in the application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/13/2025 has been considered by the examiner.
Claim Objections
Applicant is advised that should claim 19 be found allowable, claim 21 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 16-19 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al., (United States Patent Number, US 8,952,488 B2), hereinafter referenced as Yang, in view of Hideo Ichimura et al., (United States Patent Application Publication Number, US 2008/0001250 A1), hereinafter referenced as Ichimura.
Regarding claim 1, Yang teaches an integrated circuit device, comprising: an anti-fuse device including: a cup-shaped bottom anti-fuse electrode (Fig.9, formed by elements #20’ , #21’ and #25 in region 16, column 10, rows 20-30) formed in a dielectric region (Fig.9, element #12 is a dielectric, column 10, row 10); a cup-shaped anti-fuse insulator formed in an opening defined by the cup-shaped bottom anti-fuse electrode (Fig.9, element #26’ in region 16, column 9, rows 8-11); wherein a thickness of the cup-shaped anti-fuse insulator is less than 200Å (column 9, rows 25-26); a top anti-fuse electrode formed in an opening defined by the cup-shaped anti-fuse insulator (Fig.9, element #30 in region 16, column 10, row 15); and a planarized surface defining a top surface of the cup-shaped bottom anti-fuse electrode and a top surface of the top anti-fuse electrode (Fig.9, top surface of the anti-fuse is a plane that defines a top surface of the top and bottom anti-fuse electrodes).
Yang does not teach a top anti-fuse electrode contact formed on the top surface of the top anti-fuse electrode. Ichimura teaches a top anti-fuse electrode contact formed on the top surface of the top anti-fuse electrode (Fig.1, top anti-fuse electrode contact, element #83 is formed on the top surface of the top-anti-fuse electrode, element #44, paragraph [0039], rows 1-5). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Ichimura and disclose a top anti-fuse electrode contact formed on the top surface of the top anti-fuse electrode. As disclosed by Ichimura, the top contact connects the top anti-fuse electrode with top layer interconnects, and places these interconnects into a conductive state when the anti-fuse breaks down (paragraph [0039], rows 1-10), thus allowing the anti-fuse to function as a one-time programmable device (paragraph [0071], rows 7-11).
Regarding claim 2, the combination of Yang and Ichimura teaches the integrated circuit device of claim 1 as set forth in the obviousness rejection. Yang further teaches the integrated circuit device of claim 1, wherein the thickness of the cup-shaped anti-fuse insulator is between 10-200Å (column 9, rows 25-26). The claimed range, of 50-175Å, overlaps the range disclosed by the prior art, therefore, a prima facie case of obviousness exists (MPEP 2144.05).
Regarding claim 3, the combination of Yang and Ichimura teaches the integrated circuit device of claim 1 as set forth in the obviousness rejection. Yang further teaches the integrated circuit device of claim 1, wherein the thickness of the cup-shaped anti-fuse insulator is between 10-200Å (column 9, rows 25-26). The claimed range, of 75-125Å, overlaps the range disclosed by the prior art, therefore, a prima facie case of obviousness exists (MPEP 2144.05).
Regarding claim 4, the combination of Yang and Ichimura teaches the integrated circuit device of claim 1 as set forth in the obviousness rejection. Yang does not teach wherein the anti-fuse device has a breakdown voltage below 15V. Ichimura teaches wherein the anti-fuse device has a breakdown voltage below 15V (paragraph [0071], row 3-9, breakdown voltage is 2.9V). The claimed range, below 15V, overlaps the range disclosed by the prior art, therefore, a prima facie case of obviousness exists (MPEP 2144.05). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Ichimura and disclose the anti-fuse device has a breakdown voltage below 15V. As disclosed by Ichimura, by applying a voltage below 15V, such as for instance a driving voltage for a logic transistor used in an I/O interface, the dielectric breakdown can occur and a low voltage programmable semiconductor device can be obtained (paragraph [0071], rows 7-10).
Regarding claim 5, the combination of Yang and Ichimura teaches the integrated circuit device of claim 1 as set forth in the obviousness rejection. Yang does not teach wherein the anti-fuse device has a breakdown voltage below 7V. Ichimura teaches wherein the anti-fuse device has a breakdown voltage below 7V (paragraph [0071], row 3-9, breakdown voltage is 2.9V). The claimed range, below 7V, overlaps the range disclosed by the prior art, therefore, a prima facie case of obviousness exists (MPEP 2144.05). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Ichimura and disclose the anti-fuse device has a breakdown voltage below 7V. As disclosed by Ichimura, by applying a voltage below 7V, such as for instance a driving voltage for a logic transistor used in an I/O interface, the dielectric breakdown can occur and a low voltage programmable semiconductor device can be obtained (paragraph [0071], rows 7-10).
Regarding claim 6, the combination of Yang and Ichimura teaches the integrated circuit device of claim 1 as set forth in the obviousness rejection. Yang further teaches the integrated circuit device of claim 1, wherein the cup-shaped anti-fuse insulator comprises silicon oxide (SiO2), oxide-nitride-oxide (ONO), nitride-oxide-nitride (NON), or aluminum oxide (Al2O3) (Yang teaches anti-fuse insulator comprises silicon oxide, column 9, row 10).
Regarding claim 7, the combination of Yang and Ichimura teaches the integrated circuit device of claim 1 as set forth in the obviousness rejection. Yang does not teach the integrated circuit device of claim 1, comprising: a bottom anti-fuse electrode contact formed in a lower metal interconnect layer, wherein the bottom anti-fuse electrode contact is electrically connected to the cup-shaped bottom anti-fuse electrode; and wherein the top anti-fuse electrode contact is formed in an upper metal interconnect layer. Ichimura teaches the integrated circuit comprising: a bottom anti-fuse electrode contact formed in a lower metal interconnect layer (Fig.3C, element #81 is located in a lower metal interconnect layer, element #51, paragraph [0047], rows 7-9), wherein the bottom anti-fuse electrode contact is electrically connected to the cup-shaped bottom anti-fuse electrode (Fig.3C, element #81 is electrically connected to element #42, paragraph [0048], rows 6-10, paragraph [0052], rows 4-7); and wherein the top anti-fuse electrode contact is formed in an upper metal interconnect layer (Fig.3C, element #44 is formed in upper layer, element #53). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Ichimura and disclose a bottom anti-fuse electrode contact formed in a lower metal interconnect layer, wherein the bottom anti-fuse electrode contact is electrically connected to the cup-shaped bottom anti-fuse electrode; and wherein the top anti-fuse electrode contact is formed in an upper metal interconnect layer. As disclosed by Ichimura, this allows using the same process steps and materials to manufacture both anti-fuses and memory cell capacitors as part of DRAM devices (paragraph [0012], rows 1-5, paragraph [0016], rows 1-12).
Regarding claim 8, the combination of Yang and Ichimura teaches the integrated circuit device of claim 1 as set forth in the obviousness rejection. Yang does not teach the integrated circuit device of claim 1, comprising a transistor including a doped source region and a doped drain region; wherein the cup-shaped bottom anti-fuse electrode is electrically connected to a silicide region formed on the source region or a silicide region formed on the drain region of the transistor. Ichimura teaches the integrated circuit comprising a transistor including a doped source region and a doped drain region (Fig.1, element #16, paragraph [0045], rows 1-4); wherein the bottom anti-fuse electrode is electrically connected to a silicide region formed on the source region or a silicide region formed on the drain region of the transistor (Fig.1, bottom electrode, element #42 is connected to source/drain region, element #16, paragraph [0045], rows 1-4, and transistors have a silicide layers on the source and drain regions, paragraph [0044], rows 14-15). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Ichimura and disclose the integrated circuit device of claim 1, comprising a transistor including a doped source region and a doped drain region; wherein the cup-shaped bottom anti-fuse electrode is electrically connected to a silicide region formed on the source region or a silicide region formed on the drain region of the transistor. As disclosed by Ichimura, this allows the anti-fuse to operate as a one-time programable memory cell (paragraph [0071], rows 7-11), while the silicide layer helps reduce the contact resistance between the source/drain region and the bottom anti-fuse electrode.
Regarding claim 16, Yang teaches a method, comprising forming an anti-fuse device by a process including: forming a tub opening in a dielectric region (Fig.2, opening #18R is formed in the dielectric layer, element #12, column 12, row 10); depositing a conformal metal over the dielectric region and extending into the tub opening to form a cup-shaped bottom anti-fuse electrode in the tub opening (Fig.3, 4, 5 metal formed by elements #20, #21 and #25 in region 16 are deposited over element #12, extend into the opening, and form the cup-shape bottom anti-fuse electrode, column 10, rows 20-30); depositing an insulator layer with a layer thickness of less than 200 Å over the conformal metal to define a cup-shaped anti-fuse insulator in an opening defined by the cup-shaped bottom anti-fuse electrode (Fig.7, element #26 in region 16, is deposited in the opening defined by the bottom anti-fuse electrode and has a thickness less than 200 Å, column 9, rows 25-26), the cup-shaped anti-fuse insulator including a laterally-extending anti-fuse insulator base and a vertically-extending anti-fuse insulator sidewall extending upwardly from the laterally-extending anti-fuse insulator base (Fig.7, element #26 in region 16 has the features claimed); depositing a top electrode metal over the insulator layer and extending into an opening defined by the cup-shaped anti-fuse insulator to form a top anti-fuse electrode (Fig.8, element #28 in region 16, column 9, rows 27-30, is deposited and forms a top anti-fuse electrode, element #30 in region 16, column 10, rows 12-15); performing a planarization process to remove upper portions of the conformal metal, insulator layer, and top electrode metal outside the tub opening (Fig.8 and 9 the planarization process removes the upper portions of the layers outside the opening, column 10, rows 5-9 and 20-30), wherein the planarization process defines a planarized surface including a planarized top surface of the bottom anti-fuse electrode, a planarized top surface of the anti-fuse insulator, and a planarized top surface of the top anti-fuse electrode (Fig.9, the planarization process defines the top surface of the anti-fuse and includes a top surface of the top and bottom anti-fuse electrodes, element #20’ and #21’ and the insulator, element #26’, in region 16).
Yang does not teach and forming a top anti-fuse electrode contact on the planarized top surface of the top anti- fuse electrode. Ichimura teaches forming a top anti-fuse electrode contact on the top surface of the top anti- fuse electrode (Fig.1, top anti-fuse electrode contact, element #83 is formed on the top surface of the top anti-fuse electrode, element #44, paragraph [0039], rows 1-5). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Ichimura and disclose a top anti-fuse electrode contact formed on the top surface of the top anti-fuse electrode. As disclosed by Ichimura, the top contact connects the top anti-fuse electrode with top layer interconnects, and places these interconnects into a conductive state when the anti-fuse breaks down (paragraph [0039], rows 1-10), thus allowing the anti-fuse to function as a one-time programmable device (paragraph [0071, rows 7-11).
Regarding claim 17, the combination of Yang and Ichimura teaches the method of claim 16 as set forth in the obviousness rejection. Yang further teaches the method of claim 16, comprising depositing the insulator layer with the layer thickness in the range 10-200 Å. The claimed range, of 50-175Å, overlaps the range disclosed by the prior art, therefore, a prima facie case of obviousness exists (MPEP 2144.05).
Regarding claim 18, the combination of Yang and Ichimura teaches the method of claim 16 as set forth in the obviousness rejection. Yang further teaches the method of claim 16, comprising depositing the insulator layer with the layer thickness in the range 10-200 Å. The claimed range, of 75-125Å, overlaps the range disclosed by the prior art, therefore, a prima facie case of obviousness exists (MPEP 2144.05).
Regarding claims 19 and 21, the combination of Yang and Ichimura teaches the method of claim 16 as set forth in the obviousness rejection. Yang further teaches the method of claim 16, wherein the anti-fuse device is formed using only one photomask process (only one photomask process is used to form opening #18R in the dielectric layer #12, column 5, rows 15-20, mask #24 is not required to form the anti-fuse device).
Claims 9-11, 13, 14 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of disclosed prior art Wang et al., (United States Patent Application Publication Number, US 2008/0012138 A1), hereinafter referenced as Wang.
Regarding claim 9, Yang teaches an integrated circuit device, comprising: an interconnect structure (Fig.9, region 14, column 3, row 45-47, and a substrate, column 3, rows 58-59 and column 4, rows 14-17) including: a lower interconnect element formed in a lower metal layer (column 4, rows 14-17); and an interconnect via (Fig.9, via formed in region 14 by elements #20’, #21’, #25 and #30, column 3, row 45-47, column 5, rows 58-60) formed in a dielectric region (Fig.9, element #12, column 3, row 41) above the lower metal layer (column 3, rows 58-59 and column 4, rows 14-17), the interconnect via electrically connecting the lower interconnect element (column 3, rows 47-50).
Yang does not teach an upper interconnect element formed in an upper metal layer, the dielectric region below the upper metal layer, the interconnect via electrically connecting the upper interconnect element. Wang teaches an upper interconnect element formed in an upper metal layer (Fig.9, element #242, paragraph [0036], rows 1-3), the dielectric region below the upper metal layer (Fig.9, element #24, paragraph [0038], row 14), the interconnect via (Fig.9, element #240) electrically connecting the upper interconnect element (Fig.9, elements #240 and #242 are electrically connected, paragraph [0036], rows 1-3). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Wang and disclose an upper interconnect element formed in an upper metal layer, the dielectric region below the upper metal layer, the interconnect via electrically connecting the upper interconnect element. Electronic circuits use multiple interconnect layers connected through vias to allow electrical connections to different components of the circuit.
Yang further teaches an anti-fuse device including: a cup-shaped bottom anti-fuse electrode (Fig.9, formed by elements #20’, #21’ and #25 in region 16, column 10, rows 20-30) formed in the dielectric region (Fig.9, element #12 is a dielectric, column 10, row 10); a cup-shaped anti-fuse insulator formed in an opening defined by the cup- shaped bottom anti-fuse electrode (Fig.9, element #26’ in region 16, column 9, rows 8-11); wherein a thickness of the cup-shaped anti-fuse insulator is less than 200Å (column 9, rows 25-26); and a top anti-fuse electrode formed in an opening defined by the cup-shaped anti-fuse insulator (Fig.9, element #30 in region 16, column 10, row 15, wherein the interconnect via and the cup-shaped bottom anti-fuse electrode comprise respective portions of the same metal layer (Fig.9, they both comprise portions of metal layer #21 and #25).
Regarding claim 10, the combination of Yang and Wang teaches the integrated circuit device of claim 9 as set forth in the obviousness rejection. Yang further teaches the integrated circuit device of claim 9, wherein the thickness of the cup-shaped anti-fuse insulator is between 10-200Å (column 9, rows 25-26). The claimed range, of 50-175Å, overlaps the range disclosed by the prior art, therefore, a prima facie case of obviousness exists (MPEP 2144.05).
Regarding claim 11, the combination of Yang and Wang teaches the integrated circuit device of claim 9 as set forth in the obviousness rejection. Yang further teaches the integrated circuit device of claim 9, wherein the thickness of the cup-shaped anti-fuse insulator is between 10-200Å (column 9, rows 25-26). The claimed range, of 75-125Å, overlaps the range disclosed by the prior art, therefore, a prima facie case of obviousness exists (MPEP 2144.05).
Regarding claim 13, the combination of Yang and Wang teaches the integrated circuit device of claim 9 as set forth in the obviousness rejection. Yang further teaches the integrated circuit device of claim 1, wherein the cup-shaped anti-fuse insulator comprises silicon oxide (SiO2), oxide-nitride-oxide (ONO), nitride-oxide-nitride (NON), or aluminum oxide (Al2O3) (Yang teaches the anti-fuse insulator comprises silicon oxide, column 9, row 10).
Regarding claim 14, the combination of Yang and Wang teaches the integrated circuit device of claim 9 as set forth in the obviousness rejection. Yang further teaches the integrated circuit device of claim 9, wherein: the anti-fuse device is electrically connected to bottom anti-fuse electrode contact (connections requires a contact, column 3, rows 47-50 and rows 58-58, column 4, rows 14-17); the lower interconnect element and the bottom anti-fuse electrode contact are formed in a lower metal interconnect layer (they are both form is the first interconnect level (column 3, rows 58-59 and column 4, rows 14-17).
Yang does not teach the anti-fuse device is electrically connected between a bottom anti-fuse electrode contact and a top anti-fuse electrode contact; and the upper interconnect element and the top anti-fuse electrode contact are formed in an upper metal interconnect layer. Wang teaches the anti-fuse device (Fig.9, structure in region #100) is electrically connected between a bottom anti-fuse electrode contact (Fig.9, bottom anti-fuse electrode contact, element #102) and a top anti-fuse electrode contact (Fig.9, top anti-fuse electrode contact, element #142); and the upper interconnect element and the top anti-fuse electrode contact are formed in an upper metal interconnect layer (Fig.9, elements #142 and #242 are in the formed in the same interconnect layer, paragraph [0039], rows 1-2). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Wang and disclose the anti-fuse device is electrically connected between a bottom anti-fuse electrode contact and a top anti-fuse electrode contact; and the upper interconnect element and the top anti-fuse electrode contact are formed in an upper metal interconnect layer. This allows using the same process steps and materials to manufacture both anti-fuses contacts and electrical connections between interconnect layers of the integrated circuit, which may save costs and increase yields.
Regarding claim 22, the combination of Yang and Wang teaches the integrated circuit device of claim 9 as set forth in the obviousness rejection. Yang further teaches the integrated circuit device of claim 9, wherein a top surface of the top anti-fuse electrode is coplanar with a top surface of the interconnect via (Fig.9, top surface of element #30 of the anti-fuse in region 16 is coplanar with the top surface of the interconnect via, element #30 of the via in region 14).
Claims 12 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Wang and in view of Ichimura.
Regarding claim 12, the combination of Yang and Wang teaches the integrated circuit device of claim 9 as set forth in the obviousness rejection. The combination of Yang and Wang does not teach wherein the anti-fuse device has a breakdown voltage below 15V. Ichimura teaches wherein the anti-fuse device has a breakdown voltage below 15V (paragraph [0071], row 3-9, breakdown voltage is 2.9V). The claimed range, below 15V overlaps the range disclosed by the prior art, therefore, a prima facie case of obviousness exists (MPEP 2144.05). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Ichimura and disclose wherein the anti-fuse device has a breakdown voltage below 15V. As disclosed by Ichimura, by applying a voltage below 15V, such as for instance a driving voltage for a logic transistor used in an I/O interface, the dielectric breakdown can occur and a low voltage programmable semiconductor device can be obtained (paragraph [0071], rows 7-10).
Regarding claim 15, the combination of Yang and Wang teaches the integrated circuit device of claim 9 as set forth in the obviousness rejection. Yang does not teach the integrated circuit device of claim 9, comprising a transistor including a doped source region and a doped drain region; wherein the cup-shaped bottom anti-fuse electrode is electrically connected to a silicide region formed on the source region or a silicide region formed on the drain region of the transistor.
Wang teaches the integrated circuit comprising a transistor including a doped source region and a doped drain region (Fig.18, transistor element #162, has a source and drain, paragraph [0054], rows 1-4); wherein the cup-shaped bottom anti-fuse electrode is electrically connected drain region (Fig.18, bottom electrodes of anti-fuses elements #160 are connected to the drain region, paragraph [0054], rows 1-4). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Wang and disclose wherein the cup-shaped bottom anti-fuse electrode is electrically connected to a region formed on the source region or a region formed on the drain region of the transistor. As disclosed by Wang, this allows the anti-fuse to operate as a one-time programable anti-fuse capable of being operated under two voltages for read and write operations (paragraph [0049] - [0051]).
The combination of Yang and Wang does not teach the integrated circuit comprising the bottom anti-fuse electrode is electrically connected to a silicide region formed on the source region or a silicide region formed on the drain region of the transistor. Ichimura teaches the bottom anti-fuse electrode is electrically connected to a silicide region formed on the source region or a silicide region formed on the drain region of the transistor (Fig.1, bottom electrode, element #42 is connected to source/drain regions, element #16, paragraph [0045], rows 1-4, and transistor have a silicide layers on the source and drain regions, paragraph [0044], rows 14-15). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Ichimura and disclose the integrated circuit comprising the bottom anti-fuse electrode is electrically connected to a silicide region formed on the source region or a silicide region formed on the drain region of the transistors. The silicide layer helps reduce the contact resistance between the source/drain region and the bottom anti-fuse electrode.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Wang and in view of Peter S. Kirlin et al. (United States Patent Number, US 5,976,928), hereinafter referenced as Kirlin.
Regarding claim 20, the combination of Yang and Wang teaches the integrated circuit device of claim 16 as set forth in the obviousness rejection. The combination of Yang and Wang does not teach the method of claim 16, comprising: depositing a dielectric barrier layer over a planarized upper surface defined by the planarization process, the dielectric barrier layer extending over a vertically-extending sidewall of the cup-shaped bottom anti-fuse electrode, the vertically-extending anti-fuse insulator sidewall, and the top anti-fuse electrode; depositing an upper dielectric layer over the dielectric barrier layer; etching the upper dielectric layer and the dielectric barrier to form a top anti-fuse electrode contact opening exposing an upper surface of the top anti-fuse electrode, wherein the dielectric barrier layer acts as an etch stop; and filling the top anti-fuse electrode contact opening to form the top anti-fuse electrode contact on the planarized top surface of the top anti-fuse electrode. Kirlin teaches depositing a dielectric barrier layer over a planarized upper surface defined by the planarization process (Fig.2E, element #112, column 13, rows 5-6 is deposited over the planarized surface, top surface showed in Fig.2D, column 12, rows 61-62), the dielectric barrier layer extending over a vertically-extending sidewall of the cup-shaped bottom anti-fuse electrode (Fig.2E, barrier layer, element #112 extends over vertically extending sidewalls of the bottom electrode, formed by elements #104 and #106, column 12, rows 35-27), the vertically-extending anti-fuse insulator sidewall (Fig.2E, barrier layer, element #112 extends over vertically extending sidewalls of the insulator, element #108, column 12, rows 37 and 46-54), and the top electrode (Fig.2E, barrier layer, element #112 extends over vertically extending sidewalls of the top electrode, element #110, column 12, row 37-38); depositing an upper dielectric layer over the dielectric barrier layer (Fig.2E, element #114, column 13, rows 5-7); etching the upper dielectric layer and the dielectric barrier (column 13, rows 9-11) to form a top anti-fuse electrode contact opening exposing an upper surface of the top anti-fuse electrode (Fig.2F, column 13, rows 9-11) wherein the dielectric barrier layer acts as an etch stop (the barrier layer, element #112, can be Si3N4 and therefore acts as an etch stop for the upper dielectric layer, element #114 which can be SiO2, column 11, rows 57-65) and filling the top anti-fuse electrode contact opening (Fig.2F, the opening is filled) to form a top electrode contact on the planarized top surface of the top anti-fuse electrode (Fig.2F, conductive elements #116 forms a top electrode contact on the planarized top surface of element #110). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Kirlin and disclose the method comprising: depositing a dielectric barrier layer over a planarized upper surface defined by the planarization process, the dielectric barrier layer extending over a vertically-extending sidewall of the cup-shaped bottom anti-fuse electrode, the vertically-extending anti-fuse insulator sidewall, and the top anti-fuse electrode; depositing an upper dielectric layer over the dielectric barrier layer; etching the upper dielectric layer and the dielectric barrier to form a top anti-fuse electrode contact opening exposing an upper surface of the top anti-fuse electrode, wherein the dielectric barrier layer acts as an etch stop; and filling the top anti-fuse electrode contact opening to form the top anti-fuse electrode contact on the planarized top surface of the top anti-fuse electrode. As disclosed by Kirlin, this method does not require dry etching steps which may result in unwanted structures at the edges of electrodes (column 1, rows 22-26), and is cost effective (column 6, rows 55-56).
Response to Arguments
Applicant’s arguments filed on 08/26/2025 have been fully considered but they
are not persuasive. Applicant’s arguments with respect to independent claims 1, 9 and 16 have been considered but are moot because the new ground of rejection does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CRISTIAN A TIVARUS whose telephone number is (703)756-4688. The examiner can normally be reached Monday- Friday 7:30AM -5:00 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at (571)270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899