DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 03/02/2026 has been entered. Claims 1-7, 9-20, 22 and newly added claim 23, remain pending in the application. Claims 8 and 21 have been cancelled.
Claim Objections
Claim 16 is objected to because of the following informalities: “conformal metal over the dielectric region and (a) extending” should read “conformal metal over the dielectric region (a) extending”. Appropriate correction is required.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 19 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 19 recites the limitation: “The method of Claim 16, wherein the anti-fuse device is formed using only one photomask process”. The method of Claim 16, on which claim 19 is dependent on, recites the steps: “forming an anti-fuse device by a process including forming a tub opening in a dielectric region” and “forming a top anti-fuse electrode contact on the planarized top surface of the top anti-fuse electrode”. As described in paragraphs [0061] and [0074] of the current application, respectively, both step are performed using patterning /a photomask, Therefore the method of claim 16, as described in the written specification, requires using at least two photomask processes, while claim 19 limitation requires only one photomask process. Furthermore, no other parts of the specification appear to include a written description of how the limitations above may work together.
For the purpose of examination, claim 19 will be interpreted as “The method of Claim 16, wherein the anti-fuse device is formed using at least two photomask processes”.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 19 recites the limitation: “The method of Claim 16, wherein the anti-fuse device is formed using only one photomask process”. The method of Claim 16, on which claim 19 is dependent on, recites the steps: “forming an anti-fuse device by a process including forming a tub opening in a dielectric region” and “forming a top anti-fuse electrode contact on the planarized top surface of the top anti-fuse electrode”. As described in paragraphs [0061] and [0074], respectively, both step are performed using patterning /a photomask, Therefore, the method of claim 16, as described in the written specification, requires using two photomask processes, while claim 19 limitation requires only one photomask process. For the purpose of examination, claim 19 will be interpreted as “The method of Claim 16, wherein the anti-fuse device is formed using at least two photomask processes”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 9-11, 13, 14, 16-19 and 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gambino et al., (United States Patent Number US 6,081,021), hereinafter referenced as Gambino.
Regarding claim 9, Gambino teaches an integrated circuit device, comprising: an interconnect structure including: a lower interconnect element formed in a lower metal layer (Fig.28, element #315); an upper interconnect element formed in an upper metal layer (Fig.28, element #342 which fills the opening #340, located on the left side of the figure); and an interconnect via formed in a dielectric region between the lower metal layer and the upper metal layer, the interconnect via electrically connecting the upper interconnect element to the lower interconnect element (Fig.28, element #328 located on the left side of the figure and labeled in Fig.26, formed in the dielectric layer, element #307 connects element #315 to element #342); and an anti-fuse device including: a cup-shaped bottom anti-fuse electrode formed in the dielectric region from a first metal laver (Fig.28, element #328 located on the right side of the figure); a cup-shaped anti-fuse insulator formed in an opening defined by the cup-shaped bottom anti-fuse electrode (Fig.28, element #322); wherein a thickness of the cup-shaped anti-fuse insulator is less than 200Å (column 5, row 26-29); and a top anti-fuse electrode formed in an opening defined by the cup-shaped anti-fuse insulator from a second metal layer (Fig.28, element #370); wherein the interconnect via and the cup-shaped bottom anti-fuse electrode comprise respective portions of the first metal layer (Fig.21, both comprise portions of the same layer, element #326); and wherein the interconnect via is free of the second metal layer (Fig.22, layer element #370 is not present inside the via).
Regarding claim 10, Gambino teaches the integrated circuit of claim 9 as set forth in the anticipation rejection. Gambino further teaches the integrated circuit device of Claim 9, wherein the thickness of the cup-shaped anti-fuse insulator is in the range of 50-175Å (column 5, row 26-29).
Regarding claim 11, Gambino teaches the integrated circuit of claim 9 as set forth in the anticipation rejection. Gambino further teaches the integrated circuit device of Claim 9, wherein the thickness of the cup-shaped anti-fuse insulator is in the range of 75-125Å (column 5, row 26-29).
Regarding claim 13, Gambino teaches the integrated circuit of claim 9 as set forth in the anticipation rejection. Gambino further teaches the integrated circuit device of Claim 9, wherein the cup-shaped anti-fuse insulator comprises silicon oxide (SiO2), oxide-nitride-oxide (ONO), nitride-oxide- nitride (NON), or aluminum oxide (A1203) (column 5, row 26-29).
Regarding claim 14, Gambino teaches the integrated circuit of claim 9 as set forth in the anticipation rejection. Gambino further teaches the integrated circuit device of Claim 9, wherein: the anti-fuse device is electrically connected between a bottom anti-fuse electrode contact (Fig.25, element #310) and a top anti-fuse electrode contact (Fig.25, element #342 that fills the opening #340 located on the right side of the figure); the lower interconnect element and the bottom anti-fuse electrode contact are formed in a lower metal interconnect layer (Fig.25, elements #315 and #310 are formed in a lower metal interconnect layer); and the upper interconnect element and the top anti-fuse electrode contact are formed in an upper metal interconnect layer (Fig.28, elements #342 are formed in an upper metal interconnect layer).
Regarding claim 16, Gambino teaches a method, comprising forming an anti-fuse device by a process including: forming a tub opening and a separate via opening in a dielectric region (Fig.12, via opening #330 and tub opening #320 in the dielectric region #307); depositing a conformal metal over the dielectric region (a) extending into and partially filling the tub opening to form a cup-shaped bottom anti-fuse electrode in the tub opening and (b) extending into and fully filling the via opening to form a conductive via (Fig.13, metal layer #326); depositing an insulator layer with a layer thickness of less than 200A over the conformal metal to define a cup-shaped anti-fuse insulator in an opening defined by the cup-shaped bottom anti-fuse electrode, the cup-shaped anti-fuse insulator including a laterally-extending anti-fuse insulator base and a vertically-extending anti-fuse insulator sidewall extending upwardly from the laterally-extending anti-fuse insulator base (Fig.21, insulator layer, element #322, has a thickness less than 200A, column 5, rows 26-29); depositing a top electrode metal over the insulator layer and extending into an opening defined by the cup-shaped anti-fuse insulator to form a top anti-fuse electrode (Fig.22, element #370); performing a planarization process to remove upper portions of the conformal metal, insulator layer, and top electrode metal outside the tub opening, wherein the planarization process defines a planarized surface including a planarized top surface of the bottom anti-fuse electrode, a planarized top surface of the anti-fuse insulator, and a planarized top surface of the top anti-fuse electrode (Fig.23); and forming a top anti-fuse electrode contact on the planarized top surface of the top anti-fuse electrode (Fig.28, element #342 that fills opening #340 located on the right side of the figure).
Regarding claim 17, Gambino teaches the method of claim 16 as set forth in the anticipation rejection. Gambino further teaches the method of Claim 16, wherein the thickness of the cup-shaped anti-fuse insulator is in the range of 50-175Å (column 5, row 26-29).
Regarding claim 18, Gambino teaches the method of claim 16 as set forth in the anticipation rejection. Gambino further teaches the method of Claim 16, wherein the thickness of the cup-shaped anti-fuse insulator is in the range of 75-125Å (column 5, row 26-29).
Regarding claim 19, Gambino teaches the method of claim 16 as set forth in the anticipation rejection. Gambino further teaches the method of Claim 16, wherein the anti-fuse device is formed using at least two photomask processes (a photomask process for forming the tup and via openings shown in Fig.12, and a second photomask process to form the top anti-fuse electrode contact shown in Fig.19).
Regarding claim 22, Gambino teaches the integrated circuit of claim 9 as set forth in the anticipation rejection. Gambino further teaches the integrated circuit device of Claim 9, wherein a top surface of the top anti-fuse electrode is coplanar with a top surface of the interconnect via (Fig.23, top surface of element #370 and top surface of element #328 located on the left side of the figure are coplanar).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over in view of Wang et al., (United States Patent Application Publication Number, US 2008/0012138 A1), hereinafter referenced as Wang, in view of Hideo Ichimura et al., (United States Patent Application Publication Number, US 2008/0001250 A1), hereinafter referenced as Ichimura, and in view of Gambino.
Regarding claim 1, Wang teaches an integrated circuit device, comprising: a transistor including a doped source region and a doped drain region (Fig.15, annotated below); an anti-fuse device formed over the transistor and including (Fig.15, elements #150 are over and connected to the drain region, paragraph [0054], rows 1-4), and a bottom anti-fuse electrode formed in a dielectric layer (while not explicitly shown in Fig.15, the anti-fuse electrodes are formed in dielectric layers as in Fig.8 and Fig.9) .
Wang does not teach a cup-shaped bottom anti-fuse electrode is formed on a silicide region formed on the source region or on a silicide region formed on the drain region of the transistor. Ichimura teaches the bottom anti-fuse electrode is formed on a silicide region formed on the source region or on a silicide region formed on the drain region of the transistor (Fig.1, bottom electrode, element #42 is connected to source/drain regions, element #16, paragraph [0045], rows 1-4, and there are silicide layers on the source and drain regions, paragraph [0044], rows 14-15). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Ichimura and disclose a bottom anti-fuse electrode is formed on a silicide region formed on the source region or on a silicide region formed on the drain region of the transistor. The silicide layer helps reduce the contact resistance between the source/drain region and the bottom anti-fuse electrode.
Wang further teaches a bottom anti-fuse electrode formed in a dielectric region (Fig.8, element #132 formed in dielectric layers #24 and 26), an anti-fuse insulator formed in an opening defined by the bottom anti-fuse electrode (Fig.8, element #134); wherein a thickness of the cup-shaped anti-fuse insulator is less than 200A (paragraph [0048], rows 11-14); a top anti-fuse electrode formed in an opening defined by the cup-shaped anti-fuse insulator (Fig.8, formed by elements #138 and #140); and a planarized top surface of the anti-fuse device defining a planarized top surface of the bottom anti-fuse electrode and a planarized top surface of the top anti-fuse electrode (see Fig.8). Wang does not teach the cup-shaped bottom electrode and insulator but teaches anti-fuses with electrodes and insulator layers having different shapes (Regions 100 of Fig.8 and Fig.9). The combination of Wang an Ichimura does not teach a top anti-fuse electrode contact formed on the planarized top surface of the top anti-fuse electrode.
Gambino teaches a cup-shaped bottom anti-fuse electrode formed in a dielectric region (Fig.28, element #328 on the right side of the figure, formed in the dielectric region #307), a cup-shaped anti-fuse insulator formed in an opening defined by the cup-shaped bottom anti-fuse electrode (Fig.28, element #322); wherein a thickness of the cup-shaped anti-fuse insulator is less than 200Å (column 5, row 26-29); a top anti-fuse electrode formed in an opening defined by the cup-shaped anti-fuse insulator(Fig.28, element #370); and a planarized top surface of the anti-fuse device defining a planarized top surface of the cup-shaped bottom anti-fuse electrode and a planarized top surface of the top anti-fuse electrode (Fig.23 shows a planarized top surface that define the top surfaces of the two electrodes); and a top anti-fuse electrode contact formed on the planarized top surface of the top anti-fuse electrode (Fig.28, contact element #342 that fills the opening #340 located on the right side of the figure). Thus, both references Wang and Gambino teach an anti-fuse that can be used for programing logic chips and write-once memories. A person skilled in the art before the effective filing date of the claimed invention would have recognized that the anti-fuse disclosed by Wang could have been replaced for the anti-fuse disclosed by Gambino because both serve the same purpose of providing an anti-fuse can be used for programing logic chips and write-once memories. Furthermore, a person skilled in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of providing an anti-fuse can be used for programing logic chips and write-once memories. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Gambino and disclose a cup-shaped anti-fuse. As compared to the anti-fuse disclosed by Wang in Fig.8, the anti-fuse of Gambino can be formed in a single dielectric layer between two metal interconnect layers. Furthermore, the top contact connects the top anti-fuse electrode with a voltage source and allows the anti-fuse to function as a one-time programmable device, by applying a breaking voltage.
Regarding claim 2, the combination of Wang, Ichimura and Gambino teaches the integrated circuit device of claim 1 as set forth in the obviousness rejection. Wang further teaches the integrated circuit device of Claim 1, wherein the thickness of the cup-shaped anti-fuse insulator is in the range of 50-175 Å (paragraph [0048], rows 11-14).
Regarding claim 3, the combination of Wang, Ichimura and Gambino teaches the integrated circuit device of claim 1 as set forth in the obviousness rejection. Wang further teaches the integrated circuit device of Claim 1, wherein the thickness of the cup-shaped anti-fuse insulator is in the range of 75-125 Å (paragraph [0048], rows 11-14).
Regarding claim 4, the combination of Wang, Ichimura and Gambino teaches the integrated circuit device of claim 1 as set forth in the obviousness rejection. Wang further teaches the integrated circuit device of Claim 1, wherein the anti-fuse device has a breakdown voltage below 15V (paragraph [0032], rows 11-12).
Regarding claim 5, the combination of Wang, Ichimura and Gambino teaches the integrated circuit device of claim 1 as set forth in the obviousness rejection. Wang further teaches the integrated circuit device of Claim 1, wherein the anti-fuse device has a breakdown voltage below 7V (paragraph [0032], rows 11-12).
Regarding claim 6, the combination of Wang, Ichimura and Gambino teaches the integrated circuit device of claim 1 as set forth in the obviousness rejection. Wang further teaches the integrated circuit device of Claim 1, wherein the cup-shaped anti-fuse insulator comprises silicon oxide (SiO2), oxide-nitride-oxide (ONO), nitride-oxide- nitride (NON), or aluminum oxide (A1203) (paragraph [0030], rows 11-12).
Regarding claim 7, the combination of Wang, Ichimura and Gambino teaches the integrated circuit device of claim 1 as set forth in the obviousness rejection. Wang further teaches the integrated circuit device of Claim 1, comprising: a bottom anti-fuse electrode contact formed in a lower metal interconnect layer wherein the bottom anti-fuse electrode contact is electrically connected to the cup-shaped bottom anti-fuse electrode (see Fig.15 annotated below), wherein the top anti-fuse electrode contact is formed in an upper metal interconnect layer (see Fig.15 annotated below).
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Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Gambino, in view of Ichimura.
Regarding claim 12, Gambino teaches the integrated circuit of claim 9 as set forth in the anticipation rejection. Gambino does not teach the integrated circuit device of Claim 9, wherein the anti-fuse device has a breakdown voltage below 15V. Ichimura teaches wherein the anti-fuse device has a breakdown voltage below 15V (paragraph [0071], row 3-9, breakdown voltage is 2.9V). The claimed range, below 15V, overlaps the range disclosed by the prior art, therefore, a prima facie case of obviousness exists (MPEP 2144.05). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Ichimura and disclose the anti-fuse device has a breakdown voltage below 15V. As disclosed by Ichimura, by applying a voltage below 15V, such as for instance a driving voltage for a logic transistor used in an I/O interface, the dielectric breakdown can occur and a low voltage programmable semiconductor device can be obtained (paragraph [0071], rows 7-10).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Gambino, in view of Wang and in view of Ichimura.
Regarding claim 15, Gambino teaches the integrated circuit of claim 9 as set forth in the anticipation rejection. Gambino does not teach the integrated circuit device of Claim 9, comprising a transistor including a doped source region and a doped drain region; wherein the cup-shaped bottom anti-fuse electrode is electrically connected to a silicide region formed on the source region or a silicide region formed on the drain region of the transistor.
Wang teaches the integrated circuit comprising a transistor including a doped source region and a doped drain region (Fig.18, transistor element #162, has a source and drain, paragraph [0054], rows 1-4); wherein the cup-shaped bottom anti-fuse electrode is electrically connected drain region (Fig.18, bottom electrodes of anti-fuses elements #160 are connected to the drain region, paragraph [0054], rows 1-4). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Wang and disclose wherein the cup-shaped bottom anti-fuse electrode is electrically connected to a region formed on the source region or a region formed on the drain region of the transistor. As disclosed by Wang, this allows the anti-fuse to operate as a one-time programable anti-fuse capable of being operated under two voltages for read and write operations (paragraph [0049] - [0051]).
The combination of Gambino and Wang does not teach the integrated circuit comprising the bottom anti-fuse electrode is electrically connected to a silicide region formed on the source region or a silicide region formed on the drain region of the transistor. Ichimura teaches the bottom anti-fuse electrode is electrically connected to a silicide region formed on the source region or a silicide region formed on the drain region of the transistor (Fig.1, bottom electrode, element #42 is connected to source/drain regions, element #16, paragraph [0045], rows 1-4, and silicide layers exist on the source and drain regions, paragraph [0044], rows 14-15). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Ichimura and disclose the integrated circuit comprising the bottom anti-fuse electrode is electrically connected to a silicide region formed on the source region or a silicide region formed on the drain region of the transistors. The silicide layer helps reduce the contact resistance between the source/drain region and the bottom anti-fuse electrode.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Gambino in view of Peter S. Kirlin et al. (United States Patent Number, US 5,976,928), hereinafter referenced as Kirlin.
Regarding claim 20, Gambino teaches the method of claim 16 as set forth in the anticipation rejection. Gambino further teaches the method of Claim 16, comprising: depositing an upper dielectric layer over a planarized upper surface defined by the planarization process (Fig.27, element #309), the upper dielectric layer extending over a vertically-extending sidewall of the cup-shaped bottom anti-fuse electrode, the vertically-extending anti-fuse insulator sidewall, and the top anti-fuse electrode; etching the upper dielectric layer to form a top anti-fuse electrode contact opening exposing an upper surface of the top anti-fuse electrode, and filling the top anti-fuse electrode contact opening to form the top anti-fuse electrode contact on the planarized top surface of the top anti-fuse electrode (Fig.27 and 28).
Gambino does not teach a dielectric barrier layer extending over a vertically-extending sidewall of the cup-shaped bottom anti-fuse electrode, the vertically-extending anti-fuse insulator sidewall and the top anti-fuse electrode, etching the dielectric barrier to form a top anti-fuse electrode contact opening exposing an upper surface of the top anti-fuse electrode, wherein the dielectric barrier layer acts as an etch stop.
Kirlin teaches depositing a dielectric barrier layer over a planarized upper surface defined by the planarization process (Fig.2E, element #112, column 13, rows 5-6 is deposited over the planarized surface, top surface showed in Fig.2D, column 12, rows 61-62), the dielectric barrier layer extending over a vertically-extending sidewall of the cup-shaped bottom anti-fuse electrode (Fig.2E, barrier layer, element #112 extends over vertically extending sidewalls of the bottom electrode, formed by elements #104 and #106, column 12, rows 35-27), the vertically-extending anti-fuse insulator sidewall (Fig.2E, barrier layer, element #112 extends over vertically extending sidewalls of the insulator, element #108, column 12, rows 37 and 46-54), and the top electrode (Fig.2E, barrier layer, element #112 extends over vertically extending sidewalls of the top electrode, element #110, column 12, row 37-38); depositing an upper dielectric layer over the dielectric barrier layer (Fig.2E, element #114, column 13, rows 5-7); etching the upper dielectric layer and the dielectric barrier (column 13, rows 9-11) to form a top anti-fuse electrode contact opening exposing an upper surface of the top anti-fuse electrode (Fig.2F, column 13, rows 9-11) wherein the dielectric barrier layer acts as an etch stop (the barrier layer, element #112, can be Si3N4 and therefore acts as an etch stop for the upper dielectric layer, element #114 which can be SiO2, column 11, rows 57-65) and filling the top anti-fuse electrode contact opening (Fig.2F, the opening is filled) to form a top electrode contact on the planarized top surface of the top anti-fuse electrode (Fig.2F, conductive elements #116 forms a top electrode contact on the planarized top surface of element #110). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Kirlin and disclose the method comprising: depositing a dielectric barrier layer over a planarized upper surface defined by the planarization process, the dielectric barrier layer extending over a vertically-extending sidewall of the cup-shaped bottom anti-fuse electrode, the vertically-extending anti-fuse insulator sidewall, and the top anti-fuse electrode; depositing an upper dielectric layer over the dielectric barrier layer; etching the upper dielectric layer and the dielectric barrier to form a top anti-fuse electrode contact opening exposing an upper surface of the top anti-fuse electrode, wherein the dielectric barrier layer acts as an etch stop; and filling the top anti-fuse electrode contact opening to form the top anti-fuse electrode contact on the planarized top surface of the top anti-fuse electrode. As disclosed by Kirlin, this method does not require dry etching steps which may result in unwanted structures at the edges of electrodes (column 1, rows 22-26), and is cost effective (column 6, rows 55-56).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Wang in View of Ichimura, Gambino in view of Tsai (United States Patent Number, US 6,232197 B1), hereinafter referenced as Tsai and in view of Chang et al., (United States Patent Application Publication Number, US 2021/0391342 A1), hereinafter referenced as Chang.
Regarding claim 23, the combination of Wang, Ichimura and Gambino teaches the integrated circuit device of claim 1 as set forth in the obviousness rejection. Wang teaches the integrated circuit device of Claim 1, wherein the anti-fuse device is formed between Metal 1 and Metal 2 interconnect layers (Fig.15). Wang teaches anti-fuse device is formed between two metal interconnect layers (all elements are formed inside dielectric layer #307). While the two metal layers can be Metal 0 and Metal 1, Wang does not specify position of the metal layers.
The combination of Wang, Ichimura and Gambino does not teach the integrated circuit device of Claim 1, wherein the anti-fuse device is formed below a Metal-1 metal interconnect layer. Tsai teaches the integrated circuit device of Claim 1, wherein the anti-fuse device is formed below a Metal-1 metal interconnect layer (Fig.14E, elements #120, #128, #121, #122 that form the anti-fuse (a capacitor can act as an anti-fuse), are formed inside dielectric layer #130 above Metal 0, (element #120 is on the same metal level as the gate, which is Metal 0)). Chang also teaches wherein the anti-fuse device is formed below a Metal-1 metal interconnect layer (Fig.2D, elements #44, 60 and 74 are below Metal 1, gate element #52 is Metal 0). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Tsai Chang and disclose wherein the anti-fuse device is formed below a Metal-1 metal interconnect layer. This can help reduce the number of metal layers required to manufacture the device and therefore reduce the number of process steps and costs.
Response to Arguments
Applicant’s arguments filed on 03/02/2026 have been fully considered but they
are not persuasive. Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Gonzalez at al., (United States Patent Application Publication Number US 5,150,276 A) teaches an anti-fuse (a capacitor can act as an anti-fuse) formed below Metal 1 and in contact with the source/drain of a transistor (Fig.5B).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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