DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 10, 11, 13, and 20 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Bartley et al. (US 2012/0007229).
With regard to claim 1, Bartley teaches, in Fig 7, a chip (200), wherein the chip comprises a housing (250, 2502, 210), a plurality of silicon wafers (lower instances of 231, not including the top instance in the figure), and a plurality of thermal pads (220), wherein the plurality of silicon wafers and the plurality of thermal pads are mounted in the housing in a stacked manner such that at least one thermal pad is between each of the plurality of silicon wafers (see figure); and a first thermal pad (lower instance of 220 in the figure) is mounted between two adjacent silicon wafers, and an edge of the first thermal pad extends from a gap between the two adjacent silicon wafers (see figure), wherein at least one thermally conductive layer (232, 240) connects two adjacent thermal pads, and at least one thermally conductive layer (2501, 240) connects an uppermost thermal pad in the housing and an upper cover of the housing.
With regard to claim 3, Bartley teaches, in Fig 7, that each thermal pad is connected to the upper cover (250) of the housing by using a thermal conductor (240, 2501).
With regard to claim 10, Bartley teaches, in Fig 7, that a size of each thermal pad is greater than a size of each silicon wafer (horizontally in the figure).
With regard to claim 11, Bartley teaches, in Fig 7, an electronic device comprising at least one chip (200), wherein the at least one chip comprises a housing (250, 2502, 210), a plurality of silicon wafers (lower instances of 231, not including the top instance in the figure), and a plurality of thermal pads (220), wherein the plurality of silicon wafers and the plurality of thermal pads are mounted in the housing in a stacked manner such that at least one thermal pad is between each of the plurality of silicon wafers (see figure); and a first thermal pad (lower instance of 220 in the figure) is mounted between two adjacent silicon wafers, and an edge of the first thermal pad extends from a gap between the two adjacent silicon wafers (see figure), wherein at least one thermally conductive layer (232, 240) connects two adjacent thermal pads, and at least one thermally conductive layer (2501, 240) connects an uppermost thermal pad in the housing and an upper cover of the housing.
With regard to claim 13, Bartley teaches, in Fig 7, that each thermal pad is connected to the upper cover (250) of the housing by using a thermal conductor (240, 2501).
With regard to claim 20, Bartley teaches, in Fig 7, that a size of each thermal pad is greater than a size of each silicon wafer (horizontally in the figure).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6, 8, 9, 16, 18, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bartley et al. (US 2012/0007229) in view of Wolter et al. (US 2008/0042261).
With regard to claim 6, Bartley teaches most of the limitations of this claim, as set forth above with regard to claim 1.
Bartley does not explicitly teach that each thermal pad is an insulating thermal pad.
Wolter teaches that each thermal pad (520) is an insulating thermal pad ([0089]) to, “enable the selective cooling of integrated circuits within the die stack assembly without straining or burdening the thermal dissipation of the above lying integrated circuit,” ([0091]).
Therefore, it would have been obvious to the ordinary artisan at the time of filing to combine the chip of Bartley with the thermal pad of Wolter to enable the selective cooling of integrated circuits within the die stack assembly without straining or burdening the thermal dissipation of the above lying integrated circuit.
With regard to claim 8, Bartley teaches most of the limitations of this claim, as set forth above with regard to claim 1.
Bartley does not explicitly teach that the upper cover of the housing and the plurality of thermal pads are made of a same material.
Wolter teaches that the upper cover of the housing (590) and the plurality of thermal pads (520) are made of a same material ([0064], [0089]-[0090]), to, “enable the selective cooling of integrated circuits within the die stack assembly without straining or burdening the thermal dissipation of the above lying integrated circuit,” ([0091]).
Therefore, it would have been obvious to the ordinary artisan at the time of filing to combine the chip of Bartley with the materials of Wolter to enable the selective cooling of integrated circuits within the die stack assembly without straining or burdening the thermal dissipation of the above lying integrated circuit.
With regard to claim 9, Bartley teaches most of the limitations of this claim, as set forth above with regard to claim 1.
Bartley does not explicitly teach that the plurality of thermal pads comprise one or more of a single crystal diamond film, a polycrystalline diamond film, or a boron nitride film.
Wolter teaches that the plurality of thermal pads comprise one or more of a single crystal diamond film, a polycrystalline diamond film, or a boron nitride film ([0089]) to, “enable the selective cooling of integrated circuits within the die stack assembly without straining or burdening the thermal dissipation of the above lying integrated circuit,” ([0091]).
Therefore, it would have been obvious to the ordinary artisan at the time of filing to combine the chip of Bartley with the thermal pad of Wolter to enable the selective cooling of integrated circuits within the die stack assembly without straining or burdening the thermal dissipation of the above lying integrated circuit.
With regard to claim 16, Bartley teaches most of the limitations of this claim, as set forth above with regard to claim 11.
Bartley does not explicitly teach that each thermal pad is an insulating thermal pad.
Wolter teaches that each thermal pad (520) is an insulating thermal pad ([0089]) to, “enable the selective cooling of integrated circuits within the die stack assembly without straining or burdening the thermal dissipation of the above lying integrated circuit,” ([0091]).
Therefore, it would have been obvious to the ordinary artisan at the time of filing to combine the device of Bartley with the thermal pad of Wolter to enable the selective cooling of integrated circuits within the die stack assembly without straining or burdening the thermal dissipation of the above lying integrated circuit.
With regard to claim 18, Bartley teaches most of the limitations of this claim, as set forth above with regard to claim 11.
Bartley does not explicitly teach that the upper cover of the housing and the plurality of thermal pads are made of a same material.
Wolter teaches that the upper cover of the housing (590) and the plurality of thermal pads (520) are made of a same material ([0064], [0089]-[0090]), to, “enable the selective cooling of integrated circuits within the die stack assembly without straining or burdening the thermal dissipation of the above lying integrated circuit,” ([0091]).
Therefore, it would have been obvious to the ordinary artisan at the time of filing to combine the device of Bartley with the materials of Wolter to enable the selective cooling of integrated circuits within the die stack assembly without straining or burdening the thermal dissipation of the above lying integrated circuit.
With regard to claim 19, Bartley teaches most of the limitations of this claim, as set forth above with regard to claim 11.
Bartley does not explicitly teach that the plurality of thermal pads comprise one or more of a single crystal diamond film, a polycrystalline diamond film, or a boron nitride film.
Wolter teaches that the plurality of thermal pads comprise one or more of a single crystal diamond film, a polycrystalline diamond film, or a boron nitride film ([0089]) to, “enable the selective cooling of integrated circuits within the die stack assembly without straining or burdening the thermal dissipation of the above lying integrated circuit,” ([0091]).
Therefore, it would have been obvious to the ordinary artisan at the time of filing to combine the device of Bartley with the thermal pad of Wolter to enable the selective cooling of integrated circuits within the die stack assembly without straining or burdening the thermal dissipation of the above lying integrated circuit.
Claim(s) 7 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bartley et al. (US 2012/0007229) in view of Li et al. (CN 206451703, hereinafter all citations are made to the English translation of record).
With regard to claim 7, Bartley teaches most of the limitations of this claim, as set forth above with regard to claim 1.
Bartley does not explicitly teach that the two adjacent silicon wafers are connected by using a copper pillar, and the first thermal pad is provided with a through hole configured to avoid the copper pillar.
Li teaches, in Fig 1, that the two adjacent silicon wafers (adjacent instances of 1) are connected by using a copper pillar (7), and the first thermal pad (3) is provided with a through hole (5) configured to avoid the copper pillar to, “reduce the process complexity and increase the product yield level, reduces the technical process, improve the production efficiency, it can really realize the batch production by laser through-hole mode, reduce dosage of chemical process control process, accelerates product procedure time then using ultraviolet laser,” (page 3, paragraph 5-6).
Therefore, it would have been obvious to the ordinary artisan at the time of filing to combine the chip of Bartley with the connections of Li to reduce the process complexity, increase the product yield level, reduce the technical process, and improve the production efficiency.
With regard to claim 17, Bartley teaches most of the limitations of this claim, as set forth above with regard to claim 11.
Bartley does not explicitly teach that the two adjacent silicon wafers are connected by using a copper pillar, and the first thermal pad is provided with a through hole configured to avoid the copper pillar.
Li teaches, in Fig 1, that the two adjacent silicon wafers (adjacent instances of 1) are connected by using a copper pillar (7), and the first thermal pad (3) is provided with a through hole (5) configured to avoid the copper pillar to, “reduce the process complexity and increase the product yield level, reduces the technical process, improve the production efficiency, it can really realize the batch production by laser through-hole mode, reduce dosage of chemical process control process, accelerates product procedure time then using ultraviolet laser,” (page 3, paragraph 5-6).
Therefore, it would have been obvious to the ordinary artisan at the time of filing to combine the device of Bartley with the connections of Li to reduce the process complexity, increase the product yield level, reduce the technical process, and improve the production efficiency.
Response to Arguments
Applicant's arguments filed 5/21/2025 have been fully considered but they are not persuasive.
The Applicants argue:
Bartley does not teach or suggest that the plurality of silicon wafers and the plurality of thermal pads are mounted in the housing in a stacked manner such that at least one thermal pad is between each of the plurality of silicon wafers.
To the contrary, as shown in Figs. 4-7 of Bartley, stacks of silicon wafers 231 are provided in each instance without at least one thermal plate 220 therebetween. For example, Fig. 4 shows at least three components 231 stacked with no thermal pad therebetween. Even alternative embodiments such as those shown in Fig. 7, which include additional thermal plates 220, do not teach or suggest that at least one of these thermal plates is provided between each of the components 231.
The Examiner responds:
As set forth in the rejection above, a subset of the silicon wafers 231 of Bartley can be considered to meet the claimed limitation of “a plurality of silicon wafers”. Thus Bartley meets the claim.
The Applicants argue:
claims 1 and 11 further require at least one thermally conductive layer connects two adjacent thermal pads, and at least one thermally conductive layer connects an uppermost thermal pad in the housing and an upper cover of the housing. On page 5 of the outstanding Action, the Office appears to cite adhesive 232 and Thermal Interface Material (TIM) 240 as an alleged teachings of these features. Notably though, Bartley merely shows adhesive 232 between adjacent components 231, or between a component 231 and a thermal plate 220. However, as shown in Fig. 7, which is the only embodiment shown with multiple thermal plates 220, there is no thermally conductive layer provided in the space between thermal plates 220 to connect them.
The Examiner responds:
The term “connect” is defined in the Oxford English Dictionary as “To associate in occurrence or action. Chiefly passive, To be in necessary or natural association; to have practical relations, have to do with” (https://www.oed.com/dictionary/connect_v?tab=meaning_and_use#8556342, accessed on 2/21/2026). As such, the claim does not require the claimed thermally conductive layers to be in direct contact with both of the two adjacent thermal pads or uppermost thermal pad and the housing. The cited elements of 232, 2501, and 240 meet the definition of the term “connects” as applied within the claim, thus meeting the claim.
All other arguments have been fully addressed in prior Office Actions or in the rejections set forth above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/RAJ R GUPTA/Primary Examiner, Art Unit 2893