DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Claims 1, 11, and 12 have been amended. Claims 7-9 were previously cancelled. Claims 6 and 13-20 were previously withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-5, 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Han et al (US 20210202371 A1, hereinafter “Han”) in view of Iwata et al (US 20190296012 A1, hereinafter “Iwata”).
Regarding Claim 1 – Han discloses a semiconductor device, comprising: a substrate (100 in Han Fig. 4C and Han [0021]); a peripheral word line disposed on the substrate (PTR2 transistors interpreted as word lines disposed on the substrate, Han [0050]); a lower dielectric pattern disposed on the substrate and covering the peripheral word line (considered as the combination of layers 193 and 195 in Han Fig. 4C and described in [0051]), the lower dielectric pattern including a first part that covers a lateral surface of the peripheral word line (layer 193 as in Han [0051] covers the lateral surface as shown in Fig. 4C) and a second part that covers a top surface of the peripheral word line (layer 195 as in Han [0051]) and a material of each of the first part and the second part of the lower dielectric pattern including the same material, the same material being silicon oxide (Layers 193 and 195 may both include silicon oxide [0044]); a contact plug disposed on one side of the peripheral word line (protrusion CLp considered to be a contact plug, Han [0051]), the contact plug penetrating the first part and the second part of the lower dielectric pattern (CLp fills recess RC in layers 193 and 195 to contact substrate 100, as in Han [0051] and Fig. 4C); and a filling pattern in contact with the second part of the lower dielectric pattern (Separation pattern 350 considered to be a filling pattern, Han [0053]), the filling pattern penetrating at least a portion of the second part (“...350 may be positioned at a level that is lower than a topmost surface of the second interlayer dielectric layer 195”, Han [0053], shown to penetrate layer 195 in Han Fig. 4C), wherein a material of the filling pattern is silicon nitride (350 includes layer 353, which may be silicon nitride, [0035]), wherein the filling pattern contacts the lower dielectric pattern (350 in contact with 195, as in Fig. 4C), wherein the contact plug includes: a contact pad disposed on a top surface of the lower dielectric pattern (Conductive lines CL considered to be contact pads, Han [0051]); and a through plug that penetrates the first part and the second part of the lower dielectric pattern in a first direction perpendicular to a top surface of the substrate (CLp fills recess RC in layers 193 and 195 to contact substrate 100, as in Han [0051] and Fig. 4C), the through plug being connected to the substrate (as shown in Han Fig. 4C and described in Han [0051]), wherein the filling pattern surrounds a lateral surface of the contact pad (Separation pattern 350 may surround conductive lines CL as in Han [0053]), wherein the peripheral word line includes: a metal-containing pattern (170 [0030]) and a first lower capping pattern (191 [0050]) that are sequentially stacked to form a stacked gate structure on the substrate (Shown in Fig. 4C); a spacer on a sidewall of the stacked gate structure (PSP2 [0050]).
Han fails to disclose a second lower capping pattern covering the spacer and the stacked gate structure, wherein the second part of the lower dielectric pattern is in contact with a top surface of the second lower capping pattern, wherein the second lower capping pattern is in contact with the first lower capping pattern and the spacer.
However, Iwata discloses a second lower capping pattern (764 [0064]) covering the spacer (756 [0054]) and the stacked gate structure (Combination of 758, 754, 752, and 750, Fig. 12), wherein the second part of the lower dielectric pattern is in contact with a top surface of the second lower capping pattern (65 contacting 764, Fig. 12), wherein the second lower capping pattern is in contact with the first lower capping pattern and the spacer (Liners 761 and 762 are optional [0055], putting 764 directly in contact with first lower capping pattern 758 and spacer 756, Iwata Fig. 12).
Iwata is similar to Han in disclosing a planar gate MOSFET structure with vias extending through a dual-layer dielectric. Iwata teaches using a second capping layer over the gate spacers and stacked gate structure to use it as a polish or etch stop during planarization (Iwata [166]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Han and Iwata to use a second capping layer to have the benefit of a polish or etch stop.
PNG
media_image1.png
520
681
media_image1.png
Greyscale
PNG
media_image2.png
500
721
media_image2.png
Greyscale
Regarding Claim 2 – Han modified by Iwata discloses all the limitations of claim 1.
The combination of Han and Iwata further discloses the first part and the second part of the lower dielectric pattern are connected without a boundary therebetween (Layers 193 and 195 in direct contact, as seen in Han Fig. 4C and described in Han [0051]).
Regarding Claim 4 – Han modified by Iwata discloses all the limitations of claim 1.
The combination of Han and Iwata further discloses the second part of the lower dielectric pattern is between a bottom surface of the contact pad and the top surface of the peripheral word line (Layer 195 extends from the bottom of conductive lines CL (310) to the top of layer 191 on top of the word line gate stack as in Han Fig. 4C and described in Han [0051] and [0052]).
Regarding Claim 5 – Han modified by Iwata discloses all the limitations of claim 1.
The combination of Han and Iwata further discloses further comprising a diffusion stop pattern that covers a bottom surface of the contact pad (considered as barrier pattern 310 in Han [0052]) wherein the diffusion stop pattern is in contact with a top surface of the second part of the lower dielectric pattern (310 covers a top surface of the second interlayer dielectric 195, as in Han [0052]).
Regarding Claim 10 – Han modified by Iwata discloses all the limitations of claim 1.
The combination of Han and Iwata further discloses the lower dielectric pattern extends from a bottom surface of the contact pad to a lower portion of the through plug (Recess RC filled by protrusion CLp penetrates both layers 193 and 195 as in Han [0051]).
Regarding Claim 11 – Han modified by Iwata discloses all the limitations of claim 1.
The combination of Han and Iwata further discloses the through plug has widths at upper portion and a lower portions located at different heights from each other, wherein the width at the upper portion is the same as or greater than the width at the lower portion (Han Fig. 4C shows the recesses RC are tapered such that they are wider at the top than at the bottom).
Regarding Claim 12 – Han modified by Iwata discloses all the limitations of claim 1.
The combination of Han and Iwata further discloses the substrate includes a cell region and peripheral region (as in Han [0007]), wherein the peripheral word line (interpreted as transistor PTR2 in Han Fig. 4C and Han [0050]), the lower dielectric pattern (Layers 193 and 195 in Han [0051]), the contact plug (Metal protrusion CLp in Han [0051]), and the filling pattern (Separation pattern 350 in Han [0051]) are disposed on the peripheral region (as explained in Han [0050]), wherein the semiconductor device further comprises: bit lines that extend in a second direction on the cell region (As in Han [0009]), the second direction being parallel to the top surface of the substrate (As explained in Han [0009]); and an upper cell capping pattern that is disposed on each of the bit lines and extends in the second direction along a corresponding bit line (Considered as layer 190 in Han [0030]), wherein the second part of the lower dielectric pattern includes the material whose dielectric constant is less than a dielectric constant of the upper cell capping pattern (Layer 195 may be silicon oxide as in Han [0044], and layer 190 may be silicon nitride as in Han [0030], with silicon nitride having higher dielectric constant than silicon oxide).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Han et al (US 20210202371 A1, hereinafter “Han”), in view of Iwata et al (US 20190296012 A1, hereinafter “Iwata”), and further in view of Ryu et al (US 20140131786 A1, hereinafter “Ryu”).
Regarding Claim 3 – Han modified by Iwata discloses all the limitations of claim 1.
The combination of Han and Iwata fails to disclose the second part of the lower dielectric pattern includes two or more materials.
However, Ryu discloses the second part of the lower dielectric pattern includes two or more materials (Layer 145 is considered to constitute the second part of the lower dielectric pattern as shown in annotated Ryu Fig. 4B, and can comprise silicon nitride and silicon oxynitride as in Ryu [0086]).
Han and Ryu both relate to peripheral transistor construction for memory devices. Ryu proposes multiple secondary lower dielectric layers as part of the preparation for depositing interconnect lines to enable etch selectivity over the planarized interlayer insulating layer 140 (Ryu [0085]). Therefore, it would have been obvious prior to the effective filing date of the instant application to consider using multiple materials to obtain the predictable result of etch selectivity with respect to the first part of the lower dielectric layer.
PNG
media_image3.png
467
717
media_image3.png
Greyscale
Response to Arguments
Applicant's arguments filed 29 December 2025 have been fully considered but they are not persuasive.
Applicant’s Argument – The combination of Han and Iwata does not disclose “...the second lower capping pattern is in contact with the first lower capping pattern and the spacer.” More specifically, Iwata’s layers 763 and 764 are either formed together or left out together, therefore layer 764 cannot contact the spacer or peripheral capping pattern due to the intervening layer 763.
Regarding Applicant’s Argument – If direct contact of the second lower capping pattern (764) with the first lower capping pattern (758) and the spacer (756) is considered, it is clear that 764 directly contacting 758 and 756 is within the presented embodiment taught by Iwata, as the leftmost transistor in Fig. 12 omits layer 763, and layers 761 and 762 are optional [0055]. Since intervening layers 761, 762, and 763 are not required, layer 764 can directly contact 756 and 758 as in the claimed invention. Therefore, not only is this scenario within the possible embodiments of the prior art, it is directly substantiated by Iwata.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 7:30a-5p Eastern, alternating Fridays out of office.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898