DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This is re sponse to Application 17/863,500 filed on 07/13/2022. Claims 1- 25 are pending in the office action. Claim Objections Claim s 6, 12, and 24 are objected to because of the following informalities: As per claim 6: line 2, replaces “ anticommuntation ” with -- anticommutation --. As per claim 12: recited “sets of third quantum gate” should be considered depending on claim 11, instead of claim 1. As per claim 24: line 4, replaces “ anticommuntation ” with -- anticommutation -- . Appropriate correction is required. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer . Claim s 1-3, 14-15, 21-23, and 25 are rejected on the ground of nonstatutory double patenting a s being unpatentable over claim s 1-25 of U.S. Patent No. 12,505,370 . Although the claims at issue are not identical, they are not patentably distinct from each other becaus e both claimed inventions discloses similar subject matter . However, that the current pending application is a broader scope than the U.S. Pat. 12,505,370. It would obvious to one of ordinary skill in the art at the time of the effective filling date of claimed invention using ‘370 to practice as the current pending claimed invention will achieve similar result without undue experiment (see analysis as following) . As per claim 1: an apparatus (‘370, claim 1, col. 87, l. 16, a system) comprising: a controller configured to generate command signals (‘370, claim 1, col. 87, l. 1 7 , a system) ; quantum hardware including at least a plurality of qubits (‘370, claim 1, col. 87, l. 1 8 ) ; and an interface connected to the controller and the quantum hardware, the interface being configured to control the quantum hardware based on the command signals to implement a quantum circuit (‘370, claim 1, col. 87, ll. 22-25) configured to simulate a boundary operator that creates a mapping of boundaries of a given graph having at least nodes and edges, the quantum circuit having linear depth relative to number of nodes in the given graph (‘370, claim 1, col. 87, l l . 25-30 ) . As per claim 2 : The apparatus of claim 1, wherein number of quantum gates in the quantum circuit has a linear relationship with the number of vertices in the given graph (‘370, claim 2 , col. 87, l l . 42-44 ) . As per claim 3 : The apparatus of claim 1, wherein the boundary operator is defined as a sum of fermionic creation and annihilation operators (‘370, claim 3 , col. 87, l l . 45-48 ) . As per claim 14: a method (‘370, claim 15 , col. 8 9 , l . 21 ) comprising: generating, by a controller of a quantum system, command signals (‘370, claim 15 , col. 8 9 , l l. 25-26 ) ; converting, by an interface of the quantum system, the command signals into quantum operations (‘370, claim 15 , col. 8 9 , l l. 27-29 ) ; and based on the quantum operations, controlling, by the interface of the quantum system, quantum hardware of the quantum system to construct a quantum circuit including at least Pauli quantum gates, the quantum circuit configured to simulate a boundary operator that creates a mapping of boundaries of a given graph having at least nodes and edges, the quantum circuit having linear depth relative to number of nodes in the given graph (‘370, claim 15, col. 89, ll. 33-39 and claim 16, col. 89, ll. 51-56) . As per claim 15 : The method of claim 14, wherein fermionic creation and annihilation operators are mapped to Pauli spin operators representing the boundary operator (‘370, claim 16, col. 89, ll. 58-62 ) . As per claim 21: a system (‘370, claim 1, col. 87, l. 16) comprising: a first computing device configured to process data encoded in binary bits (it would obvious a classical computing device) ; a second computing device configured to be in communication with the first computing device (it would obvious a quantum computing device) , wherein the second computing device comprises at least: a controller configured to generate command signals (‘370, claim 1, col. 87, l. 17) ; quantum hardware including at least a plurality of qubits (‘370, claim 1, col. 87, l. 18) ; and an interface connected to the controller and the quantum hardware, the interface being configured to control the quantum hardware based on the command signals to implement a quantum circuit configured to simulate a boundary operator that creates a mapping of boundaries of a given graph having at least nodes and edges, the quantum circuit having linear depth relative to number of the nodes in the given graph (‘370, claim 1, col. 87, ll. 22-30) . As per claim 22 : The system of claim 21, wherein number of quantum gates in the quantum circuit has a linear relationship with the number of the nodes in the given graph (‘370, claim 2, col. 87, ll. 42-44) . As per claim 2 3: The system of claim 21, wherein the boundary operator is defined as a sum of fermionic creation and annihilation operators (‘370, claim 3, col. 87, ll. 45-48) . As per claim 25: an apparatus comprising: a controller configured to generate command signals (‘370, claim 25, col. 92, l. 10) ; quantum hardware including at least a plurality of qubits (‘370, claim 25, col. 92, l. 15) ; and an interface connected to the controller and the quantum hardware, the interface being configured to control the quantum hardware based on the command signals to implement a quantum circuit (‘370, claim 25, col. 92, ll. 16-19) configured to simulate a boundary operator that creates a mapping of simplices of orders in a given simplicial complex (‘370, claim 25, col. 92, ll. 25-26) , the quantum circuit having linear depth relative to number of vertices in the given simplicial complex , and number of quantum gates in the quantum circuit has a linear relationship with the number of vertices in the given simplicial complex (‘370, claim 1, col. 87, ll. 20-21 and ll. 25-30) . Prior Arts Das et al., (U.S. Pub. 2021/0042651) . Das discloses an apparatus (‘651, fig. 1-2) comprising: a controller configured to generate command signals (‘651, fig. 1, controller 120 and fig. 2, 218, par. [0054]) ; quantum hardware including at least a plurality of qubits (‘651, fig. 2, array of qubits 214, par. [0054]) ; and an interface connected to the controller and the quantum hardware, the interface being configured to control the quantum hardware based on the command signals to implement a quantum circuit (‘651, fig. 2, interface 230, par. [0054] ). Das also teaches generating a graph having edge represents a data qubit and each vertex represent a parity qubit , and decoding start by growing spanning forest to cover all the erroneous syndrome bit s to form one or more even clusters (‘651, figs. 11-15). Volker W. Thurey , A Boundary Operator for Simplices, arXiv:1109.2161 [math.GT], September 13, 2018, pages 1-33. (Year: 2018) Thurey teaches a boundary operator is constructed by taking the topological boundary of an n-dimensional standard simplex as a linear combination of n+1 simplices of dimension (n-1), (the faces), provided with alternating signs (the abstract , page 2). Allowable Subject Matter Claims 1-25 would be allowable if rewritten or amended to overcome the rejection(s) under Double Patenting rejection, set forth in this Office action. The following is a statement of reasons for the indication of allowable subject matter: the prior art of record does not teach the combination of claim limitations, comprise : As per claims 1, 14, and 21: a quantum circuit configured to simulate a boundary operator that creates a mapping of boundaries of a given graph having at least nodes and edges, the quantum circuit having linear depth relative to number of the nodes in the given graph . As per claim 25: a quantum circuit configured to simulate a boundary operator that creates a mapping of simplices of orders in a given simplicial complex , the quantum circuit having linear depth relative to number of vertices in the given simplicial complex , and number of quantum gates in the quantum circuit has a linear relationship with the number of vertices in the given simplicial complex . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT NGHIA M DOAN whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-5973 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Mon - Fri 7:00 AM - 5:00 PM . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. 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