DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/08/2022 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
Acknowledgment is made of the amendment filed 07/17/2025, in which: claims 1 and 10 are amended; new claim 20 is added; claims 13-14 and 16-19 stand withdrawn; and the rejection of the claims are traversed. Claims 1-12, 15, and 20 are currently pending an Office action on the merits as follows.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US Publication 20210119086) in view of Katsuno et al. (US Publication 20150001561).
Regarding independent claim 1, Wang teaches a flip-chip semiconductor light-emitting element (fig. 4), comprising:
a light-emitting epitaxial layer (102, 103, and 104), comprising:
a first conductive type semiconductor layer (102), an active layer (103), and a second conductive type semiconductor layer (104) sequentially stacked from bottom to top in that order,
wherein the light-emitting epitaxial layer is provided with a mesa, and the first conductive type semiconductor layer forms an upper surface of the mesa (paragraph 0029, “the epitaxial structure may be formed with at least one mesa structure such that a portion of the first semiconductor layer 102 is not covered by the active layer 103 or the second semiconductor layer 104”);
an insulating layer (fig. 4 106 and 109) comprising an insulating reflective layer (109, paragraph 0038), disposed overlying the light-emitting epitaxial layer and covering side walls of the light-emitting epitaxial layer on two sides of the mesa (fig. 4); and
electrode pads (fig. 4 107 and 108), comprising:
a first electrode pad (107) electrically connected to the first conductive type semiconductor layer (paragraph 0036), and a second electrode pad (108) electrically connected to the second conductive type semiconductor layer, wherein the second electrode pad is directly in contact with the second conductive type semiconductor layer (paragraph 0036, “the contact electrode 105 may be formed with a through hole to expose the second-type semiconductor layer 104, and the second electrode 108 may extend into the through hole to contact with the second-type semiconductor layer 104”); and
PNG
media_image1.png
213
326
media_image1.png
Greyscale
wherein the insulating layer is defined with a first through hole (see figure below), the first through hole penetrates through the insulating layer corresponding to the mesa to expose the first conductive type semiconductor layer at the mesa (fig. 4), the first electrode pad is formed in the first through hole (see figure below).
Wang does not teach and a diameter of the first through hole is less than 12 µm.
Katsuno teaches and a diameter of the first through hole is less than 12 µm (paragraph 114, “more favorable for the width of the hole to be, for example, not less than 5 .mu.m and not more than 20 .mu.m” which overlaps with claimed range of less than 12 µm and is thus a prima facie case of obviousness per MPEP 2144.05).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the flip-chip semiconductor light-emitting element of Wang and the diameter of the first through hole of Katsuno in order to increase the surface area of the first light emitting layer, thereby, “the light emitting region can be enlarged; the luminous efficiency increases; and the operating voltage can be reduced” (Katsuno paragraph 0114).
Wang in view of Katsuno does not explicitly teach wherein a thickness of the insulating reflective layer is in a range of 1 µm to 3 µm, however, Wang discloses the interface layer serving as second insulation layer 109 “may have a thickness within a range of 0.2 μm to 1.0 μm” (paragraph 0038).
It would have been obvious to one of ordinary skill in the art before the effective filing date to arrive at a value within the claimed range so as to achieve “the light extraction efficiency of the LED may be improved, and a compressive strain at the cutting region may be reduced, thereby reducing bowing of the LED and improving a quality thereof” (paragraph 0038) and/or because in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists and/or “a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close” per MPEP 2144.05.
Regarding dependent claim 20, Wang in view of Katsuno teaches the flip-chip semiconductor light-emitting element according to claim 1.
Wang in view of Katsuno does not explicitly wherein an overall thickness of the insulating layer is no greater than 3 µm, however, Wang discloses the interface layer serving as second insulation layer 109 “may have a thickness within a range of 0.2 μm to 1.0 μm” (paragraph 0038).
It would have been obvious to one of ordinary skill in the art before the effective filing date to arrive at a value within the claimed range so as to achieve “the light extraction efficiency of the LED may be improved, and a compressive strain at the cutting region may be reduced, thereby reducing bowing of the LED and improving a quality thereof” (paragraph 0038) and/or because in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists and/or “a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close” per MPEP 2144.05.
Claims 2-4, 10, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Katsuno as applied to claim 1 above, and further in view of Chuang et al. (US Publication 20200357955).
Regarding dependent claim 2, Wang in view of Katsuno teaches the flip-chip semiconductor light-emitting element according to claim 1.
Wang in view of Katsuno does not teach wherein the insulating layer further comprises: a first insulating protective layer, disposed between the insulating reflective layer and the second conductive type semiconductor layer.
Chuang teaches wherein the insulating layer (fig. 3 18 and 50) further comprises:
a first insulating protective layer (40), disposed between the insulating reflective layer (44) and the second conductive type semiconductor layer (34).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the flip-chip semiconductor light-emitting element of Wang in view of Katsuno and the first insulating protective layer of Chuang in order to provide a reflective function (Chuang paragraph 0047).
Regarding dependent claim 3, Chuang further teaches the flip-chip semiconductor light-emitting element according to claim 2, wherein the insulating layer further comprises:
a second insulating protective layer (fig. 3 54), disposed overlying the insulating reflective layer (54 disposed overlying insulating reflective layer 44);
PNG
media_image2.png
419
722
media_image2.png
Greyscale
wherein a thickness of the second insulating protective layer is less than a thickness of each of insulating material layers in the insulating reflective layer (see figure below).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the flip-chip semiconductor light-emitting element of Wang in view of Katsuno and the second insulating protective layer of Chuang per the reasons stated above in claim 2.
Regarding dependent claim 4, Chuang further teaches the flip-chip semiconductor light-emitting element according to claim 3,
wherein the second insulating protective layer is one of an aluminum oxide layer, and a silicon oxide layer (paragraph 0047 and 0065, a material of the second insulating protective layer “includes silicon dioxide (SiO.sub.2) or titanium dioxide (TiO.sub.2)”).
Wang in view of Katsuno and Chuang does not explicitly teach the aluminum oxide layer to have a thickness range in a range of 8 nm to 200 nm, and a silicon oxide layer with a thickness in a range of 8 nm to 50 nm, however, Chuang discloses “since the red light emitting diode of the disclosure is provided in a form of a flip-chip light emitting diode, the red light emitting diode may be electrically connected to an external substrate (e.g., an array substrate of a display) in a flip-chip manner through the two electrode pads and may not have to include a substrate and a bonding layer. In this way, arrangement of a wire-bonding region may be omitted, so that a volume of a light emitting diode device (e.g., a light emitting diode display) and a chip thickness may be effectively reduced, favorable applicability is provided, and applications to a micro LED light emitting module may be effectively applied.” (paragraph 0110).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to obtain the claimed thickness ranges of the second insulating protective layer, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
PNG
media_image3.png
279
510
media_image3.png
Greyscale
Regarding dependent claim 10, Wang further teaches the flip-chip semiconductor light-emitting element according to claim 2, wherein the insulating layer is further defined with a second through hole (see figure below), and the second through hole penetrates through the insulating layer corresponding to the second conductive type semiconductor layer to expose the second conductive type semiconductor layer (paragraph 0036, “the contact electrode 105 may be formed with a through hole to expose the second-type semiconductor layer 104, and the second electrode 108 may extend into the through hole to contact with the second-type semiconductor layer 104”); and
wherein the second electrode pad is formed in the second through hole (fig. 4).
Katsuno further teaches and the first through hole is a circular through hole (paragraph 0094, “configuration of the second metal unit 51b is, for example, a rectangle, a polygon, an ellipse (including a circle), a fan-like configuration, or a combination of these shapes.”, and 51b is inside first through hole so shape of first through hole can be configured to be circular per MPEP 2144.04).
Regarding dependent claim 15, Wang further teaches the flip-chip semiconductor light-emitting element according to claim 2,
wherein at least one dimension of the flip-chip semiconductor light-emitting element is no greater than 300 µm (paragraph 0026, “the first surface of the light-transmissive substrate 101 has a length that ranges from 40 μm to 300 μm, such as 100 μm to 300 μm, 100 μm to 200 μm, or even not greater than 100 μm (e.g., 40 μm to 100 μm)”).
Claims 5-9 are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Katsuno and further in view of Chuang as applied to claim 2 above, and further in view of Chen et al. (US Publication 20170141260).
Regarding dependent claim 5, Chuang further teaches the flip-chip semiconductor light-emitting element according to claim 2, wherein the insulating layer further comprises:
PNG
media_image4.png
463
735
media_image4.png
Greyscale
a third insulating protective layer (fig. 3 42), disposed between the first insulating protective layer (40) and the insulating reflective layer (44, see figure below);
wherein the third insulating protective layer is a silicon oxide layer (paragraph 0047);
PNG
media_image5.png
454
735
media_image5.png
Greyscale
wherein a thickness of the first insulating protective layer is less than a thickness of the third insulating protective layer (see figure below).
Wang in view of Katsuno and Chuang does not teach wherein the first insulating protective layer is an aluminum oxide layer.
Chen teaches the first insulating protective layer is an aluminum oxide layer (paragraph 0031, “the first insulating layer 20a is formed of a non-conductive material and comprises organic material, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymers (COC), polymethylmethacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, fluorocarbon polymer, or inorganic material, such as silicone, glass, or dielectric material, such as aluminum oxide (Al.sub.2O.sub.3), silicon nitride (SiN.sub.x), silicon oxide (SiO.sub.x), titanium oxide (TiO.sub.x), or magnesium fluoride (MgF.sub.x)”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the flip-chip semiconductor light-emitting element of Wang in view of Katsuno and Chuang and the material of the first insulating protective layer of Chen in order to protects the sidewall of the semiconductor structure to prevent the active layer from being destroyed (Chen, paragraph 0031).
Regarding dependent claim 6, Chen further teaches the flip-chip semiconductor light-emitting element according to claim 5, wherein the first insulating protective layer is the aluminum oxide layer (paragraph 0031) and the third insulating protective layer is the silicon oxide layer (paragraph 0047).
Wang in view of Katsuno, Chuang, and Chen does not explicitly teach a thickness [of the aluminum oxide layer] in a range of 50nm to 200 nm, and a thickness [of the silicon oxide layer] in a range of 80 nm to 450nm, however, Chuang discloses “since the red light emitting diode of the disclosure is provided in a form of a flip-chip light emitting diode, the red light emitting diode may be electrically connected to an external substrate (e.g., an array substrate of a display) in a flip-chip manner through the two electrode pads and may not have to include a substrate and a bonding layer. In this way, arrangement of a wire-bonding region may be omitted, so that a volume of a light emitting diode device (e.g., a light emitting diode display) and a chip thickness may be effectively reduced, favorable applicability is provided, and applications to a micro LED light emitting module may be effectively applied.” (paragraph 0110).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to obtain the claimed thickness ranges of the first and third insulating protective layers per the reasons stated above in claim 5 and/or since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding dependent claim 7, Wang in view of Katsuno, Chuang and further in view of Chen teaches the flip-chip semiconductor light-emitting element according to claim 6.
PNG
media_image6.png
474
735
media_image6.png
Greyscale
Wang in view of Katsuno, Chuang, and Chen does not explicitly teach wherein a ratio of the thickness of the first insulating protective layer to the thickness of the third insulating protective layer is in a range of 1:3 to 1:5, however, figure 3 of Chuang clearly shows a thickness of the first insulating protective layer to be less than a thickness of the third insulating protective layer (see figure below).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to obtain the claimed thickness ratios per the reasons stated above in claim 5 and/or since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding dependent claim 8, Chuang further teaches the flip-chip semiconductor light-emitting element according to claim 3, wherein the insulating layer further comprises:
a fourth insulating protective layer (fig. 3 52), disposed between the second insulating protective layer (54) and the insulating reflective layer (44).
Wang in view of Katsuno and Chuang does not teach wherein the second insulating protective layer is an aluminum oxide layer with a thickness in a range of 8 nm to 200 nm.
Chen teaches wherein the second insulating protective layer is an aluminum oxide layer (paragraph 0038, “second insulating layer 50a is formed of a non-conductive material comprising organic material, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymers (COC), polymethylmethacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, fluorocarbon polymer, or inorganic material, such as silicone, glass, or dielectric material, such as aluminum oxide (Al.sub.2O.sub.3), silicon nitride (SiN.sub.x), silicon oxide (SiO.sub.x), titanium oxide (TiO.sub.x), or magnesium fluoride (MgF.sub.x)”).
Wang in view of Katsuno, Chuang, and Chen does not explicitly teach a thickness in a range of 8 nm to 200 nm, however, Chuang discloses “since the red light emitting diode of the disclosure is provided in a form of a flip-chip light emitting diode, the red light emitting diode may be electrically connected to an external substrate (e.g., an array substrate of a display) in a flip-chip manner through the two electrode pads and may not have to include a substrate and a bonding layer. In this way, arrangement of a wire-bonding region may be omitted, so that a volume of a light emitting diode device (e.g., a light emitting diode display) and a chip thickness may be effectively reduced, favorable applicability is provided, and applications to a micro LED light emitting module may be effectively applied.” (paragraph 0110).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to obtain the claimed thickness of the second insulating protective layer in order to protect the sidewalls of the semiconductor structure to prevent destruction of the active layer (Chen paragraph 0038) and/or since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding dependent claim 9, Chuang further teaches the flip-chip semiconductor light-emitting element according to claim 8, wherein the fourth insulating protective layer is a silicon oxide layer (paragraph 0047 and 0065).
Wang in view of Katsuno, Chuang, and Chen does not explicitly teach a thickness in a range of 8 nm to 50 nm, however, Chuang discloses “since the red light emitting diode of the disclosure is provided in a form of a flip-chip light emitting diode, the red light emitting diode may be electrically connected to an external substrate (e.g., an array substrate of a display) in a flip-chip manner through the two electrode pads and may not have to include a substrate and a bonding layer. In this way, arrangement of a wire-bonding region may be omitted, so that a volume of a light emitting diode device (e.g., a light emitting diode display) and a chip thickness may be effectively reduced, favorable applicability is provided, and applications to a micro LED light emitting module may be effectively applied.” (paragraph 0110).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to obtain the claimed thickness of the fourth insulating protective layer per the reasons stated above in claim 8 and/or since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Katsuno and Chuang as applied to claim 10 above, and further in view of He et al. (CN Publication 208127232).
Regarding dependent claim 11, Wang in view of Katsuno and Chuang teaches the flip-chip semiconductor light-emitting element according to claim 10.
Wang in view of Katsuno and Chuang does not teach wherein a recess is defined in the first conductive type semiconductor layer at the mesa and below the first through hole in the insulating layer.
He teaches wherein a recess (see figure below) is defined in the first conductive type semiconductor layer at the mesa (see figure below) and below the first through hole (fig. 2 1061) in the insulating layer (106).
PNG
media_image7.png
228
546
media_image7.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the flip-chip semiconductor light-emitting element of Wang in view of Katsuno and Chuang and the first through hole shape of He in order to “improve the packaging thrust level and enhance the reliability” as stated by He.
PNG
media_image8.png
239
428
media_image8.png
Greyscale
Regarding dependent claim 12, He further teaches the flip-chip semiconductor light-emitting element according to claim 11, wherein a width of an upper opening of the recess is less than a width of the mesa (see figure below).
Response to Arguments
Applicant’s arguments with respect to claims 1-12, 15, and 20 have been fully considered but are moot in view of the new grounds of rejection (Amendments).
Applicant’s arguments filed 07/17/2025 have been fully considered but are not persuasive.
Applicant argues on pages 8-10 of the instant Remarks: “Based on the amendments of claim 1, Applicant submits that none of the cited references discloses, teaches, or suggests the following features: A, the second electrode pad is directly in contact with the second conductive type semiconductor layer; and B, a diameter of the first through hole is less than 12 µm. Specifically, regarding the feature A: Wang only mentions that a second electrode 108 is electrically connected to a second-type semiconductor layer 104, and does not disclose a direct contact therebetween. In addition, each of Chuang, Chen and He also does not disclose any details about the direct contact between the second electrode pad and the second conductive type semiconductor layer. That is to say, Wang, Chuang, Chen and He taken alone or in combination fail to disclose, teach or suggest the feature A of the instant application. Moreover, as disclosed in paragraph [0004] of the specification, in the prior art, since a first electrode layer only covers a portion of a first semiconductor layer and a portion of a transparent conductive layer, there is an inclination angle between an edge of the first electrode layer and a surface of the transparent conductive layer; in this case, when an insulating layer is deposited, the insulating layer may have sublayers with a total thickness greater than 3 µm, and thus the existence of the inclination angles will make the insulating layer have corners and protrusions. In addition, when electrode through holes are formed in the insulating layer, there is an inclination angle between a side wall of the insulating layer and an upper surface of the first electrode layer, such as 66.7⁰ as illustrated in FIG. 1B. When electrode pads are formed overlying the first electrode layer, the above corners, protrusions and the inclination angles of the side walls of the electrode through holes will make material coverage of the electrode pad poor, and there will be defects such as fracture or crack, which will reduce the reliability of the device. In view of the above problems, currently amended claim 1 discloses the feature A that the second electrode pad is directly in contact with the second conductive type semiconductor layer, i.e., without the first electrode layer, which avoids the defects like fractures or cracks caused by poor material coverage at the electrodes due to the corners, the protrusions and the inclination angles of the side walls, thereby enhancing the reliability of the flip-chip semiconductor light-emitting element. Therefore, currently amended claim 1 yields unpredictable result. Regarding the feature B: Each of Wang, Chuang, Chen and He does not mention a detailed range of the diameter of the first through hole, let alone "a diameter of the first through hole is less than 12 µm", that is to say, Wang, Chuang, Chen and He taken alone or in combination fail to disclose, teach or suggest the feature B of the instant application. Moreover, referring to paragraph [0039] of the specification of the instant application, owing to a diameter of the first through hole being less than 12 µm (i.e., relatively small first through hole), an area of the mesa occupied by the first through hole can be reduced correspondingly, and an area of the active layer can be increased, therefore, a light-emitting area of the light-emitting element can be increased, which is conducive to improving a light-emitting efficiency of the light-emitting element. In addition, since a current expansion of a P layer in the light-emitting element is much worse than that of an N layer, the smaller the area of the N layer, the larger the area of the P layer, which can balance the current expansion of the P layer and the N layer, so as to improve the ESD capability of the light-emitting element. Therefore, currently amended claim 1 yields unpredictable result. Accordingly, at least based on the above reasons, Applicant submits that currently amended claim 1 of the instant application is allowable over all the cited references. Reconsideration and withdrawal of the rejection and the allowance of currently amended claim 1 are hereby requested. In response to the rejections of claims 2-12 and 15, Applicant submits that claims 2-12 and 15 depend upon now-allowable claim 1 and therefore also are allowable over all the cited references. Reconsideration and withdrawal of the rejections and the allowance of claims 2-12 and 15 in their current forms are hereby requested. Claim 20, as newly added, depends upon now-allowable claim 1 and therefore also is allowable. Further, owing to an overall thickness of the insulating layer no greater than 3 µm, when electrode through holes are formed in the insulating layer, abnormal protrusions will not occur due to the excessive thickness of the insulation protective layer, the electrode through holes have good morphology, and the adhesion of the electrode pads in the electrode through holes and on the insulating protective layer is enhanced, thus the electrode pads will not have defects such as cracks or fractures, thereby the stability and reliability of the device can be enhanced. In addition, the overall thickness of the insulating layer no greater than 3 µm may avoid a too large upper opening of the electrode through hole, thereby avoiding a risk of electric leakage due to the portion of the insulating reflective layer near the side wall of the mesa is thin, and a risk of reduction of luminous area due to the mesa is too large. Therefore, claim 20 yields unpredictable result.”
However, as stated above, Wang does disclose wherein the second electrode pad is directly in contact with the second conductive type semiconductor layer (paragraph 0036, “the contact electrode 105 may be formed with a through hole to expose the second-type semiconductor layer 104, and the second electrode 108 may extend into the through hole to contact with the second-type semiconductor layer 104”) and therefore yields predictable result. Also, Katsuko teaches a diameter of the first through hole is less than 12 µm (paragraph 114, “more favorable for the width of the hole to be, for example, not less than 5 .mu.m and not more than 20 .mu.m” which overlaps with claimed range of less than 12 µm and is thus a prima facie case of obviousness per MPEP 2144.05), and therefore yields predictable result. Wang also discloses the interface layer serving as second insulation layer 109 of the insulation layer to “have a thickness within a range of 0.2 μm to 1.0 μm” (paragraph 0038), which is less than 3 μm and thus the overall thickness of the insulating layer can be no less than 3 μm to achieve “the light extraction efficiency of the LED may be improved, and a compressive strain at the cutting region may be reduced, thereby reducing bowing of the LED and improving a quality thereof” (paragraph 0038) and/or because in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists and/or “a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close” per MPEP 2144.05. Therefore, claim 20 yields predictable result.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GRACE Y CHA whose telephone number is (703)756-5393. The examiner can normally be reached Monday - Thursday 8:00 am - 5:00 pm and every other Friday 8:00 am - 4:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GRACE CHA/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897