DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
The examiner acknowledges amendments to claims 1, 15, and 18 and cancellation of claims 6 and 23 in the applicant’s response dated 19 February 2026. Claims 2, 7, and 10-11 were previously cancelled. Claims 18-20 were previously withdrawn as relating to a non-elected invention. Claims 24-26 have been added.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 1 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "...coupling the interconnect to the second portion of the conductive contact" in the last line. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the above limitation will be considered as “...coupling the interconnect to the conductive contact”.
Claims 3-5, 8-9, 12-17, 21-22, and 24-26 are rejected for their dependency on claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5, 8-9, 12-14, 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Moens et al (US 20160043218 A1, hereinafter “Moens”), in view of Chou et al (US 20210167165 A1, hereinafter “Chou”).
Regarding Claim 1 – Moens discloses a structure comprising: a substrate (12 [0040]); a layer stack (26 minus 12 [0044]) on the substrate, the layer stack including a top surface (Interface of 26 and 104, Fig, 10) and a semiconductor layer at the top surface (24 [0044] and Fig. 10), and the semiconductor layer comprising a III-V compound semiconductor material ([0044]); a first dielectric layer on the layer stack (104 [0053] and Fig. 10); a conductive contact (102 [0051]) extending in a vertical direction fully through the layer stack to the substrate ([0051] and Fig. 10), the conductive contact arranged in the layer stack to separate a first portion of the layer stack (Active Area, annotated Moens Fig. 10) from a second portion of the layer stack (Peripheral Area, annotated Moens Fig. 10); a device structure including a source ohmic contact (52 [0049]) and a drain ohmic contact (54 [0049]), the source ohmic contact and the drain ohmic contact in a contacting relationship with the first portion of the layer stack (24 [0049]), a second dielectric layer (118 [0055] and Fig. 10) on the first dielectric layer, an interconnect (116 [0055] and Fig. 10).
Moens fails to disclose a conductive contact extending fully through the first dielectric layer, the conductive contact including a middle portion in the layer stack and an upper portion in the first dielectric layer, the conductive contact fully surrounding the first portion of the layer stack, and the conductive contact comprising tungsten; a first contact in the second dielectric layer, the first contact coupling the interconnect to the source ohmic contact; and a second contact in the second dielectric layer, the second contact coupling the interconnect to the conductive contact.
However, Chou discloses a conductive contact (20, Chou [0022] and Fig. 3E) extending fully through the first dielectric layer (114, Chou [0032] and Fig. 3E), the conductive contact including a middle portion in the layer stack and an upper portion in the first dielectric layer (20 in both 111 and 114, Chou [0042]), the conductive contact fully surrounding the first portion of the layer stack (Seal region AS surrounds active regions AA, Chou [0021]), and the conductive contact comprising tungsten (Chou [0044]); a first contact (126V, Chou [0046] and Fig. 3E) in the second dielectric layer (124, Chou [0045] and Fig. 3E), the first contact coupling the interconnect (126M, Chou [0046] and Fig. 3E) to the source ohmic contact (116, Chou [0046] and Fig. 3E); and a second contact (129V, Chou [0045] and Fig. 3E) in the second dielectric layer, the second contact coupling the interconnect to the conductive contact (Chou [0047] and Fig. 3E).
Like Moens, Chou describes a compound semiconductor device with an active area bounded by a conductive contact. Chou teaches the conductive contact extends through the first dielectric layer into the layer stack and substrate to prevent moisture from penetrating the active region (Chou [0022]), and surrounds the active area to give the further advantage of preventing cracks from entering the active region (Chou [0020]). Chou further teaches that tungsten may be used for this purpose (Chou [0044]). Yet further, Chou teaches extending the conductive contact into the first dielectric layer for the benefit of preventing moisture ingression (Chou [0053]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Moens and Chou, and use a tungsten conductive contact extending through the first dielectric and compound semiconductor layers to surround the active area, preventing cracks and moisture from entering.
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Regarding Claim 3 – Moens modified by Chou discloses all the limitations of claim 1.
The combination of Moens and Chou further discloses the conductive contact is positioned in a lateral direction between the first portion of the layer stack (Active Area, annotated Moens Fig. 10) and the second portion of the layer stack (Peripheral Area, annotated Moens Fig. 10) as a partition (102 and 46 separate Active and Peripheral Areas, annotated Moens Fig. 10).
Regarding Claim 4 – Moens modified by Chou discloses all the limitations of claim 1.
The combination of Moens and Chou further discloses the device structure is a high-electron-mobility transistor that includes a gate (50, Moens [0049]) on the first portion of the layer stack (on 24, Moens [0049]).
Regarding Claim 5 – Moens modified by Chou discloses all the limitations of claim 1.
The combination of Moens and Chou further discloses the substrate comprises a heavily-doped semiconductor material (“...1×10−3 Ohm-centimeters (Ω-cm) to about 100 Ω-cm.”, Moens [0040]).
Regarding Claim 8 – Moens modified by Chou discloses all the limitations of claim 1.
The combination of Moens and Chou further discloses a trench in the first dielectric layer and the layer stack (201, Chou [0034] and Fig. 3C), the trench having an inner sidewall and an outer sidewall that extend to the substrate (Inner Sidewall and Outer Sidewall in annotated Chou Fig. 3C), and the middle portion and the upper portion of the conductive contact positioned inside the trench (20, Chou [0022] and Fig. 3E); a first dielectric spacer (46A on Active Area sidewall, Moens [0047] and Fig. 10) between the conductive contact and the inner sidewall of the trench (between 102A and 42A, Moens Fig. 10); and a second dielectric spacer (46A on Peripheral Area sidewall, Moens [0047] and Fig. 10) between the conductive contact and the outer sidewall of the trench (between 102A and 42A, Moens Fig. 10).
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Regarding Claim 9 – Moens modified by Chou discloses all the limitations of claim 1.
The combination of Moens and Chou further discloses the conductive contact has an end in direct contact with the substrate (102A contacts 12 at 44A, Moens [0051] and Fig. 10).
Regarding Claim 12 – Moens modified by Chou discloses all the limitations of claim 1.
The combination of Moens and Chou further discloses the conductive contact is formed in a trench penetrating through the layer stack to the substrate (40, Moens [0046]), the trench has an inner sidewall and an outer sidewall (42A, Moens [0046]), and further comprising: a first dielectric spacer between the conductive contact and the inner sidewall of the trench (46A on Active Area sidewall, Moens [0047] and Fig. 10); and a second dielectric spacer between the conductive contact and the outer sidewall of the trench (46A on Peripheral Area sidewall, Moens [0047] and Fig. 10).
Regarding Claim 13 – Moens modified by Chou discloses all the limitations of claim 12.
The combination of Moens and Chou further discloses the conductive contact, the first dielectric spacer, and the second dielectric spacer fully surround the first portion of the layer stack (102A and 46A of Moens contained in the seal region of Chou, AS, which surrounds AA, Chou [0021]).
Regarding Claim 14 – Moens modified by Chou discloses all the limitations of claim 12.
The combination of Moens and Chou further discloses the conductive contact, the first dielectric spacer, and the second dielectric spacer are positioned in a lateral direction between the first portion of the layer stack and the second portion of the layer stack as a partition (102A and 46A separate Active and Peripheral Areas, annotated Moens Fig. 10).
Regarding Claim 21 – Moens modified by Chou discloses all the limitations of claim 8.
The combination of Moens and Chou further discloses the conductive contact has an end in direct contact with the substrate (102A contacts 12 at 44A, Moens [0051] and Fig. 10).
Regarding Claim 22 – Moens modified by Chou discloses all the limitations of claim 9.
The combination of Moens and Chou further discloses the conductive contact is formed in a trench (40, Moens [0046]) penetrating through the layer stack to the substrate, the trench has an inner sidewall and an outer sidewall (both 42A, Moens [0046]), and further comprising: a first dielectric spacer (46A, Moens [0047]) between the conductive contact and the inner sidewall of the trench; and a second dielectric spacer (46A, Moens [0047]) between the conductive contact and the outer sidewall of the trench (between 102A and 42A, Moens Fig. 10).
Claims 15-17 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Moens et al (US 20160043218 A1, hereinafter “Moens”), in view of Chou et al (US 20210167165 A1, hereinafter “Chou”), and further in view of Lin et al (US 20200403090 A1, hereinafter “Lin”).
Regarding Claim 15 – Moens modified by Chou discloses all the limitations of claim 1.
The combination of Moens and Chou fails to expressly disclose an isolation region in the semiconductor layer of the layer stack, wherein the conductive contact penetrates through the isolation region.
However, Lin discloses an isolation region (240, Lin [0018] and Fig. 1B) in the semiconductor layer of the layer stack, wherein the conductive contact penetrates through the isolation region (601/602, Lin [0018] and Fig. 1B).
Lin discloses a similar compound semiconductor device to Moens. Lin teaches an isolation region in the semiconductor layer of the layer stack for the benefit of isolating the two-dimensional electron gas in the active area (Lin [0025]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Moens and Lin to include an isolation region in the semiconductor layer of the layer stack for the benefit of isolating the two-dimensional electron gas in the active area.
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Regarding Claim 16 – Moens modified by Chou and Lin discloses all the limitations of claim 15.
The combination of Moens, Chou, and Lin further discloses the conductive contact and the isolation region fully surround the first portion of the layer stack (240 of Lin defining region 202, Lin [0018] and Figs. 1B and 2A, contained in the seal region of Chou, AS, which surrounds AA, Chou [0021]).
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Regarding Claim 17 – Moens modified by Chou and Lin discloses all the limitations of claim 15.
The combination of Moens, Chou, and Lin further discloses the conductive contact and the isolation region are positioned in a lateral direction between the first portion of the layer stack and the second portion of the layer stack as a partition (102A of Moens and 240 of Lin separate Active and Peripheral Areas, annotated Moens Fig. 10 and Lin Fig. 2A).
Regarding Claim 26 – Moens modified by Chou and Lin discloses all the limitations of claim 1.
The combination of Moens and Chou fails to disclose the interconnect comprises copper or aluminum, and the first contact and the second contact comprise tungsten.
However, Lin discloses the interconnect comprises copper or aluminum, and the first contact and the second contact comprise tungsten (Lin [0031]).
Lin discloses a similar compound semiconductor device to Moens. Lin teaches the contacts and interconnects in the device can be aluminum, copper, or tungsten (Lin [0031]). This is a prima facie case of obviousness, as these materials are known in the semiconductor industry for this purpose. See MPEP 2144.07. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to use aluminum, copper, or tungsten for the interconnects and contacts in a compound semiconductor device.
Claims 24 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Moens et al (US 20160043218 A1, hereinafter “Moens”), in view of Chou et al (US 20210167165 A1, hereinafter “Chou”), and further in view of Lin et al (US 20200403090 A1, hereinafter “Lin”), and further in view of Moens et al (US 20140264453 A1, hereinafter “Moens2”).
Regarding Claim 24 – Moens modified by Chou and Lin discloses all the limitations of claim 15.
The combination of Moens, Chou, and Lin further discloses the conductive contact is formed in a trench penetrating through the layer stack and the isolation region to the substrate (201, Chou [0034] and Fig. 3C), the trench has an inner sidewall and an outer sidewall (Inner Sidewall and Outer Sidewall in annotated Chou Fig. 3C), and further comprising: a first dielectric spacer inside the trench (46A on Active Area sidewall, Moens [0047] and Fig. 10), the first dielectric spacer between the conductive contact and the inner sidewall of the trench (between 102A and 42A, Moens Fig. 10); and a second dielectric spacer inside the trench (46A on Peripheral Area sidewall, Moens [0047] and Fig. 10), the second dielectric spacer between the conductive contact and the outer sidewall of the trench (between 102A and 42A, Moens Fig. 10), wherein the isolation region comprises the III-V compound semiconductor material and nitrogen in the III-V compound semiconductor material (Lin [0026]).
The combination of Moens, Chou, and Lin fails to disclose the first dielectric spacer and the second dielectric spacer comprise silicon dioxide.
However, Moens2 discloses the first dielectric spacer and the second dielectric spacer comprise silicon dioxide (41, Moens [0027] and Fig. 1).
Moens2 discloses an analogous compound semiconductor device to Moens. Moens2 teaches the first dielectric spacer and the second dielectric spacer comprise silicon dioxide for the benefit of increased breakdown voltage (Moens2 [0027]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Moens and Moens2 to use silicon dioxide from the first and second dielectric spacers for the benefit of increased breakdown voltage.
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Regarding Claim 25 – Moens modified by Chou, Lin, and Moens2 discloses all the limitations of claim 24.
The combination of Moens, Chou, Lin, and Moens2 further discloses the III-V compound semiconductor material comprises aluminum gallium nitride (24 is AlGaN, Moens [0044]).
Response to Arguments
Applicant’s arguments have been considered but are moot in view of the new grounds of rejection necessitated by amendment.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON MCDONALD/ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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