DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Regarding the objections to the drawings in the Office Action filed 1 October 2025, Applicant’s amendments in the reply filed 30 December 2025 are acknowledged and overcome the associated objections. As such, the associated objections are withdrawn.
Regarding the objections to the specification in the Office Action filed 1 October 2025, Applicant’s amendments in the reply filed 30 December 2025 are acknowledged. However, not all associated objections are overcome. See Specification section for details.
Regarding the rejections to the claims under 35 U.S.C. 112(b) in the Office Action filed 1 October 2025, Applicant’s amendments in the reply filed 30 December 2025 are acknowledged. However, not all associated rejections are overcome. See Claim Rejections - 35 USC § 112 section for details.
Regarding the rejections to the claims under 35 U.S.C. 102(a)(1), 35 U.S.C. 102(a)(2), and 35 U.S.C. 103 in the Office Action filed 1 October 2025, Applicant’s amendments in the reply filed 30 December 2025 are acknowledged and have been fully considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The disclosure is objected to because of the following informalities:
Regarding ¶ [0024], a layer “1D” is cited and does not appear and/or is not labeled in the accompanying figures.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 9, 10 & 20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention.
Regarding Claim 9,
Lin. 3 recites the list “A12O3, BN, AlN, Si3N4, diamond”. However, it is unclear if this list is closed or open without the presence of “and” or “or”. For prosecution purposes, this list will be interpreted as closed “A12O3, BN, AlN, Si3N4, and diamond”, forming a proper Markush group.
Regarding Claim 10,
This claim depends upon Claim 9.
Regarding Claim 20,
Lin. 1 – 2 recite the limitation “wherein the first potting material forms a glob”. However, the term “glob” is ambiguous, making this limitation indefinite. The language of the claim must clearly and precisely define the metes and bounds of the claimed invention, since patented claims place the public on notice of the scope of the patentee's right to exclude. It is important that a person of ordinary skill in the art be able to interpret the metes and bounds of the claims so as to understand how to avoid infringement of the patent that ultimately issues from this application. For the purposes of examination, this limitation will be interpreted as “wherein the first potting material forms a localized and continuous mass”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 7 – 8, 13 – 14, & 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by HARTUNG (US 20180033711 A1).
Regarding Claim 1,
HARTUNG discloses:
A semiconductor power module (Fig. 3C: 100; Par. 12 & 53), comprising:
an insulating interposer (Fig. 3C: 2; Par. 22) comprising
an insulative layer (Fig. 3C: 20; Par. 22) disposed between a lower metal layer (Fig. 3C: 22; Par. 22), a first upper metal layer (Fig. 3C: rightmost 21; Par. 22) and a second upper metal layer (Fig. 3C: center 21; Par. 22);
a semiconductor transistor die (Fig. 3C: 1; 20) disposed on the first upper metal layer;
an electrical connector (Fig. 3C: 3; Par. 36) connecting the semiconductor transistor die with the second upper metal layer;
a housing (Fig. 3C: 6; Par. 30) that forms an interior volume (Fig. 3C: volume enclosed by 61, 8, 62 & 20 less the volume occupied by 21, 25,1, 3, & 4) enclosing the insulating interposer and the semiconductor transistor die (As seen in Fig. 3C);
a first potting material (Fig. 3C: 51; Par. 42) locally encapsulating the semiconductor transistor die and the electrical connector (As seen in Fig. 3C);
and a second potting material (Fig. 3C: 52; Par. 42) completely filling the interior volume outside of the first potting material (As seen in Fig. 3C);
wherein the first and second potting materials are different from each other (Par. 42).
Regarding Claim 3,
HARTUNG discloses:
The semiconductor power module according to claim 1,
wherein the amount of the first potting material is less than the amount of the second potting material (As seen in Fig. 3C).
Regarding Claim 7,
HARTUNG discloses:
The semiconductor power module according to claim 1,
wherein the first potting material comprises a higher Young's modulus than the second potting material (Par. 42, where “modulus of elasticity” is known in the art to be synonymous with “Young’s Modulus”).
Regarding Claim 8,
HARTUNG discloses:
The semiconductor power module according to claim 1,
wherein the first potting material comprises an inorganic filled silicone.
(Par. 44 teaches 51 may be silicone, which may be filled with a “ceramic powder” where ceramic powders are known in the art to be inorganic.)
Regarding Claim 13,
HARTUNG discloses:
The semiconductor power module according to claim 1,
wherein the second potting material is based on one or more of a silicone gel, a resin, an epoxy resin, and an acrylate (Par. 47).
Regarding Claim 14,
HARTUNG discloses:
The semiconductor power module according to claim 1,
wherein the insulating interposer comprises one of a direct copper bond, an active metal braze or an insulated metal substrate (Par. 23).
Regarding Claim 20,
HARTUNG discloses:
The semiconductor power module according to claim 1,
wherein the first potting material forms a localized and continuous mass (As seen in Fig. 3C; Par. 12).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 & 5 are rejected under 35 U.S.C. 103 as being unpatentable over HARTUNG.
Regarding Claim 4,
HARTUNG does not explicitly disclose:
The semiconductor power module according to claim 1,
wherein the first potting material comprises a higher temperature stability than the second potting material.
However, HARTUNG does disclose that “in contrast to soft gels…the comparatively hard first [potting material] 51 does not tend to form bubbles/voids when it is heated” Par. 45. Further, HARTUNG discloses that the second potting material is “soft” Par. 49, may be a “gel” Par. 47, and has a “tendency to form bubbles”, Par. 48.
Regardless, one of ordinary skill in the art would have recognized the finite number of predictable means to order the temperature stability of the first potting material and the second potting material—i.e. the first potting material comprises a higher, lower, or equal temperature stability than the second potting material. As such, absent unexpected results, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to try all three possible means to order the temperature stability of the first potting material and the second potting material to determine which order is suitable for the associated and desired thermal management of the semiconductor power module (HARTUNG Par. 45 – 49).
Regarding Claim 5,
HARTUNG does not disclose:
The semiconductor power module according to claim 1,
wherein the second potting material comprises a higher creeping ability than the first potting material.
Regardless, one of ordinary skill in the art would have recognized the finite number of predictable means to order the creeping ability of the second potting material and the first potting material—i.e. the second potting material comprises a higher, lower, or equal creeping ability than the first potting material. As such, absent unexpected results, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to try all three possible means to order the creeping ability of the second potting material and the first potting material to determine which order is suitable for the associated and desired thermal management of the semiconductor power module (HARTUNG Par. 45 – 49).
Claims 6 & 9 – 10 are rejected under 35 U.S.C. 103 as being unpatentable over HARTUNG in view of TERAI (US 20150076517 A1).
Regarding Claim 6,
HARTUNG does not explicitly disclose:
The semiconductor power module according to claim 1,
wherein the first potting material comprises a higher thermal conductivity than the second potting material.
TERAI does not explicitly disclose:
wherein the first potting material (Fig. 1: 120; Par. 22) comprises a higher thermal conductivity than the second potting material (Fig. 1: 12; Par. 25).
However, TERAI Par. 22 does teach 120 may be a “silicone resin” in which “a ceramic powder is dispersed” as a means to “adjust [its] heat resistance”. Similarly, TERAI Par. 25 teaches 12 may be a “silicone resin” to which “a ceramic powder…is added” thereby also providing a means to adjust the heat resistance of 12. Further, “heat resistance” is known in the art to be the inverse and unnormalized value of “thermal conductivity”. Therefore, TERAI provides a means to adjust the thermal conductivity of the first potting material relative to and independent from the second potting material such that the first potting material comprises a higher, lower, or equal thermal conductivity compared to the second potting material.
Further, one of ordinary skill in the art would have recognized the finite number of predictable means to order the thermal conductivity of the first potting material and the second potting material—i.e. the first potting material comprises a higher, lower, or equal thermal conductivity than the second potting material. As such, absent unexpected results, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to try all three possible means to order the thermal conductivity of the first potting material and the second potting material to determine which order is suitable for the associated and desired thermal management of the semiconductor power module (TERAI Par. 22 – 25).
Regarding Claim 9,
HARTUNG does not disclose:
The semiconductor power module according to claim 1,
wherein one or both of the first and second potting materials are filled with particles out of the group containing A12O3, BN, AlN, Si3N4, and diamond.
TERAI discloses:
wherein one or both of the first (Fig. 1: 120; Par. 22) and second (Fig. 1: 12; Par. 25) potting materials are filled with particles out of the group containing A12O3, BN, AlN, Si3N4, and diamond (Par. 22 and Par. 25, respectively).
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of HARTUNG with those of TERAI to enable one or both of the first and second potting materials to be filled with particles out of the group containing A12O3, BN, AlN, Si3N4, and diamond—which are all known ceramic materials—in HARTUNG according to the teachings of TERAI, as HARTUNG discloses one or both of the first and second potting materials to be filled with ceramic particles (HARTUNG Par. 44) but not disclose which ceramic material(s) specifically. Therefore, a person having ordinary skill in the art would look to the prior art for specific ceramic material(s) recognized for their suitability and intended purpose (MPEP 2144.07). Further still, the ceramic materials of TERAI meet these criteria, as the semiconductor power module device structure, in general, and the disposition of the first and second potting materials, specifically, are substantially similar in both HARTUNG and TERAI.
Regarding Claim 10,
HARTUNG does not disclose:
The semiconductor power module according to claim 9,
wherein the second potting material comprises a higher amount of the particles than the first potting material.
TERAI does not explicitly disclose:
wherein the second potting material comprises a higher amount of the particles than the first potting material.
However, TERAI Par. 22 does teach 120 may be a “silicone resin” in which “a ceramic powder is dispersed” as a means to “adjust [its] heat resistance”. Similarly, TERAI Par. 25 teaches 12 may be a “silicone resin” to which “a ceramic powder…is added” thereby also providing a means to adjust the heat resistance of 12. Therefore, TERAI provides a means to adjust the heat resistance of the first potting material relative to and independent from the second potting material such that the second potting material comprises a higher, lower, or equal amount of particles than the first potting material.
Further, one of ordinary skill in the art would have recognized the finite number of predictable means to order the relative particle content of the second potting material and the first potting material—i.e. the second potting material comprises a higher, lower, or equal amount of particles than the first potting material. As such, absent unexpected results, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to try all three possible means to order the relative particle content of the second potting material and the first potting material to determine which order is suitable for the associated and desired thermal management of the semiconductor power module (TERAI Par. 22 – 25).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenneth S. Stephenson whose telephone number is (571)272-6686. The examiner can normally be reached Monday through Friday, 9 A.M. to 5 P.M. (EST)..
Examiner interviews are available via telephone and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview—preferably at 4 P.M. (EST)—applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.S.S./Examiner, Art Unit 2898
/JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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