Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Amendments to claims 1, 11, and 17 are acknowledged in the applicant’s reply dated 2 March 2026. Claims 21-24 have been added. Claim 9 was previously withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Iwata et al (US 20190296012 A1, hereinafter “Iwata”).
Regarding Claim 17 – Iwata discloses a semiconductor device comprising: a gate electrode (“Gate Electrode 1” or “Gate Electrode 2” in annotated Iwata Figure 27B, and 754 combined with 752P or 752N, as in Iwata [0051]); a spacer layer covering above the gate electrode and a sidewall of the gate electrode (Combination of 755, 756, and 761 in Iwata Figure 27B and [0054-0055]): a liner layer covering the gate electrode (762 in Iwata Figure 27B and [0055]) via the spacer layer; and a contact connected to the gate electrode (782G1 or 782G2, as described in Iwata [0087] as shown in Iwata annotated Figure 27B), wherein the contact includes: a conductive layer extending downward from above the liner layer, penetrating the spacer layer above the gate electrode, and reaching the gate electrode (782G1 or 782G2 extends from above 762 through 761 and connects to gate electrode layer 754 as shown in annotated Iwata Fig. 27B and described in [0087]); and an insulating layer (674C) covering a sidewall of the conductive layer, the insulating layer extending from above the liner layer to the liner layer and remaining on or in the liner layer (674C extends down to 762 as described in Iwata [0138] and shown in annotated Fig. 27B).
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Regarding Claim 18 – Iwata discloses all the limitations of claim 17.
Iwata further discloses the insulating layer is an oxide layer (674C is formed by layer 674L as described in Iwata [0138], and 674L is silicon oxide as stated in Iwata [0134]), and the liner layer is a nitride layer (Iwata [0055]).
Regarding Claim 19 – Iwata discloses all the limitations of claim 17.
Iwata further discloses comprising a cap layer (758 in [0051]) on the gate electrode, wherein the conductive layer penetrates the cap layer while being in direct contact with the cap layer on a side surface (Visible in Iwata Fig. 27B, 782 directly contacts 758 on the side), and is connected to the gate electrode (782G1 or 782G2 extends through layer 758 and connects to gate electrode layer 754 as shown in annotated Iwata Fig. 27B and described in [0087]).
Regarding Claim 20 – Iwata discloses all the limitations of claim 17.
Iwata further discloses the gate electrode is a gate electrode of a high- voltage N-channel transistor or a low-voltage P-channel transistor (The transistors described in Iwata [0143] can have various operating voltages, and the thicker gate oxides in Iwata Fig. 27B indicate higher operating voltage than in Figures 27A or 27C. Transistor 701 is PMOS and 702 is NMOS as described in Iwata [0048]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 10-16, 21-22, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Iwata et al (US 20190296012 A1, hereinafter “Iwata”), in view of Richter et al (US 20140264632 A1, hereinafter “Richter”).
Regarding Claim 1 – Iwata discloses a semiconductor device comprising: a first gate electrode (“Gate Electrode 1” in annotated Iwata Figure 27B, and 754 combined with 752P or 752N, as in Iwata [0051]); a second gate electrode (“Gate Electrode 2” in annotated Iwata Figure 27B, and 754 combined with 752P or 752N, as in Iwata [0051]); a first spacer layer covering the first gate electrode and sidewall of the first gate electrode (Combination of 755, 756, and 761 on Gate Electrode 1 in Iwata Figure 27B and [0054-0055]); a second spacer layer covering above the second gate electrode and sidewall of the second gate electrode (Combination of 755, 756, and 761 on Gate Electrode 2 in Iwata Figure 27B and [0054-0055]); a first liner layer covering the first gate electrode with the first spacer layer interposed therebetween (762 [0055] on Gate Electrode 1 with first spacer in-between, as shown in Fig. 27B); a second liner layer covering the second gate electrode with the second spacer layer interposed therebetween (762 [0055] on Gate Electrode 2 with first spacer in-between, as shown in Fig. 27B); a first contact (782G1, as described in Iwata [0087] as shown in Iwata annotated Figure 27B) including a first conductive layer (782 [0086]), the first conductive layer extending from above the first liner layer, penetrating the first spacer layer above the first gate electrode, and being connected to the first gate electrode (782G1 extends from above 762 through 761 and connects to gate electrode layer 754 as shown in annotated Iwata Fig. 27B and described in [0087]); and a second contact (782G2, as described in Iwata [0087] as shown in Iwata annotated Figure 27B) including a second conductive layer (782 [0086]), the second conductive layer extending from above the second liner layer, penetrating the second spacer layer above the second gate electrode, and being connected to the second gate electrode (782G2 extends from above 762 through 761 and connects to gate electrode layer 754 as shown in annotated Iwata Fig. 27B and described in [0087]), wherein the second conductive layer is in direct contact with the second spacer layer on a side surface (782 directly contacts 761 on a side surface in annotated Iwata Fig. 27B).
However, Iwata fails to disclose the first conductive layer is in contact with the first spacer layer on a side surface via a first insulating layer covering a sidewall of the first conductive layer.
Nonetheless, Richter discloses the first conductive layer (126 [0092]) is in contact with the first spacer layer (114 [0066]) on a side surface via a first insulating layer (124 [0091]) covering a sidewall of the first conductive layer (Richter [0091] and Fig. 17b).
Iwata and Richter both disclose MOSFET gate configurations concerned with improving reliability. Richter teaches separating the gate contact from other layers in order to prevent electrical shorting (Richter [0092]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to combine the teachings of Iwata and Richter to extend the contact insulating layer through the liner layer to directly contact the spacer layer on a side surface to achieve the expected outcome of preventing shorts between layers.
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Regarding Claim 2 – Iwata modified by Richter discloses all the limitations of claim 1.
The combination of Iwata and Richter further discloses the second contact includes a second insulating layer covering the second conductive layer above the second liner layer (674C extends from liner layer 762 upward, lining conductive layer 782, overlying the gate electrode as described in [0148] and annotated Iwata Fig. 27B).
Regarding Claim 3 – Iwata modified by Richter discloses all the limitations of claim 2.
The combination of Iwata and Richter further discloses the first insulating layer covers the first conductive layer from an upper side to a lower side of the first liner layer (124 is formed on the sidewalls of gate contact 120 as in Richer [0111], and extends completely through 114, as shown in Richter Figure 17b), and the second insulating layer extends from above the second liner layer to the second liner layer and remains on or in the second liner layer (674C extends down to 762 as described in Iwata [0138] and shown in annotated Fig. 27B).
Regarding Claim 4 – Iwata modified by Richter discloses all the limitations of claim 2.
The combination of Iwata and Richter further discloses the first and second insulating layers are oxide layers (674C is formed by layer 674L as described in Iwata [0138], and 674L is silicon oxide as stated in Iwata [0134]), and the first and second liner layers are nitride layers (Iwata [0056]).
Regarding Claim 5 – Iwata modified by Richter discloses all the limitations of claim 1.
The combination of Iwata and Richter further discloses the semiconductor device according to claim 1, further comprising first and second cap layers (758 [0051]) on the first and second gate electrodes (as described in Iwata [0051]), respectively, wherein the first and second conductive layers penetrate the first and second cap layers and are connected to the first and second gate electrodes, respectively (as seen in annotated Iwata Fig. 27B).
Regarding Claim 6 – Iwata modified by Richter discloses all the limitations of claim 5.
The combination of Iwata and Richter further discloses the first insulating layer reaches a predetermined depth of the first cap layer (Cap layer considered to be layer 114 in Richter Fig. 17b, penetrated by insulating layer 124, which is only removed from the bottom of the contact vias, as explained in Richter [0091).
Regarding Claim 7 – Iwata modified by Richter discloses all the limitations of claim 5.
The combination of Iwata and Richter further discloses the second conductive layer is in direct contact with the second cap layer on the side surface (Visible in Iwata Fig. 27B, 782 directly contacts 758 on the side).
Regarding Claim 8 – Iwata modified by Richter discloses all the limitations of claim 1.
The combination of Iwata and Richter further discloses the second conductive layer is in direct contact with the second liner layer on the side surface over an entire thickness direction of the second liner layer (Oxide liner 674C sits on top of the silicon nitride layer 762 as in Iwata [0138], leaving the full thickness of layer 762 to contact the gate contact 782G1 as in Iwata Fig. 27B).
Regarding Claim 10 – Iwata modified by Richter discloses all the limitations of claim 1.
The combination of Iwata and Richter further discloses the first gate electrode is a gate electrode of a high-voltage P-channel transistor, and the second gate electrode is a gate electrode of a high-voltage N-channel transistor or a low-voltage P- channel transistor (The transistors described in Iwata [0143] can have various operating voltages, and the thicker gate oxides in Iwata Fig. 27B indicate higher operating voltage than in Figures 27A or 27C. Transistor 701 is PMOS and 702 is NMOS as described in Iwata [0048]).
Regarding Claim 11 – Iwata discloses a semiconductor device comprising: a first gate electrode (“Gate Electrode 1” in annotated Iwata Figure 27B, and 754 combined with 752P or 752N, as in Iwata [0051]); a second gate electrode (“Gate Electrode 2” in annotated Iwata Figure 27B, and 754 combined with 752P or 752N, as in Iwata [0051]); a first spacer layer covering the first gate electrode and sidewall of the first gate electrode (Combination of 755, 756, and 761 on Gate Electrode 1 in Iwata Figure 27B and [0054-0055]); a second spacer layer covering above the second gate electrode and a sidewall of the second gate electrode (Combination of 755, 756, and 761 on Gate Electrode 2 in Iwata Figure 27B and [0054-0055]); a first liner layer covering the first gate electrode via the first spacer layer (762 [0055] on Gate Electrode 1 with first spacer in-between, as shown in Fig. 27B); a second liner layer covering the second gate electrode with the second spacer layer interposed therebetween (762 [0055] on Gate Electrode 1 with first spacer in-between, as shown in Fig. 27B); a first contact connected to the first gate electrode (782G1, Iwata [0087] and annotated Figure 27B); and a second contact connected to the second gate electrode (782G2, Iwata [0087] and annotated Figure 27B), wherein the first contact includes: a first conductive layer extending downward from above the first liner layer, penetrating the first spacer layer above the first gate electrode, and reaching the first gate electrode (782G1 extends through layer 761 and connects to gate electrode layer 754 as shown in annotated Iwata Fig. 27B and described in [0087]); and a first insulating layer covering a sidewall of the first conductive layer (674C, as described in Iwata [0138]), and the second contact includes: a second conductive layer extending downward from above the second liner layer, penetrating the second spacer layer above the second gate electrode, and reaching the second gate electrode (782G2 extends through layer 761 and connects to gate electrode layer 754 as shown in annotated Iwata Fig. 27B and described in [0087]); and a second insulating layer covering a sidewall of the second conductive layer, the second insulating layer extending from above the second liner layer to the second liner layer and remaining on or in the second liner layer (674C extends from liner layer 762 upward, lining conductive layer 782, overlying the gate electrode as described in [0148] and shown in annotated Iwata Fig. 27B).
Iwata does not disclose (the first insulating layer) extending downward from above the first liner layer.
However, Richter teaches (the first insulating layer) extending downward from above the first liner layer (124 is formed on the sidewalls of gate contact 120 as in Richer [0111], and extends completely through 114, as shown in Richter Figure 17b).
Iwata and Richter both disclose MOSFET gate configurations concerned with improving reliability. Richter teaches using a liner to separate the gate contact from other layers, preventing electrical shorting (Richter [0092]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to combine the teachings of Iwata and Richter to extend the contact insulating layer through the liner layer to directly contact the spacer layer on a side surface to achieve the expected outcome of preventing shorts between layers.
Regarding Claim 12 – Iwata modified by Richter discloses all the limitations of claim 11.
Iwata modified by Richter further discloses the first and second insulating layers are oxide layers (674C is formed by layer 674L as described in Iwata [0138], and 674L is silicon oxide as stated in Iwata [0134]), and the first and second liner layers are nitride layers (Iwata [0055]).
Regarding Claim 13 – Iwata modified by Richter discloses all the limitations of claim 11.
Iwata modified by Richter further discloses comprising first and second cap layers (758) on the first and second gate electrodes (as described in Iwata [0051]), respectively, wherein the first and second conductive layers penetrate the first and second cap layers and are connected to the first and second gate electrodes, respectively (as seen in annotated Iwata Fig. 27B and explained in Iwata [0144]).
Regarding Claim 14 – Iwata modified by Richter discloses all the limitations of claim 13.
Iwata modified by Richter further discloses the first insulating layer reaches a predetermined depth of the first cap layer (The insulating layer 124 is formed in the contact hole, and can extend the entire depth of the contact 126 as in Richter [0111], thus penetrating the depth of the cap layer).
Regarding Claim 15 – Iwata modified by Richter discloses all the limitations of claim 13.
Iwata modified by Richter discloses the second conductive layer is in direct contact with the second cap layer on the side surface (Visible in Iwata Fig. 27B, 782 directly contacts 758 on the side, and contact via cavities extend through dielectric portions 758 as in Iwata [0141]).
Regarding Claim 16 – Iwata modified by Richter discloses all the limitations of claim 11.
Iwata modified by Richter further discloses the first gate electrode is a gate electrode of a high-voltage P-channel transistor, and the second gate electrode is a gate electrode of a high-voltage N-channel transistor or a low-voltage P- channel transistor (The transistors described in Iwata [0143] can have various operating voltages, and the thicker gate oxides in Iwata Fig. 27B indicate higher operating voltage than in Figures 27A or 27C. Transistor 701 is PMOS and 702 is NMOS as described in Iwata [0048]).
Regarding Claim 21 – Iwata modified by Richter discloses all the limitations of claim 1.
The combination of Iwata and Richter further discloses the first and second spacer layers respectively contact the first and second gate electrodes (as shown in Iwata Fig. 27B).
Regarding Claim 22 – Iwata modified by Richter discloses all the limitations of claim 11.
The combination of Iwata and Richter further discloses the first and second spacer layers respectively contact the first and second gate electrodes (as shown in Iwata Fig. 27B).
Regarding Claim 24 – Iwata modified by Richter discloses all the limitations of claim 22.
The combination of Iwata and Richter further discloses the first and second liner layers respectively extend laterally over the upper surface of the first and second gate electrodes with the first and second spacer layers disposed respectively therebetween (as shown in Iwata Fig. 27B).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Iwata et al (US 20190296012 A1, hereinafter “Iwata”), in view of Richter et al (US 20140264632 A1, hereinafter “Richter”), and further in view of Togo et al (US 20220399448 A1, hereinafter “Togo”), and further in view of Iwata et al (US 20220359690 A1, hereinafter “Iwata2”), and further in view of Wang et al (CN 103500760 B, hereinafter “Wang”).
Regarding Claim 23 – Iwata modified by Richter discloses all the limitations of claim 22.
The combination of Iwata and Richter fails to disclose the first and second spacer layers are formed of a single, continuous material in contact with side surfaces of the first and second gate electrodes and extend laterally over an upper surface of the first and second gate electrodes, respectively.
However, Togo (Spacer 78G on MOSFET D, [0096] and Fig. 16), Iwata2 (Spacers in Fig. 46B, [0176]), and Wang (10 [0022] and Fig. 1) all disclose spacer layers formed of a single, continuous material in contact with side surfaces of the gate electrode and extending laterally over an upper surface of the gate electrode.
Togo, Iwata2, and Wang all disclose analogous planar MOSFETs to Iwata. Togo, Iwata2, and Wang teach a spacer layer formed of a single, continuous material in contact with side surfaces of the gate electrode and extending laterally over an upper surface of the gate electrode, instead of a multi-layered spacer layer. A single, continuous material forming the spacer layer is therefore a known equivalent to a multi-layer spacer layer. See MPEP 2144.06(II). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider combining the teachings of Iwata and Togo, Iwata2, or Wang, to form a spacer layer of a single, continuous material in contact with side surfaces of the gate electrode and extending laterally over an upper surface of the gate electrode.
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Response to Arguments
Applicant asserts layer 761 is not described as being etched to form a spacer. However, the claims relate to device structure rather than method.
Applicant asserts 756 and 761 in combination do not contact the gate electrode. However, the combination of 755, 756, and 761 as necessitated by amendment does contact the gate electrode as described above.
Conclusion
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/JASON MCDONALD/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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